JPH0563183U - Video signal processing circuit for both NTSC and PAL video tape recorders - Google Patents

Abstract

(57) [Abstract] [Purpose] NTSC using one 1H delay line
Provided is a video signal processing circuit of a video tape recorder for both NTSC system and PAL system, which can realize 1H delay of the system and PAL system video signals. A video signal processing circuit for processing an NTSC video signal having a first color subcarrier frequency and a PAL video signal having a second color subcarrier frequency, and an NTS
In response to the C format video signal and the PAL format video signal,
First and second control signals NTSC (H) and PAL
And a control microprocessor for generating (H). The video signal processing circuit generates a clock signal (2fsc) having a frequency twice as high as the first and second color subcarrier frequencies, and is responsive to the first and second control signals from the control microprocessor. hand,
A clock supply circuit 32 for generating first and second clock signals, and a video signal from the video signal processing circuit 2 is delayed by 1H in response to the first and second clock signals, and the delayed video signal is video signal processed. Delay line means for feeding the circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a video signal processing circuit for a video tape recorder, and in particular, realizes 1H delay of an NTSC or PAL video signal having different color subcarriers by using one 1H delay line. The present invention relates to a video signal processing circuit of a video tape recorder for both NTSC and PAL systems.

[0002]

[Problems to be solved by conventional techniques and devices]

 The video processing circuit of the video tape recorder compensates for physical damage to the cassette tape or dropout phenomenon of the video signal or removes line noise when reproducing the video signal recorded on the cassette tape. In addition, a delay line for delaying the luminance signal included in the video signal by 1H is provided. Recently, charge-coupled devices have been used as such delay lines. Also, the delay line using the charge coupled device includes a low pass filter. The low pass filter provides an additional delay such that the delay line has a total 1H delay and removes the clock leakage component due to the integrated circuit characteristics of the delay element to prevent distortion.

In the video processing circuit of the video tape recorder for both NTSC and PAL video signals, since the NTSC video signal and the PAL video signal use different color subcarriers, different 1H time intervals are set. Inevitably, in order to provide the 1H delay time for the two methods, a delay line having a 1H delay with a different time interval is used. A schematic block diagram of a video signal processing circuit of such a conventional NTSC and PAL system video tape recorder is shown in FIG.

As shown in the figure, the video signal processing circuit is integrated with the video signal processing integrated circuit 2 by the control signals (NTSC (H)) and (PAL (H)). It comprises an oscillation circuit 3 which provides clocks of different oscillation frequencies, a first delay line 11 and a second delay line 12.

The first delay line 11 and the second delay line 12 delay the video signal from the video signal processing integrated circuit 2, that is, the luminance signal by 1H by the NTSC video signal or the PAL video signal. To work selectively. The selective operation is performed by the selective switching operation of the switching circuits 13 and 14 according to the control signals (NTSC (H)) and (PAL (H)), which causes different color sub-signals from the integrated circuit 2 for video signal processing. A clock (2fsc) having a frequency twice the carrier frequency (fsc) is selectively supplied to the first and second delay lines 11 and 12. The first and second delay circuits 11 and 12 each include an NTSC charge-coupled device integrated circuit 4, a PAL charge-coupled device integrated circuit 6, and low-pass filters 8 and 9. The control signals (NTSC (H)) and (PAL (H)) are provided by a control microprocessor, not shown.

The oscillation circuit 3 includes a first oscillating unit 15 that operates according to a control signal (NTSC (H)) and a second oscillating unit 16 that operates according to a control signal (PAL (H)). The first oscillating unit is used for NTSC video signal processing and outputs a sine wave clock signal having a color subcarrier frequency of the NTSC video signal, for example, a frequency of 3.579545 MHz. The second oscillating unit is used for PAL video signal processing, and outputs a sine wave clock signal having a color subcarrier frequency of the PAL video signal, for example, a frequency of 4.433619 MHz. ..

As described above, according to the conventional video signal processing circuit, when the control microprocessor outputs the control signal (NTSC (H)), the oscillation circuit 3 outputs the clock signal having the frequency of 3.579545 MHz. The charge-coupled device integrated circuit 4 is supplied to the image processing integrated circuit 2, and the charge-coupled device integrated circuit 4 has a frequency twice as high as the frequency of the color subcarrier of the NTSC system, that is, 7.1590 MHz by the operation of the switch circuit 13. A clock signal is provided. The luminance signal from the video signal processing circuit 2 is input to the charge-coupled device integrated circuit 4. As a result, the luminance signal is delayed by 1H by the operation of the charge coupling element integrated circuit 4 and the operation of the low pass filter 8 and is further supplied to the video signal processing integrated circuit 2 for the next processing.

When a control signal (PAL (H)) is output by the control microprocessor, a clock signal having a frequency of 4.433619 MHz is supplied from the oscillation circuit 3 to the video signal processing integrated circuit 2, and a switch is provided. By the operation of the circuit 14, a clock signal having a frequency twice that of the PAL color subcarrier from the terminal (2fsc) of the video processing integrated circuit 2, that is, a frequency of 8.8672375 MHz is supplied to the charge coupled device integrated circuit 5. Is supplied to. On the other hand, a luminance signal is input to the charge-coupled device integrated circuit 5 from the video signal processing integrated circuit 2. As a result, the luminance signal is delayed by 1H by the operation of the charge-coupled element integrated circuit 5 and the operation of the low-pass filter 10 and is further supplied to the video signal processing integrated circuit 2 for the next processing.

As can be seen from the above description, the image processing circuit of the conventional NTSC and PAL system dual-purpose video tape recorder includes two delay lines that operate individually according to each broadcasting system. Therefore, the conventional video processing circuit additionally includes a charge coupled device integrated circuit and a low pass filter as a delay line, which increases the cost of the video tape recorder and complicates the manufacturing process. there were.

Therefore, an object of the present invention is to provide a video signal processing circuit for an NTSC / PAL type video tape recorder which can delay 1H for both NTSC and PAL type video signals with one delay line. To provide.

[0011]

[Means for Solving the Problems]

 According to the present invention, a video signal processing circuit for processing an NTSC video signal having a first color subcarrier frequency and a PAL video signal having a second color subcarrier frequency, the NTSC video signal and An image of a video tape recorder for both NTSC and PAL systems including control means for generating the first and second control signals (NTSC (H)) and (PAL (H)) according to the PAL system video signal. In the signal processing circuit, a clock signal (2fsc) having a frequency corresponding to twice the first and second color subcarrier frequencies from the video signal processing circuit is generated, and the first and second signals from the control means are generated. Clock supply means for generating first and second clock signals in response to a second control signal; and a clock supply means for responding to the first and second clock signals. The video signal processing circuit of the video tape recorder of the video signal from the video signal processing circuit by the 1H delay and a delay line means for coupling said delayed video signal to the video signal processing circuit is provided.

[0012]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a schematic block diagram of a delay line of a general form. As shown in FIG. 1, the delay line receives an input of a luminance signal from the video signal processing integrated circuit 2. A low pass filter 21, a charge coupled device integrated circuit 4 for delaying a preset time by inputting a luminance signal from the input low pass filter 21 and a clock signal from the video signal processing integrated circuit 2; 6 and output low-pass filters 8 and 9 for inputting the brightness signals from the charge-coupled device integrated circuits 4 and 6 to remove additional delay and signal distortion.

The charge coupled device integrated circuits 4 and 6 include a clock generation circuit 22, a first amplifier 23, an input bias unit 24, a charge coupled device unit 25, a sampling / holding unit 26, and a second amplifier 27. Composed.

The clock generation circuit 22 inputs the sinusoidal clock signal from the video signal processing integrated circuit 2 of FIG. 1 to shape the waveform, and the input bias unit 24, the charge coupled device unit 25 and the sampling / sampling unit An optimum pulse is supplied to each hold unit 26.

The input bias unit 24 is a circuit for providing an appropriate bias for analog signal processing of the charge coupled device unit 25, and the sampling / holding unit 26 and the second amplifier 27 are connected to the charge coupled device unit 25. The clock component included in the luminance signal output from is extracted and amplified to an appropriate level. In this case, a linear amplifier is used as the second amplifier.

The charge coupled device section 25 includes an input section 51, a transmission section 52, and an output section 53. The input unit 51 inputs an electrical signal from the input bias 24, samples the signal, converts the sampled signal into an equivalent charge amount, and outputs the equivalent charge amount to the transmission unit 52.

The transmission unit 52 includes a predetermined transmission stage, and in response to a signal input through the clock pulse generation circuit 22 and the first amplifier 23, the electric charge from the input unit 51 is transmitted through the transmission stage. Transmit sequentially. Here, the transmission time of the transmission unit 52 is determined by the number of transmission stages. Charge-coupled device integrated circuits that are generally commercially available include 453 bit transmission stages for the NTSC system and 565 transmission stages for the PAL system charge-coupled device integrated circuit.

The total delay time when the charge coupled device integrated circuit is used as a delay line, that is, the transmission time (Tn) is calculated as follows. That is, when the charge-coupled device integrated circuit for the NTSC system is used, the transmission time (Tn) = the number of transmission stages of the transmission part × 1 / clock frequency = 453 × 1/2 fsc = 453 × 7.1590 MHz = 63.276 μs. However, in reality, the sampling / holding unit 26, which is the next stage of the charge-coupled device unit 52, delays one stage more, so that the actual number of transmission stages of the charge-coupled device integrated circuit is 453. Become. Therefore, the transmission time (Tn) becomes 63.415 μs. On the other hand, in the case of the whole delay line, in the case of NTSC, 1 H is 63.556 μs, which is short of about 140 ns. Such 140 ns can be delayed by a delay filter coupled to the rear end of the charge coupled device integrated circuit, and a delay of 1H can be realized in the entire delay line.

Even when the charge coupled device integrated circuit for the PAL system is used, the number of transmission stages is 566 if the sampling / hold unit 26 is taken into consideration.

Transmission time (Tp) = 566 × 1/2 fsc = 566 × 1 / 8.867238 MHz = 63.83 μs In the case of the PAL system, 1H is 64 μs, so a delay of about 170 ns is insufficient. Therefore, the delay time of the low-pass filter coupled to the rear end of the charge-coupled device integrated circuit must be designed to be 170 μs. The output unit 53 converts the charge from the transmission unit 52 into a voltage and provides the voltage to the sampling / holding unit 26.

FIG. 3 shows a video signal processing circuit of a video tape recorder for both NTSC and PAL systems according to the present invention. The video signal processing circuit includes a video signal processing integrated circuit 2 for processing video signals of NTSC and PAL systems, an oscillation circuit 3, a delay line 11, and a clock supply circuit 32.

The video signal processing integrated circuit 2 and the oscillating circuit 3 perform the same functions as those of the circuit of the general form described above, and are therefore assigned the same reference numerals. The delay line 11 includes the charge coupled device integrated circuit 4 for the NTSC system and the low pass filter 8.

The clock supply circuit 32 includes a switch unit 33 and a clock generation unit 34. The switch unit 33 supplies the sine wave clock (2fsc) of the video signal processing integrated circuit 2 to the charge coupling element integrated circuit 4 for the NTSC system in response to the control signal NTSC (H) or PAL (H). Alternatively, the clock signal from the clock generator 34 is supplied to the charge coupled element integrated circuit 4.

Switch unit 33 includes transistors Q1 and Q2 driven by control signals NTSC (H) and PAL (H), respectively. The control signal NTSC (H) is supplied to the collector of the transistor Q1 and the base of the transistor Q1 through the current limiting resistor R2, and the control signal PAL (H) is supplied to the collector of the transistor Q2 and the voltage dividing resistors R4 and R5. It is supplied to the base of the transistor Q2. The emitters of the transistors Q1 and Q2 are coupled to the ground through the current limiting resistor R5, and are coupled to the clock terminal CLK of the charge coupled device integrated circuit 4 as the output of the switch unit 33. The base of the transistor Q1 is coupled to the clock (2fsc) of the video signal processing integrated circuit 2 through the mute circuit 36 including the diode D 1 and the transistor Q4 and the waveform shaping circuit 35 including the coupling capacitor C1 and the resistor R1. , The base of the transistor Q1 is coupled to the output of the clock generator 34 through a waveform shaper 36 including a capacitor C2, a resistor R6 and a capacitor C3. The clock generator 34 is operated by the control signal PAL (H) and has a transistor Q3, resistors R7, R8, R9, capacitors C4, 5 and a crystal oscillator X. The clock generator 34 generates a sine wave clock having a frequency of 7.10919 MHz in this embodiment.

When the control microprocessor (not shown) senses the control signal of the cassette tape, determines the broadcasting system, and outputs the control signal NTSC (H), the integrated circuit for video signal processing. A clock (2fsc) signal, that is, a sine wave clock signal having a frequency of 7.1590 MHz is supplied from the end of the second clock (2fsc) to the base of the transistor Q1 through the waveform shaping circuit 35 and the mute circuit 36. Such a sinusoidal clock signal is input to the clock terminal CL K of the charge-coupled device integrated circuit 4 by the operation of the transistor Q1 that operates according to the control signal NTSC (H). On the other hand, as described above, the luminance signal is input from the video signal processing integrated circuit 2 to the charge coupled device integrated circuit 4. As can be seen from the above formula, this luminance signal is delayed by 63.415 μs from the charge-coupled device integrated circuit 4 and further delayed by 140 μs by the low-pass filter 8 for a total of 1H, that is, 63.556 μs. Will be. The luminance signal delayed by 1H in this manner is supplied to the video signal processing integrated circuit 2 for the next processing.

When the control microprocessor senses the control signal to the cassette tape, determines the broadcasting method, and outputs the control signal PAL (H), the clock (2fsc) of the integrated circuit 2 for video signal processing is used. ) Signal, that is, a sinusoidal clock signal having a frequency of 8.86238MHz is supplied to the transistor Q2 through the waveform shaping circuit 35. However, the clock (2fsc) signal is bypassed to the ground by the mute circuit 36 operated by the control signal PAL (H). Instead, a sine wave clock having a frequency of 7.109919 MHz is supplied from the clock generator 32 to the base of the transistor Q2 through the waveform shaping circuit 35. Such a sine wave clock is input to the clock terminal CLK of the charge coupled device integrated circuit 4 by the transistor Q2 operated by the control signal PAL (H). On the other hand, as described above, the luminance signal is input from the video signal processing integrated circuit 2 to the charge coupled device integrated circuit 4. The luminance signal delay time in the charge coupled device integrated circuit 4 can be calculated as follows.

Delay time (Tp) = 454 × 1 / 7.109919 MHz = 63.86 μs Since 140 μs is delayed by the low-pass filter 8, the total delay becomes 64 μs. This indicates a delay of 1H of the PAL system video signal, and the luminance signal delayed by 1H is supplied to the video signal processing integrated circuit 2 for subsequent processing.

[0029]

[Effect of the device]

 As can be seen from the above description, according to the present invention, regardless of the NTSC system or the PAL system, only one delay line integrated circuit is used and only one delay line is used for both broadcasting systems. Can be delayed by 1H. Therefore, if the video signal processing circuit according to the present invention is used, it is not necessary to separately configure the 1H delay line in the video tape record for both the NTSC system and the PAL system, so that the manufacturing cost is significantly reduced. The effect is that the number of video signals can be reduced, and the video signal processing circuit can be configured very easily.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a video processing circuit of a conventional NTSC system and PAL system video tape recorder.

FIG. 2 is a schematic block diagram showing a basic charge-coupled device integrated circuit.

FIG. 3 is a circuit diagram showing a video signal processing circuit of a video tape recorder for both NTSC system and PAL system according to the present invention.

[Explanation of symbols]

 2 integrated circuit for video signal processing 3 oscillator circuit 4 charge-coupled device integrated circuit 8 low-pass filter 11 delay line 32 clock supply circuit 33 switch section 34 clock generation section

Claims (2)

[Scope of utility model registration request] 1. An NTSC having a first color subcarrier frequency.
System video signal and PAL having second color subcarrier frequency
A video signal processing circuit for processing the video signal of the H.264 system and first and second control signals (NTSC (H)) and (PAL (H)) according to the video signal of the NTSC system and the video signal of the PAL system. Including control means for generating
In a video signal processing circuit of a video tape recorder for both SC and PAL systems, a clock signal (2fsc) having a frequency corresponding to twice the first and second color subcarrier frequencies from the video signal processing circuit is generated. At the same time, clock supply means for generating first and second clock signals in response to the first and second control signals from the control means, and the video signal processing in response to the first and second clock signals Delay line means for delaying the video signal from the circuit by 1H and coupling the delayed video signal to the video signal processing circuit.
Video signal processing circuit for TSC and PAL video tape recorders. 2. The delay line means includes a charge coupled device integrated circuit having 453 transmission stages and a low pass filter having a delay of 140 ns, and the clock supply means has a clock having a 7.10919 MHz frequency. Clock generating means for generating a signal, and the first control signal (N
The clock signal (2fsc) having a frequency twice as high as the first color subcarrier frequency is coupled to a clock terminal (CLK) of the charge coupled device integrated circuit according to TSC (H)), and 2. The NTSC system and the PAL system according to claim 1, comprising switch means for coupling the clock signal from the clock generation means to a clock terminal (CLK) of the charge-coupled device integrated circuit according to a control signal (PAL (H)). Video signal processing circuit for dual-purpose video tape recorder.