JPS5843315Y2 - video clamp circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a video clamp circuit that can be applied to a satellite broadcast receiving device using the SHF band.

In the satellite broadcasting system, frequency modulation is performed on the television signal, but in this case it is undesirable if carrier wave energy concentrates.

For example, if the television signal has a black level, the carrier wave energy will be concentrated at a frequency corresponding to the black level.

If the concentration of carrier wave energy is large in this way, cross-modulation may occur due to the nonlinearity of the amplifier when multiple FM waves are amplified, and interference with adjacent channels may easily occur.

For this reason, a symmetric triangular wave (energy spread signal) with a uniform distribution of carrier wave energy within a frequency shift is superimposed on the television signal, and FM modulation is performed to spread the carrier wave energy.

Therefore, on the receiving device side, it is necessary to demodulate the FM television signal, remove the spread signal, and restore the original television signal.

A television signal with energy spreading is shown in FIG.

1 is a vertical synchronization signal, and a triangular wave voltage 2 is superimposed as an energy diffusion signal.

The frequency of this triangular wave voltage 2 is 30 Hz, and a clamp method can be considered as one method for removing it.

FIG. 2 shows the basic circuit of a well-known peak clamp circuit using diodes.

3 and 4 of this circuit are input terminals, into which a video signal on which a triangular wave voltage is superimposed is inputted via a capacitor C1.

R1 is the impedance of the signal source, R2 is the load impedance, and R4<CR2.

C1 is a capacitor interposed between the signal source and load R2, and Dl is a clamping diode arranged between the voltage source 10 and the connection point between capacitor C1 and load R2.

Now, when a video signal is supplied through the input terminal 3, the diode D1 becomes conductive in response to horizontal and vertical synchronization signals.

As the diode D1 conducts, the peak level of these synchronizing signals is clamped to the output voltage vc of the voltage source 10.

However, the clamping diode D1 does not operate as an ideal switch because it has internal impedance.

On the other hand, an energy diffusion signal (30 Hz triangular wave voltage) is superimposed on the video signal, and when the diffusion signal voltage is applied to the diode, a voltage change occurs due to the internal impedance of the diode D1, and the energy diffusion signal cannot be removed sufficiently.

Therefore, the capacitance value of the coupling capacitor C1 is selected to be small, and this clamp circuit is given high-pass characteristics, and the energy spread signal applied to the diode D1 is removed (30Hz triangular wave voltage).
By reducing this, it is possible to improve the effect of removing the energy diffusion signal superimposed on the video signal.

However, the period of the vertical synchronization signal also has low frequency components like the energy spread signal, so if the clamp circuit has the above-mentioned high-pass characteristics, sufficient signal transmission will not be possible during the vertical synchronization signal period, and the vertical synchronization signal Sag 5 occurs after 1.

The principle of generation of this sag 5 will be explained in more detail with reference to FIG.

If the charging/discharging time constant is sufficiently long compared to the period of the vertical synchronizing signal, the voltage e1 across the capacitor C1 is approximately 01, assuming that the peak value voltage of the vertical synchronizing signal is 02.

It is expressed as □−■. However, if the charging/discharging time constant is small, the capacitor will be fully charged during the vertical synchronization signal period T1, and the diode D1 will become non-conductive.

When the diode D1 becomes non-conductive, the capacitor CI starts charging through the load R2 during the vertical synchronization signal period T2 that follows, and the voltage e1 across the capacitor C1 becomes e2-v.
c becomes larger, and the load R2 begins to decrease.

If the voltage drop during the vertical synchronization signal period is △e, then at the falling edge of the vertical synchronization signal, the reference level at the rising edge is A (Figure 3).
The signal level is lowered by Δe.

Therefore, the peak value of the horizontal synchronizing signal for a certain period following the vertical synchronizing signal does not reach the level that makes the diode D1 conductive due to this decrease in level, so that no clamping operation is performed.

Therefore, the capacitor C1 continues discharging with the time constant of CX (R1+R2) in the case of el-"e2'c.

Then, when e2 becomes Vc during e1, the peak level of the horizontal synchronizing signal reaches a level that makes the diode D1 conductive (point t□ in FIG. 3), so a normal clamping operation is started.

In this way, sag 5 occurs after vertical synchronization signal 1.

The present invention improves the clamp circuit shown in FIG. 2 to eliminate the above-mentioned sag, and its basic circuit is shown in FIG. 4.

The difference between the circuit in Fig. 4 and the circuit in Fig. 2 is that the clamping diode D
A sufficient voltage is applied to the anode of 1 for lamp operation.

This voltage is obtained by separating the vertical synchronization signal.

As shown in Figure 5, by adding a separate synchronization signal port to the vertical synchronization signal period A of the video signal to be clamped, the diode D1 can be reliably connected to the video signal from a different path from the signal path of the video signal during the vertical synchronization signal period. A voltage is applied to make it conductive.

Therefore, the diode D1 does not become non-conductive during the vertical synchronization signal period, so the voltage e1 across the capacitor C1 is e1 ÷ e
Maintained at 2 Vc.

That is, the voltage drop △e mentioned above during the vertical synchronization signal period is △
Since the state of e=o is maintained, before the vertical synchronization signal period,
The signal level in the subsequent period is kept equal, and the vertical synchronizing signal is normally clamped during the vertical synchronizing signal period as shown by the broken line in A.

Therefore, the peak level of the horizontal synchronizing signal following the vertical synchronizing signal is also taken out as a signal without any sag in order to maintain the conduction level of the diode D1.

FIG. 6 is an actual circuit diagram to which the present invention is applied.

Q1 to Q4 are transistors for video amplification, and resistors R1 and R18 are connected to the cathode of the clamping diode D1.
, a clamp voltage is provided by capacitor C12.

6 is a synchronization separation circuit that takes out a vertical synchronization signal, and the vertical synchronization signal is obtained through a low-pass filter consisting of a resistor R2□ and a capacitor C16.
6 switches 10B voltage.

A positive pulse corresponding to the vertical synchronizing signal appearing at the collector of transistor Q6 is divided by resistors R29+R30VC and applied to the clamp circuit via capacitor C2.

In this case, the time constant of the synchronization separation circuit is determined so that a portion of the horizontal synchronization signal is included in the positive pulse, and the resistor R29
By selecting an appropriate voltage division ratio between R30 and R30, the horizontal synchronization signal between the vertical synchronization intervals can also be reproduced as a complete signal without distortion.

As described above, this proposal provides high-pass characteristics to the peak clamp circuit that couples the video signal to the clamping diode using a capacitor, and sufficiently removes the energy spread signal with a frequency lower than the field frequency that is superimposed on the video signal. In addition, by holding the clamping diode in a conductive state when the vertical synchronizing signal of the video signal arrives, it has the excellent effect of preventing the sag that occurs during and after the vertical synchronizing signal. .

The residual clamp circuit of the present invention can also be applied to a normal television receiver to eliminate airplane fluff.

[Brief explanation of the drawing]

Figure 1 is a schematic waveform diagram showing an SHF broadcast television signal superimposed with an energy diffusion wave, Figure 2 is a basic circuit diagram of a conventional video clamp, and Figure 3 is a triangular waveform of the signal in Figure 1 using the circuit in Figure 2. 4 is a basic circuit diagram of the clamp circuit of the present invention, FIG. 5 is a waveform diagram for explaining the operation of FIG. 4, and FIG. 6 is an example of the present invention. It is a circuit diagram concerning. C1... Coupling capacitor, Dl... Clamping diode, 6... Synchronous separation circuit.

Claims (1)

[Scope of utility model registration request] A video signal is coupled to one end of a clamping diode via a capacitor, the other end of the diode is held at a predetermined voltage, and the diode is made conductive in accordance with a synchronization signal of the video signal to adjust the synchronization level of the video signal. In the peak clamp circuit that clamps to the predetermined voltage, when a signal with a frequency lower than the field frequency is superimposed on the video signal, a voltage is applied to one end of the diode to make the diode conductive only during the vertical synchronization period. A video clamp circuit that performs a clamping operation to remove a signal having a frequency lower than the field frequency without damaging a vertical synchronizing signal of a video signal output.