JPH0563003A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0563003A
JPH0563003A JP24661491A JP24661491A JPH0563003A JP H0563003 A JPH0563003 A JP H0563003A JP 24661491 A JP24661491 A JP 24661491A JP 24661491 A JP24661491 A JP 24661491A JP H0563003 A JPH0563003 A JP H0563003A
Authority
JP
Japan
Prior art keywords
gate
recess
nitride film
deposited
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24661491A
Other languages
Japanese (ja)
Inventor
Yukiko Yamaguchi
由紀子 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24661491A priority Critical patent/JPH0563003A/en
Publication of JPH0563003A publication Critical patent/JPH0563003A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a cavity (hollow region) within a recess in a field effect transistor having a recessed structure in order to eliminate a disadvantage that if the recess is filled with a passivation film, the capacitance between a gate and a drain increases, lowering a power gain. CONSTITUTION:A silicon oxide film 2 and a silicon nitride film 3 as a spacer are deposited on an n type active layer 1, these films are patterned with a photoresist 10, thereafter a recess 5 is opened by dry etching and wet etching (process A), the recess is formed and after formation of a gate (process B), a cavity 9 is formed within the recess 5 (process C). Thereby, power gain in the high frequency characteristic can be improved without increasing a capacitance value between the gate and drain.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特にリセス構造を有する電界効果トランジスタ
のゲ−ト部形成方法に係る半導体装置の製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device according to a method of forming a gate portion of a field effect transistor having a recess structure.

【0002】[0002]

【従来の技術】従来のリセス構造タイプのゲ−ト部形成
方法を図3に基づいて説明する。図3は、従来例のゲ−
ト部断面図であって、これは、次の方法で製造されてい
る。まず、n型活性層1上にスペ−サとなるシリコン酸
化膜2を被着し、その後、ホトレジストを塗布し、露
光、現像によりゲ−ト形成予定部にパタ−ニングを行
う。次に、ホトレジストをマスクとしてシリコン酸化膜
2をエッチングし、ゲ−ト部を開口する。この時、ウエ
ットエッチング等によりシリコン酸化膜2を水平方向に
もエッチングする。この大きさは、そのままリセス幅の
広さとなる。なお、このリセス幅が小さく、ゲ−ト・ソ
−ス間或いはドレイン間が狭くなると、ゲ−ト耐圧が低
くなってしまい、特性上使用することができない。
2. Description of the Related Art A conventional method for forming a gate portion of a recess structure type will be described with reference to FIG. FIG. 3 shows a conventional example
It is a sectional view of the toe part, which is manufactured by the following method. First, a silicon oxide film 2 serving as a spacer is deposited on the n-type active layer 1, and then a photoresist is applied, and a portion where a gate is to be formed is patterned by exposure and development. Next, the silicon oxide film 2 is etched using the photoresist as a mask to open the gate portion. At this time, the silicon oxide film 2 is also etched in the horizontal direction by wet etching or the like. This size has a wide recess width. If the recess width is small and the gate-source or drain-narrow becomes narrow, the gate breakdown voltage becomes low, and it cannot be used due to its characteristics.

【0003】リセス幅をウエットエッチングにより決め
た後は、ソ−ス・ドレイン間の電流をモニタ−する等に
より、リセスを形成する。次に、ゲ−トメタル(Ti-A
l)を蒸着し、有機溶剤によりリフトオフを行い、リセ
ス内にTi-Alゲ−ト6を形成する。その後、パッシベ−
ション膜として、シリコン酸化膜7やシリコン窒化膜8
を被着し、図3に示すリセス構造タイプのゲ−ト部が形
成される。
After the recess width is determined by wet etching, the recess is formed by monitoring the current between the source and the drain. Next, the gate metal (Ti-A
l) is vapor-deposited and lift-off is performed with an organic solvent to form a Ti-Al gate 6 in the recess. After that, passivate
Silicon oxide film 7 and silicon nitride film 8
To form a gate portion of the recess structure type shown in FIG.

【0004】[0004]

【発明が解決しようとする課題】この従来のゲ−ト形成
方法では、その後のシリコン酸化膜7或いはシリコン窒
化膜8によるパッシベ−ション膜の被着において、リセ
ス内のゲ−ト・ドレイン間或いはソ−ス間は、パッシベ
−ション膜にてびっしりと埋まってしまう。これは、特
に、ゲ−ト・ドレイン間の容量を増大させ、高周波特性
である利得を低下させる原因となってしまう欠点があっ
た。また、その不具合を抑えるために、パッシベ−ショ
ン膜の厚さを薄くすることは、容量低減にはなるけれど
も、デバイスの信頼度を低下させることになってしまう
という問題点があった。
In this conventional gate forming method, in the subsequent deposition of the passivation film by the silicon oxide film 7 or the silicon nitride film 8, the gate-drain or the recess in the recess is formed. The space between the sources is tightly filled with a passivation film. This has a drawback that it increases the gate-drain capacitance and lowers the gain which is a high frequency characteristic. Further, reducing the thickness of the passivation film in order to suppress the problem reduces the capacitance, but has a problem that the reliability of the device is reduced.

【0005】そこで、本発明は、上記欠点、問題点を解
消するリセス構造を有する電界効果トランジスタのゲ−
ト部形成方法に係る半導体装置の製造方法を提供するこ
とを目的とし、詳細には、ゲ−ト・ドレイン間容量を増
大させることなく、高周波特性における電力利得を向上
させることができる上記半導体装置の製造方法を提供す
ることを目的とする。
Therefore, the present invention provides a field effect transistor having a recess structure for solving the above-mentioned drawbacks and problems.
It is an object of the present invention to provide a method for manufacturing a semiconductor device according to a method for forming a gate portion, and more specifically, the semiconductor device capable of improving power gain in high frequency characteristics without increasing a gate-drain capacitance. It aims at providing the manufacturing method of.

【0006】[0006]

【課題を解決するための手段】そして、本発明は、リセ
ス内に中空領域を形成させ、空洞を設けることを特徴と
し、これによって、ゲ−ト・ドレイン間容量を増大させ
ることなく、高周波特性における電力利得を向上させる
ことができるようにしたものである。
The present invention is characterized in that a hollow region is formed in the recess to provide a cavity, whereby high frequency characteristics can be achieved without increasing the gate-drain capacitance. The power gain in is improved.

【0007】即ち、本発明は、n型活性層上にゲ−トリ
フトオフのスペ−サとなるシリコン酸化膜を被着し、そ
の上にシリコン窒化膜を前記シリコン酸化膜より薄く被
着し、ホトレジストによりゲ−ト形成部にパタ−ニング
した後、該窒化膜をドライエッチングにて除去し、その
後、ウエットエッチングにて窒化膜を殆どエッチングせ
ず酸化膜のみを基板まで除去し、更に、サイドエッチを
行って窒化膜下部に空隙を設け、次に、リセス形成を行
い、ゲ−トメタルを蒸着し、レジストでのリフトオフを
行ってゲ−トを形成し、窒化膜とゲ−ト間がふさがり、
リセス内が空洞になるようにパッシベ−ション膜を被着
することを特徴とする半導体装置の製造方法である。
That is, according to the present invention, a silicon oxide film serving as a gate lift-off spacer is deposited on the n-type active layer, and a silicon nitride film is deposited thereon to be thinner than the silicon oxide film. Patterning on the gate formation area by means of dry etching, the nitride film is removed by dry etching, then the nitride film is hardly etched by wet etching, and only the oxide film is removed up to the substrate. To form a void below the nitride film, then form a recess, deposit a gate metal, lift off with a resist to form a gate, and block the nitride film and the gate.
A method of manufacturing a semiconductor device is characterized in that a passivation film is deposited so that a recess is hollow.

【0008】以下、本発明を詳細に説明する。リセス構
造を有する電界効果トランジスタにおいて、リセス内が
パッシベ−ション膜で埋まると、ゲ−ト・ドレイン間容
量が増大し、電力利得の低下を招くので、本発明は、こ
の欠点を解消するため、リセス内に空洞(中空領域)を
形成させるものである。そして、リセススペ−サとして
酸化膜のみを用いるのが通常であるが、本発明では、そ
の上に、更に、ウエットエッチに比べエッチレ−トがか
なり遅い窒化膜を被着し、リセス内に窒化膜で屋根がで
きるようにし、これによって、リセス内に中空領域を形
成させ、その後のパッシベ−ション膜被着に対しては、
リセス内に薄く膜が付くのみであり、窒化膜とゲ−ト間
が閉じてしまうので、中空領域を保つことができる。
The present invention will be described in detail below. In a field effect transistor having a recess structure, if the inside of the recess is filled with a passivation film, the gate-drain capacitance increases, leading to a decrease in power gain.The present invention solves this drawback. A cavity (hollow region) is formed in the recess. Then, it is usual to use only an oxide film as the recess spacer, but in the present invention, a nitride film whose etch rate is considerably slower than wet etching is further deposited on the oxide film, and the nitride film is formed in the recess. To create a roof, which creates a hollow area in the recess for subsequent passivation film deposition.
Since only a thin film is attached to the inside of the recess and the gap between the nitride film and the gate is closed, the hollow region can be maintained.

【0009】本発明におけるゲ−ト部形成手段を説明す
ると、まず、n型活性層上にゲ−トリフトオフのスペ−
サとなるシリコン酸化膜を被着する。次に、この酸化膜
上にシリコン窒化膜を、該酸化膜より薄く被着し、ホト
レジストによりゲ−ト形成部にパタ−ニングを行う。そ
の後、窒化膜をドライエッチングにより除去し、次い
で、ウエットエッチングにて酸化膜の除去並びにサイド
エッチを行う。この時、ウエットエッチにては、窒化膜
は殆どエッチングされないので、窒化膜はレジストと同
パタ−ンで残っているが、酸化膜はリセス長と同じ大き
さに任意に決めることができる。次に、リセス形成を行
い、ゲ−トメタルを蒸着し、レジストにてリフトオフす
ることによりゲ−トを形成する。その後、パッシベ−シ
ョン膜を被着するが、この時、リセス内に窒化膜の屋根
ができるため、ゲ−トとの間がふさがり、リセス内に空
洞(中空領域)が形成される。
The gate portion forming means in the present invention will be described. First, a gate lift-off space is formed on the n-type active layer.
A silicon oxide film serving as a support is deposited. Next, a silicon nitride film is deposited on the oxide film to be thinner than the oxide film, and a photoresist is used to pattern the gate forming portion. After that, the nitride film is removed by dry etching, and then the oxide film is removed and side etching is performed by wet etching. At this time, since the nitride film is hardly etched by wet etching, the nitride film remains in the same pattern as the resist, but the oxide film can be arbitrarily determined to have the same size as the recess length. Then, a recess is formed, a gate metal is vapor-deposited, and a resist is lifted off to form a gate. After that, a passivation film is applied. At this time, since a nitride film roof is formed in the recess, the space between the gate and the gate is blocked and a cavity (hollow region) is formed in the recess.

【0010】[0010]

【実施例】次に、本発明について図1及び図2を参照し
て詳細に説明する。 (実施例1)図1は、本発明の一実施例を示す工程(A
〜C)順のゲ−ト部断面図であって、この内工程Aは、
リセス内に空洞を形成するまでの途中の工程図であり、
n型活性層1上にスペ−サとしてのシリコン酸化膜2と
シリコン窒化膜3を被着し、ホトレジスト10でパタ−
ニングした後、ドライエッチ及びウエットエッチにてリ
セス5を開口することを示す図である。また、工程B
は、工程Aに続いてリセス形成をし、次にゲ−トを形成
した後の図であり、工程Cは、リセス5内に空洞9を形
成した本発明のゲ−ト部断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to FIGS. (Embodiment 1) FIG. 1 shows a process (A) showing an embodiment of the present invention.
~ C) is a cross-sectional view of the gate portion in this order, in which the step A is
It is a process drawing on the way to forming a cavity in the recess,
A silicon oxide film 2 and a silicon nitride film 3 serving as a spacer are deposited on the n-type active layer 1 and patterned with a photoresist 10.
FIG. 6 is a diagram showing that the recess 5 is opened by dry etching and wet etching after the etching. Also, process B
FIG. 8 is a view after forming a recess and then forming a gate following step A, and step C is a cross-sectional view of the gate portion of the present invention in which a cavity 9 is formed in the recess 5. ..

【0011】この工程A〜Cを、更に説明すると、n型
活性層1の上にLPCVDによりシリコン酸化膜2を1500オ
ングストロム程度被着し、その後、プラズマCVDにより
シリコン窒化膜3を500オングストロム被着する。次
に、ホトリゾグラフイ技術を用いてゲ−ト開口予定部4
にパタ−ニングを行い、まず、ドライエッチングにてシ
リコン窒化膜3をエッチングし、次に、1:6のバッファ
−ドフッ酸によりウエットエッチを行い、シリコン酸化
膜3のみをサイドエッチさせる(工程A)。
To further explain these steps A to C, a silicon oxide film 2 of about 1500 angstrom is deposited on the n-type active layer 1 by LPCVD, and then a silicon nitride film 3 of 500 angstrom is formed by plasma CVD. Put on. Next, using the photolithography technique, the gate opening planned portion 4 is formed.
Then, the silicon nitride film 3 is first etched by dry etching, and then wet etching is performed by using 1: 6 buffered hydrofluoric acid to side etch only the silicon oxide film 3 (step A ).

【0012】その後、硫酸:過酸化水素:水=1:8:60
0のエッチヤントにて電流をモニタ−しながら活性層1
をエッチングし、リセス5を約1000オングストロムの深
さで形成する。その後、ゲ−トメタルとなるチタン(T
i)500オングストロム、アルミニウム(Al)3000オ
ングストロムを蒸着し、有機溶剤にてリフトオフし、Ti
ーAlゲ−ト6を形成する(工程B)。次に、LPCVD酸化膜
(1000オングストロム)7、プラズマCVD窒化膜(1800
オングストロム+2000オングストロム)8を被着し、リ
セス5内に空洞9を形成する(工程C)。
After that, sulfuric acid: hydrogen peroxide: water = 1: 8: 60
Active layer 1 while monitoring current with 0 etchant
Is etched to form a recess 5 with a depth of about 1000 angstrom. After that, titanium (T
i) 500 angstrom and aluminum (Al) 3000 angstrom are vapor-deposited and lifted off with an organic solvent.
-Al gate 6 is formed (step B). Next, LPCVD oxide film (1000 angstrom) 7, plasma CVD nitride film (1800
(Angstrom + 2000 angstrom) 8 is deposited to form a cavity 9 in the recess 5 (step C).

【0013】(実施例2)図2は、本発明の他の実施例
であるマッシュル−ム型のゲ−ト部断面図である。この
種のゲ−トは、ゲ−ト抵抗の低減のために、マッシュル
−ム型にしたものであり、このため、構造的には、ひさ
し部とゲ−ト電極間がパッシベ−ションで埋まることに
より、実施例1以上に容量の増大を招き、電力利得に対
して不利となる。このマッシュル−ム型の場合も、その
ゲ−ト形成手段としては、実施例1と同様であり、酸化
膜2、窒化膜3の二重のスペ−サをつくり、マッシュル
−ムゲ−ト11と窒化膜によりリセス内に空洞9をつく
り、容量の増大を抑え、電力利得の向上ができる。
(Embodiment 2) FIG. 2 is a sectional view of a mashroom type gate portion which is another embodiment of the present invention. This type of gate is of a mashroom type in order to reduce the gate resistance. Therefore, structurally, the space between the eaves and the gate electrode is filled with passivation. As a result, the capacity is increased more than in the first embodiment, which is disadvantageous to the power gain. In the case of this mashroom type, the gate forming means is the same as that of the first embodiment, and a double spacer of the oxide film 2 and the nitride film 3 is formed to form the mashroom gate 11. By forming a cavity 9 in the recess by the nitride film, it is possible to suppress an increase in capacitance and improve power gain.

【0014】[0014]

【発明の効果】本発明は、以上説明したように、ゲ−ト
・ソ−ス間又はドレイン間において、リセス内にて空洞
を形成するものであり、このため、パッシベ−ション膜
の厚さにかかわらずゲ−ト・ドレイン間容量を増大させ
ることなく、高周波特性における電力利得を向上させる
ことができる効果を有する。
As described above, according to the present invention, a cavity is formed in the recess between the gate and the source or between the drains. Therefore, the thickness of the passivation film is increased. Regardless of this, there is an effect that the power gain in the high frequency characteristics can be improved without increasing the gate-drain capacitance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す工程順のゲ−ト部断面
図である。
FIG. 1 is a sectional view of a gate portion in the order of steps showing an embodiment of the present invention.

【図2】本発明の他の実施例であるマッシュル−ム型ゲ
−トの断面図である。
FIG. 2 is a cross-sectional view of a mashroom type gate according to another embodiment of the present invention.

【図3】従来例のゲ−ト部断面図である。FIG. 3 is a sectional view of a gate portion of a conventional example.

【符号の説明】[Explanation of symbols]

1 n型活性層 2 シリコン酸化膜 3 シリコン窒化膜 4 ゲ−ト形成予定部 5 リセス 6 TiーAlゲ−ト 7 シリコン酸化膜 8 シリコン窒化膜 9 空洞 10 ホトレジスト 11 マッシュル−ムゲ−ト DESCRIPTION OF SYMBOLS 1 n-type active layer 2 silicon oxide film 3 silicon nitride film 4 planned gate formation part 5 recess 6 Ti-Al gate 7 silicon oxide film 8 silicon nitride film 9 cavities 10 photoresist 11 mashroom gate

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 n型活性層上にゲ−トリフトオフのスペ
−サとなるシリコン酸化膜を被着し、その上にシリコン
窒化膜を酸化膜より薄く被着し、ホトレジストによりゲ
−ト形成部にパタ−ニングした後、該窒化膜をドライエ
ッチングにて除去し、その後、ウエットエッチングにて
窒化膜を殆どエッチングせず酸化膜のみを基板まで除去
し、更に、サイドエッチを行って窒化膜下部に空隙を設
け、次に、リセス形成を行い、ゲ−トメタルを蒸着し、
レジストでのリフトオフを行ってゲ−トを形成し、窒化
膜とゲ−ト間がふさがり、リセス内が空洞になるように
パッシベ−ション膜を被着することを特徴とする半導体
装置の製造方法。
1. A gate oxide film is deposited on the n-type active layer to serve as a gate lift-off spacer, and a silicon nitride film is deposited thereon to be thinner than the oxide film. After the patterning, the nitride film is removed by dry etching, then the nitride film is hardly etched by wet etching, and only the oxide film is removed up to the substrate. A void is formed in the hole, then a recess is formed and a gate metal is vapor-deposited.
A method for manufacturing a semiconductor device, characterized in that a gate is formed by performing lift-off with a resist, and a passivation film is deposited so that the nitride film and the gate are closed and the recess is hollow. ..
【請求項2】 ゲ−トがマッシュル−ム型ゲ−トである
請求項1に記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the gate is a mashroom type gate.
JP24661491A 1991-08-31 1991-08-31 Manufacture of semiconductor device Pending JPH0563003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24661491A JPH0563003A (en) 1991-08-31 1991-08-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24661491A JPH0563003A (en) 1991-08-31 1991-08-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0563003A true JPH0563003A (en) 1993-03-12

Family

ID=17151026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24661491A Pending JPH0563003A (en) 1991-08-31 1991-08-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0563003A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007028920A1 (en) * 2006-10-12 2008-04-24 Mitsubishi Electric Corp. Field effect transistor and method for producing the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268069A (en) * 1988-04-19 1989-10-25 Fujitsu Ltd Manufacture of semiconductor device
JPH0491439A (en) * 1990-08-02 1992-03-24 Nikko Kyodo Co Ltd Field-effect transistor and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01268069A (en) * 1988-04-19 1989-10-25 Fujitsu Ltd Manufacture of semiconductor device
JPH0491439A (en) * 1990-08-02 1992-03-24 Nikko Kyodo Co Ltd Field-effect transistor and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007028920A1 (en) * 2006-10-12 2008-04-24 Mitsubishi Electric Corp. Field effect transistor and method for producing the same
DE102007028920B4 (en) * 2006-10-12 2009-09-10 Mitsubishi Electric Corp. Field effect transistor with a cavity formed in a silicon nitride layer and method for producing the same
US7642567B2 (en) 2006-10-12 2010-01-05 Mitsubishi Electric Corporation Field-effect transistor and method of manufacturing the same

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