JPH0561783A - Microcomputer - Google Patents

Abstract

PURPOSE:To make an error processing exact in serial communication between plural systems according to a simplified program by storing an error class in a memory in the same form as received data in the case of serial reception and judging whether the block stored in the memory is the received data or the error class. CONSTITUTION:This device is composed of a shift register 1 to convert serial data signals (d) into parallel data, error detector 3 to detect the generation of error in the serial reception, and error class register 4 to store the detected error class and further, the device is equipped with a reception buffer 2 to store the received data and data showing the error class, selecting circuit 5 to select whether the data to be stored in the reception buffer 2 are the received data or the error class, and storage circuit 6 to store whether the data in the reception buffer 2 are the received data or the error class until a CPU reads the data. Then, a software transfers the data while pairing the received data or the error class in the reception buffer with the data in the storage circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a serial receiver circuit built in the microcomputer.

[0002]

2. Description of the Related Art A conventional serial receiving circuit will be described with reference to the drawings. FIG. 6 is a block diagram of a serial reception circuit of a conventional microcomputer. In the figure, a shift register 1. converts the data signal d received as serial data into parallel data. And a reception buffer that saves the converted parallel data until it is read by the CPU of the microcomputer 2. And an error detector for detecting an error in serial reception. Error type register that stores the type of error detected Had.

The above-mentioned error type does not indicate that the next serial data is received (overrun error) before the data saved in the receiving buffer 2 is read to the CPU, or that there is no stop bit indicating the end of the serial data. There is a message indicating that the received data has a different parity (a parity error). Normally, this type of serial receiving circuit receives received data from the receiving buffer 2. Reception end signal when retreating to b. And the error type is the error type register 4. Received error signal c.
It was supposed to output.

As one of serial reception processes using a microcomputer having the above-described serial reception circuit built-in, software processes as shown in FIGS. 7 and 8 have been used.

In FIG. 7, the reception end signal b. Software processing by D. Is starting up. Software processing D. Receive buffer 2. 7. The received data of 7 is read to the CPU, and the memory for each block 7. Process for transferring to D. Within the reception error judgment block, the reception error signal c. If a reception error occurs, the software processing for performing an error response (correction response) to the sender is performed. (Error processing) is activated.

In FIG. 8, the reception end signal b. Software processing in F. With the received error signal c.
(Error processing) is activated. Software processing F.
Is the receive buffer 2. Read the received data of to the CPU,
Memory for each block 7. Process to transfer to
In this process, the interrupt signal c. The point that does not detect D. Is different from

FIG. 9 is a diagram of an example of a system in which a plurality of microcomputers are connected by serial communication.

FIG. 10 is a diagram of an example of an error signal line connection system.

FIG. 11 is a diagram of an example of a system in which a circle connection is made.

As shown in FIGS. 9, 10 and 11, recently, a microcomputer incorporating this serial receiving circuit is used to connect a plurality of microcomputers by a common serial signal line, and each signal line is connected through the signal line. The number of cases of constructing a system for exchanging data between microcomputers is increasing. In this case, in order to define the transmitting microcomputer and the receiving microcomputer, a procedure for data transmission / reception in serial communication is defined, and when connecting the plurality of microcomputers in FIGS. Serial communication is performed by formatting the serial data of a plurality of blocks as shown in the figure of the format example of exchanging block data. This data transmission / reception procedure is called a communication protocol (communication procedure), and various ones are considered.

[0011]

In the microcomputer incorporating the conventional serial receiving circuit, the error type register 4. Data is held only until the next serial reception is performed, and the reception error signal c. Is only retained for the above period. Therefore, in the software processing of FIG. 7 and FIG.
An error response (correctness response) is sent to the sender. However, in the case of constructing the system as shown in FIGS. 9, 10, and 11, even if a reception error occurs in a block in the middle of the format of a plurality of blocks as shown in FIGS. 12 and 13, the software process G shown in FIG. ． In many cases, you should not send an error response to the sender.

This is because, in the systems shown in FIGS. 9, 10 and 11, all the microcomputers connected by the common serial signal line perform serial communication according to the defined communication protocol. When the data communication of the format is completed, only the microcomputer corresponding to the receiving address is supposed to respond.

Therefore, even if an error occurs during the serial communication, the communication is continued, and after all blocks having the formats as shown in FIGS. 12 and 13 are communicated, the receiver address is confirmed and the corresponding microcomputer is confirmed. Only had to respond with an error.

Otherwise, if a communication error occurs, another microcomputer may make an error response while the transmission source microcomputer is still transmitting, or a plurality of microcomputers may make an error response at the same time. There was a problem that serial data would collide with each other, serial communication could not be performed, and the microcomputer would be destroyed.

However, in a conventional microcomputer having a built-in serial reception circuit, when new serial data is serially received, information indicating that an error has occurred (reception error signal c.) And information indicating the type of error (error data) are provided. Since it is lost, it is impossible to determine the presence or absence of an error and the error type after the communication of all the blocks having the formats shown in FIGS. 12 and 13 is completed.

For this reason, it is difficult for the system as shown in FIGS. 9, 10 and 11 to make an error response after all blocks having the formats shown in FIGS. 12 and 13 have been communicated. It was

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a microcomputer with a simplified program for appropriately executing error processing in serial communication between a plurality of systems. To do.

[0018]

A microcomputer according to the present invention serially receives a plurality of blocks of data, each block having a plurality of bits of data, and judges whether the plurality of blocks of data are serially communicated in units of blocks. As a result of the above judgment, if the block is a positive block, the received data is retained as it is, and if it is an incorrect block, the received data is converted into data indicating the content of the error, and then a plurality of blocks are collectively stored in a memory. And a means for discriminating a block showing the content of the error from a plurality of blocks stored in the memory.

[0019]

According to the above structure, the microcomputer of the present invention judges whether the serial communication of a plurality of blocks of data in units of blocks is correct, holds the correct block as it is, and in the case of the incorrect block. After converting into data indicating the content of the error, a plurality of blocks are collectively stored in the memory and the block indicating the content of the error is discriminated. Therefore, the error processing can be performed after the communication of the block of the format is completed.

[0020]

The present invention will be described below with reference to the drawings.

FIG. 1 is a flow chart of software processing A of a microcomputer according to an embodiment of the present invention. Software processing of FIG. Is the case where it is executed by the system shown in the conventional example. Receive buffer serially received in FIG. Memory for each block 7. Reception end signal b. Is started with. Software processing A. Block A1. Receive error signal at c. Is being detected (step ST10). If no error occurs, the received data is stored in the memory as it is 7.
(ST11). If an error has occurred, block A2. The error type is selected in step (step ST12) and the memory 7. Are transferred to (STEP ST13, ST14, ST15). In addition, block A3. At memory 7. A block indicating whether the data transferred to the received data is the received data or the error type is stored in the memory 7. (Step ST16), (step ST17).

FIG. 2 is a flow chart of software processing B of the microcomputer according to the embodiment of the present invention. Software processing B. Software processing A. In the process of analyzing the format as shown in FIG. Software processing B. Block B3. At memory 7. It is determined whether the 1 block is received data or an error type (step ST20).
Block B4. At memory 7. It is confirmed that the data of a plurality of blocks transferred to the above-mentioned data matches the format, and the received addresses match (step ST21). If the format and address match (step ST2)
2) Block B5. If there is an error type, an error response (correction response) according to the error type is transmitted to the transmission source microcomputer (step ST23), (step ST24).

In this way, after all blocks having the format as shown in FIG. 12 are communicated once, only the microcomputer of the corresponding address can respond with an error.

When an error response is made in the system example shown in FIG. 9 regardless of the present embodiment, it is necessary to receive an error response before the block next to the block in which the error has occurred is received and the error information is lost. Therefore, as in the system example shown in FIG. 10, the signal line 15. It is necessary to stop the transmission of the next block of the transmission source microcomputer by this error signal. The process of outputting and receiving the error signal is shown in FIG.
It is necessary to carry out from one block to the block of the above format, which is highly urgent. For this reason, the interrupt process is usually used, and the process becomes very complicated and has severe timing. According to this embodiment, since an error response can be made after the completion of serial communication, there is an advantage that a signal line for notifying an error and error processing are not required, and the microcomputer port can be saved and software processing can be simplified.

Further, in the case where the blocks for all microcomputers are always defined in the format as in the circle connection system of FIG. 11, the microcomputers of the transmission source and the reception destination are located at the positions of the blocks of the format of FIG. However, even if there is an error in a block in the middle, an error response cannot be made. Therefore, in anticipation of an error, data received normally several times (at least three times) match and are valid. Therefore, completion of data reception requires several times the cycle of the format of FIG. 13 and takes communication time.

According to this embodiment, after the serial communication is completed,
Since an error response can be made by serial communication in the next cycle,
There is an eye merit that the communication time can be shortened (about 1/3) without having to confirm the coincidence of the communication data several times.

Next, a second embodiment which is another embodiment of the present invention will be described.

FIG. 3 is a block diagram of a microcomputer showing a second embodiment of the present invention.

In FIG. 3, the serial data signal d. Shift register for converting data into parallel data And an error detector that detects that an error has occurred in serial reception.
And an error type register for storing the detected error type 4. In addition to the conventional configuration, the shift register 1.
1. A reception buffer that stores the reception data converted in step 1 and the data indicating the error type. And the receiving buffer 2.
4. A selection circuit for selecting either the received data or the error type as the data to be stored in 5. And the reception buffer 2. 5. A storage circuit for storing whether the data of (1) is received data or an error type until it is read by the CPU section of the microcomputer. Composed of.

FIG. 4 is a flow chart of software processing in the microcomputer according to the second embodiment. If serial reception is performed and there is an error, the error type register 4. If there is no error in the contents of shift register 1. Contents of the selection circuit 5. Receive buffer 2. Memorized in. Receive buffer 2. When the data is stored in the reception end signal a. Occurs, and the software processing C. Is started. Software processing C. Receive buffer at 2. Received data or error type and storage circuit 6. Memory of data of 1 as one block 7. Transfer to.

In this case, the software processing C. Is the software processing A. of the first embodiment. Much simpler than
Receive buffer 2. Data and memory circuit 6. Memory of the data of 7. Process to transfer to (step S
T30). Therefore, faster serial communication can be supported as compared with the first embodiment. The software processing E receives data block by block, and the same software processing B. Analyze the format with.

Next, a third embodiment which is another embodiment of the present invention will be described.

FIG. 5 is a block diagram of a microcomputer showing a third embodiment of the present invention, and is a block diagram of an automatic reception system by hardware to which the present invention is applied.

In FIG. 5, the serial data signal d. Shift register for converting data into parallel data And an error detector that detects that an error has occurred in serial reception.
And an error type register for storing the detected error type 4. And the shift register 1. 1. A reception buffer that stores the reception data converted in step 1 and the error type. When,
Receive buffer 2. 4. A selection circuit for selecting either the received data or the error type as the data to be stored in 5. When,
The reception buffer 2. 5. A storage circuit for storing whether the data of (1) is received data or an error type until it is read by the CPU section of the microcomputer. In addition to
The communication start data H.264 shown in the format of H.2. And receive buffer 2. Reception start data comparator for comparing the data stored in 9. And the communication end data I. And receive buffer 2. Reception end data comparator for comparing the data stored in 10. When the format shown in FIG. 12 is being transmitted, the receiving signal h
Receiving signal generator 11 for outputting And memory for each block 7. Storage destination designation circuit for storing the address to be stored in 12. It is composed of

While receiving the format of FIG.
The receiving signal h and the reception end signal a. The storage destination address is updated by and the block for the format of FIG. 12 is transferred.

In this case, there is no software processing as in the first and second implementation examples, and faster serial communication can be supported as compared with the first and second embodiments.

[0037]

As described above, the present invention has means for storing the error type at the time of serial reception in the memory in the same format as the received data and means for determining whether the block stored in the memory is the received data or the error type. Since it is provided, a serial communication system of a microcomputer can be easily constructed, and even if an error occurs in a block in the format of multiple blocks, only the specified destination microcomputer will give an error response (correctness response). Can be done. Further, there is an effect that a system for automatically receiving serial data composed of several blocks of data by hardware and transferring it to the memory can be realized.

[Brief description of drawings]

FIG. 1 is a flowchart of software processing A of a microcomputer that is an embodiment of the present invention.

FIG. 2 is a flowchart of software processing B of the microcomputer that is an embodiment of the present invention.

FIG. 3 is a block diagram of a microcomputer that is a second embodiment of the present invention.

FIG. 4 is a flow chart of software processing C of the microcomputer according to the second embodiment of the present invention.

FIG. 5 is a block diagram of a microcomputer according to a third embodiment of the present invention.

FIG. 6 is a block diagram of a conventional microcomputer.

FIG. 7 is a flow chart of software processing D and E of a conventional microcomputer.

FIG. 8 is a flowchart of processing of software processing F and G of a conventional microcomputer.

FIG. 9 is a diagram of an example of a conventional connection system for a plurality of microcomputers and serial communication.

FIG. 10 is a diagram of an example of a conventional plurality of microcomputers and an error signal line connection system for serial communication.

FIG. 11 is a diagram of a system example of a plurality of conventional microcomputers and a circle connection for serial communication.

FIG. 12 is a diagram of a format example of a plurality of conventional microcomputers and serial communication.

FIG. 13 is a diagram showing a block-based format example of a plurality of conventional microcomputers and serial communication.

[Explanation of symbols]

 A. Example of reception end process 1 B. Format analysis process C. Example of reception end processing 2 H. Communication start data I. Communication end data 1 Shift register 2 Reception buffer 3 Error detector 4 Error type register 5 Selection circuit 6 Storage circuit 7 Memory 8 Internal data bus 9 Start data comparator 10 End data comparator 11 Receiving signal generator 12 Storage destination address Designation circuit 13 Internal address bus 14 Serial bus 15 Error signal line a Reception end signal (including reception error) b Reception end signal c Reception error signal d Serial data e Internal reference clock f Normal data or error type identification signal g Error type signal h Signal being received i Start data detection signal j End data detection signal

Claims (1)

[Claims] 1. A microcomputer for serially receiving a plurality of blocks of data, in which a plurality of bits of data is one block, and means for judging whether the serially received reception data of the plurality of blocks is correct or not in serial communication in block units. As a result of the judgment by the means for judging the correctness, in the case of a positive block, the received data is retained as it is, and in the case of an incorrect block, the received data is converted into data indicating the content of the error, and then a plurality of blocks are collectively processed. And a unit that stores the data in a memory, and a unit that determines a block including data indicating the content of the error from a plurality of blocks stored in the memory by the storage unit.