JP2655631B2 - CSI bit processing method and circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer system (Asyn
In ch n referred to as rous Transfer Mode Hereinafter ATM), Convergence Sublayer Indication in a transfer unit of the communication cell (Convergence Sublaye
r Indication (hereinafter referred to as CSI) bit reception processing, and in particular, to a method of checking information transfer using CSI bits and its circuit.

[0002]

2. Description of the Related Art One example of the use of CSI is CCITT.
Recommendation I. 363. I. In AAL, that is, Type 1 of the ATM Adaptation Layer specified in H.363, a digital signal that is asynchronous with the network clock is A
As a method for reproducing the original clock frequency on the receiving side when transferring in the form of TM cells, SRTS (Synchr
onous Residual Time Stamp ). In this method, frequency information is expressed by 4 bits and transmitted from the transmission side to the reception side. In Type1 the AAL, (hereinafter referred to as SN) sequence number of 0-7 to indicate the order of the cells but is used, frequency regeneration
It is a correction time stamp of the synchronization information RTS (Residual
Time Stamp) information is to be transferred by the CSI bit of the cell of the odd number SN. Therefore, SN = 1, 3,
Cells of 5 and 7 transfer RTS of 4 bits. At this time, the MSB (Most Significant Bit) of the information transferred
Is transferred in the cell of SN = 1, and the LSB (Least Signific
ant Bit) is transferred in the cell of SN = 7.

[0003]

The above-mentioned conventional AAL
In the type 1 CSI bit processing method, by checking the continuity of the received cells, it is possible to detect cell loss or erroneous writing. For example, "SDH path signal transmission method using ATM network" by Uematsu and Ueda, IEICE Technical Report CS91-112 March 1992
According to the algorithm shown in the month, it is possible to detect one cell alone mis-distribution and a maximum of six consecutive cell losses,
It is possible to detect whether the CSI bit is lost due to cell loss.

By the way, when a cell loss occurs, the RTS information is lost when the SN of the lost cell is odd, but the RTS information is not lost even when the even SN cell is lost.

That is, in this case, it is not sufficient to determine only whether or not the CSI bit is lost, and it is necessary to determine whether or not the lost CSI bit transfers valid information. There's a problem.

[0006] It is an object of the present invention to provide a method for processing CSI bits, which determines whether or not information transferred by CSI bits has been lost due to cell loss.

[0007]

The CSI bit processing method of the present invention uses a convergence sublayer indication bit, that is, a CSI bit in an asynchronous transmission system, and uses a sequence number assigned to a cell which is a unit of communication transmission. A method of processing CSI bits when transmitting information by CSI of a cell of at least one specific sequence number, comprising the step of determining whether information is lost due to cell loss when receiving an information transfer. ing.

[0008] The step of determining whether or not information has been lost due to the cell loss includes the step of detecting whether or not a cell with the specific sequence number has been received, and detecting a lack of reception of the cell with the specific sequence. And outputting a signal indicating that the transfer information has been lost.

Further, the CSI processing circuit of the present invention uses a convergence sublayer indication bit, that is, a CSI bit in an asynchronous transmission system, and uses at least one specific number by using a sequence number assigned to a cell which is a unit of the communication. Means for detecting reception of a cell for each specific sequence number transmitting information by the CSI bit, in a CSI bit processing circuit on the receiving side when transmitting information by CSI of a cell having a sequence number;
Set / reset flip-flop means which is set when loss of at least one of the cells having the specific sequence number is detected, and reset when reception of a cell having a predetermined sequence number is detected; And means for outputting a signal indicating that transfer information has been lost when the setting means is set.

[0010] Further, the specific sequence numbers are 1, 3, 5, and
7 including a cell having a sequence number of 1 for performing the reset.

[0011]

As described above, the information is loaded on the cell having the predetermined sequence number, and the receiving side performs the CSI for each of the
Is detected, and when a loss of at least one cell is detected, a signal indicating loss is output, so that it is possible to automatically recognize whether or not the received information is correct.

[0012]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a CSI bit processing circuit to which the CSI bit processing method of the present invention is applied.

This CSI bit processing device is a processing device for transferring 4-bit information in odd-numbered SN cells in the same manner as the SRTS, and is an individual device for detecting the reception of each of the received SNs 1, 3, 5, and 7. Reception detectors 1, 3, 5, 7
An odd SN cell loss detector 11 for detecting the loss of one of the odd cells, a seventh cell loss detector 12 for detecting the loss of the cell of SN7, a timing pulse generator 13, RS flip-flop RS-FF
10 and individual CSI bit latch units 21, 23, 25, 27 for latching the CSI of the odd-numbered cells, and D
The flip-flop 14 is provided.

Next, the operation of this embodiment will be described.

(1) When it is detected that cells having SN = 1, 3, 5, and 7 have been received, the respective CSI bits are latched by the CSI bit latch units 21, 23, 25, and 27.

(2) When it is detected that a cell with SN = 7 has been received, as shown in (1), the CSI bit latch 2
Latch at 7. Then, the timing pulse generator 13
, A latch pulse is generated, and the latched 4-bit CSI bit is output from the D flip-flop 14 together with the reset invalid information flag.

(3) The output of the RS-FF 10 is an invalid information flag, and the odd SN cell loss detecting section 11
When the cell loss is detected, the invalid information flag which is the output of the RS-FF set is set in the D flip-flop 14, and when the reception detecting unit 1 detects the reception of the cell with SN = 1, the invalid information flag is reset. .

(4) When the cell with SN = 7 is lost, the odd-number SN cell loss detecting section 11 operates to set the RS in the set state.
-FF outputs an invalid information flag, sets it in the D flip-flop 14, and then outputs the timing pulse generator 13 by the operation of the seventh cell loss detector 12,
The latched 4-bit CSI bit is output together with a set invalid information flag indicating invalid.

(5) If a cell with SN = 1 is lost, R
The S-FF is not reset, and thus the invalid information flag remains set.

Next, an example of reception will be described with reference to Table 1.

[0022]

[Table 1] An example of the reception SN sequence shown in Table 1 shows an operation example of the circuit of FIG.

Reception example 1. In the case of the received SN sequence shown in item No. 1, 4-bit information is determined when SN = 7 is received. If the odd-numbered SN cell loss detector 11 is not operating at that time, it indicates that all odd-numbered cells of SN = 1, 3, 5, 7 have been normally received.
Is in the reset state, and the invalid information flag in the reset state is determined by the CSI bit received via the D flip-flop 14 (whether or not the CSI bit has been set is determined by the CS
(Depending on the I bit reception state) to indicate the validity of the information. If the odd SN cell loss detection unit 11 is operating, one of the cells of SN = 1, 3, 5 is lost, the RS-FF 10 is in the set state, and the invalid information flag in the set state is set to the D flip-flop. Output together with the CSI bit received via the loop 14 to indicate that the information is invalid. In addition, the reception of SN = 1 indicates that the reception of the next information has started normally, so that the invalid information flag is reset.

Reception example 2. In the case of the received SN sequence shown in item No. 2, SN = 0 is lost, but this does not affect the CSI bit, so that the state of the RS-FF 10 does not change and the same operation as in the first reception example. Becomes

Reception example 3 In the case of the received SN sequence shown in item No. 3, SN = 7 is lost, and when SN = 0 is received, the loss of SN = 7 is detected, and the odd SN cell loss detector 11
Operates, the RS-FF 10 is set, and the invalid information flag is set in the D flip-flop 14 and output together with the four meaningless data latched. The data at this time is meaningless information because SN = 7 is missing. However, at the time of reception of SN = 1, SN
Upon receipt of 1, the RS-FF is reset and the invalid information flag is reset.

Reception example 4. In the case of the received SN sequence shown in No. 4, both SN = 7 and 0 are lost, and SN =
1 is received, the odd SN cell loss detection unit 11
= 7 is detected, the RS-FF 10 is set, the invalid information flag is set in the D flip-flop 14, and immediately after that, the data is output together with the latched 4-bit meaningless information. Thereafter, the RS-FF 10 is reset when SN = 1 is received, as in the third reception example.

Reception example 5 In the case of the received SN sequence shown in item No. 5, SN = 7 and 1 are lost, and when SN = 2 is received, the loss of SN = 7 and 1 is detected, and the odd SN cell loss detection unit 11 Puts the RS-FF 10 in a set state, whereby the invalid information flag is set in the D flip-flop 14, and is output together with the meaningless 4-bit information latched immediately thereafter. Further, since SN = 1 has not been received, the RS-FF 10 is not reset.

Reception example 6 In the case of the reception SN sequence shown in item No. 6, the four bits latched as in the reception example 1 and the invalid bit reset as in the reception example 1 unless there is an output of the odd-number SN cell loss detector 11 at the reception time of SN = 7 Output information flag. Further, at the time of receiving the cell with SN = 2, the loss of SN = 1 is detected and the invalid information flag is set. in this case,
The invalid information flag is not reset.

[0029]

As described above, the present invention detects reception of each specific cell number for transmitting information, and outputs a signal indicating invalid information when loss is detected in any one of them. Therefore, there is an effect that the authenticity of the transmitted information can be automatically and immediately recognized.

[Brief description of the drawings]

FIG. 1 shows a C to which a CSI bit processing method of the present invention is applied.
It is a block diagram of one embodiment of an SI bit processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reception detection part of SN = 1 3 Reception detection part of SN = 3 5 Reception detection part of SN = 5 7 Reception detection part of SN = 7 10 RS-FF 11 Odd SN cell loss detection part 12 7th cell loss detection part Reference Signs List 13 timing pulse generator 14 D flip-flop 15 invalid information flag 21 1st cell bit latch section 23 3rd cell bit latch section 25 5th cell bit latch section 27 7th cell bit latch section

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiromi Ueda Nippon Telegraph and Telephone Corporation, 1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo (56) References "B-ISDN Picture-to-Text Reader" Supervised by Minoru Akiyama Ohmsha (Issued January 30, 1993) P104-106 ITU-T RECOMMENDATION ION. 363

Claims (4)

(57) [Claims] 1. A method of using a convergence sub-layer indication bit, ie, CSI bit, in an asynchronous transmission system, and using a sequence number assigned to a cell, which is a unit of communication transmission, for a CSI of a cell having at least one specific sequence number. When transmitting information by C
A method of processing CSI bits, comprising the step of, when receiving an information transfer, determining whether transfer information has been lost due to cell loss. 2. The method according to claim 1, wherein the step of determining whether information is lost due to the cell loss includes the step of detecting whether a cell for each of the specific sequence numbers is received; Outputting a signal indicating that the transfer information has been lost when detected. 3. A method of using a convergence sub-layer indication bit, ie, CSI bit, in an asynchronous transmission system, and using a sequence number assigned to a cell, which is a unit of the communication, to obtain information by a CSI of a cell having at least one specific sequence number. In the CSI bit processing circuit on the receiving side when transmitting the cell, means for detecting reception of a cell for each of the specific sequence numbers transmitting the transfer information by the CSI bit, and at least one of the cells having the specific sequence number Set / reset type flip-flop means which is set when a cell loss is detected and reset when reception of a cell having a predetermined sequence number is detected; and when the flip-flop means is set, transfer information is set. Output a flag bit indicating loss A CSI bit processing circuit comprising means. 4. The method according to claim 3, wherein the specific sequence numbers are 1, 3, 5, and 7 when the sequence numbers are repeated from 0 to 7, and the sequence number of the cell to be reset is 1. A CSI bit processing circuit as described in the above.