JPH0561649A - Divider circuit - Google Patents

Abstract

PURPOSE:To rapidly and efficiently execute division in which the number of digits in data is known like division to be used for the calculation of a centroid in fuzzy inference. CONSTITUTION:An OR value between the most significant bit(MSB) of a partial residual and an overflow signal from a subtractor is used for deciding the validity of subtraction, lower bits in a dividend register 2 are stored in a shift register 5 and outputted to the least significant bit(LSB) of the subtractor in each bit synchronously with subtraction shift. Since the size of the subtractor in a subtraction shift type divider can be reduced up to the number of bits of a divisor and the frequency of subtraction shift operation can be reduced up to the number of bits in a quotient, rapid division can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a division circuit for digitally executing division when calculating a centroid value performed by a defuzzification operation of fuzzy inference.

[0002]

2. Description of the Related Art In digital operation, when performing division of integer type numbers, so-called subtraction shift type division (reference 1: "Computer high-speed operation method", written by Yasushi Horikoshi), in which a divisor is repeatedly subtracted from a dividend. P215, Modern Science Co., Ltd.).

This is the most significant bit (MSB) of the dividend
And the least significant bit (LSB) of the divisor are combined to perform the first division. If the subtraction is possible, the subtraction result is the partial remainder, and if the subtraction is not possible, the dividend before the subtraction is the partial remainder.

Then, the divisor is shifted by 1 bit to the lower bit side, and the same operation is performed. Similarly, if a subtraction shift is performed by the divisor bit, an integer division result is obtained.

By continuing the subtraction shift, the calculation result below the decimal point can be obtained. The partial remainder represents the remainder up to where each subtraction shift is performed. The exact method of obtaining the remainder is described in detail in Japanese Examined Patent Publication No. 3-37212 (Reference 2).

In fuzzy inference, a defuzzification operation is performed at the end of inference to convert a fuzzy amount into a normal (crisp) amount. As a method, the centroid value of the fuzzy amount is generally obtained. Target. In this case, the center of gravity value G is calculated by the following equation.

G = (ΣAi × Di) / ΣDi (1)

However, Ai represents each element of the base set (indicating the spread) of the membership function, and Di represents the grade of each element of the base set. The center-of-gravity value G is obtained by dividing the result of the product sum operation of the numerator and denominator. Generally, the number of divisions of the platform set takes a value of about 16 to 256, and elements and grades are expressed by about 4 to 8 bits.

According to Document 1, in order to perform the subtractive shift type division in general, a dividend register, a divisor register, and a subtracter having a digit number twice the dividend are required. When the division is performed according to the equation (1), for example, when the element is represented by 8 bits (that is, the number of divisions is 256) and the grade is also represented by 8 bits, when the sum of products operation is performed on each of the denominator numerator, the numerator becomes 24 The bit and denominator are represented by 16 bits.

When operating with a conventional divider, it is necessary to handle the larger 24 bits, so that the register for the dividend (numerator), the divisor register (for the denominator) and the subtracter need 48 digits. Become. Finally, the division shift is repeated 24 times to obtain an integer type quotient.

[0011]

On the other hand, since the division in the calculation of the center of gravity of fuzzy reasoning has the following characteristics,
A conventional divider has many wasteful operations in its configuration. That is,

Even if the dividend is 24 bits, since the divisor has only 16 bits, it is obvious that at least the first 16 stages cannot be divided when the subtraction shift is performed in the division process. This subtraction shift of 16 steps is a useless calculation.

When the dividend is 24 bits, the conventional method prepares a register of 48 bits including the quotient field (24 bits) (MSB of dividend and L of divisor).
(Since SB digits are combined and divided, double size is required)
However, the quotient is 8 bits or less, and at least the upper 16 bits for the quotient field are known to be 0, which results in wasting. Not only the register but also the subtracter may not have 16 bits of the quotient field as a result.

An object of the present invention is to provide a division circuit which can eliminate such a wasteful operation and can obtain an equivalent operation result with a minimum configuration.

[0015]

In order to achieve the above object, in a division circuit according to the present invention, a dividend is input, and a dividend register for holding a partial remainder during a division operation and a divisor are input to perform a division operation. During this period, a divisor register that holds the divisor, a subtraction circuit that performs subtraction between the value of the dividend register and the value of the divisor register, a subtraction determination circuit that determines whether subtraction is possible, a subtraction result if subtraction is possible, a subtraction result If possible, a subtraction shift type including a subtraction selection circuit that sends the dividend before subtraction to the dividend register as a partial remainder for the next subtraction, a quotient register that sequentially holds the subtraction determination signal, and a timing control circuit that controls arithmetic processing. Of the subtraction circuit, the most significant bit of which is connected to the subtraction determination circuit, and outputs 1 when the divisor is larger than the dividend. Is connected to also the subtraction discriminating circuit output flow, either subtraction determination circuit of the most significant bit or overflow of the dividend is what determines if 1 deductible and.

Further, a dividend register is input, and a dividend register that holds a partial remainder during a division operation; a divisor register that inputs a divisor and holds a divisor during a division operation; a value of the dividend register and the divisor; A subtraction circuit that performs subtraction with the value of the register, a subtraction determination circuit that determines whether or not subtraction is possible,
A subtraction selection circuit that sends the subtraction result as a subtraction result if it can be subtracted, or a dividend before subtraction as a partial remainder for the next subtraction if it cannot be subtracted, a quotient register that sequentially holds the subtraction determination signal, and timing control that controls arithmetic processing. A subtraction shift type division circuit including a circuit, the number of digits of the subtraction circuit is equal to the number of digits of the divisor, and the dividend register has the most significant bit connected to the subtraction determination circuit and the most significant bit of the dividend. It is held in the minute register, the lower bits of the dividend are made up of the shift register by the difference between the number of digits of the dividend and the number of digits of the divisor, and the output of the register of the upper bits of the dividend is output to the subtracter except for the most significant bit. Connected, the serial output of the shift register is connected to the least significant bit of the subtractor, and one bit from the upper bit in the shift register each time the subtraction is performed. One is intended to output.

[0017]

[Operation] The useless registers and operations made clear above are
First, delete it. Next, further optimization is performed with the remaining configuration. If the dividend is a bits, the divisor is b bits, and only the integer part of the quotient is c bits, there is a relationship of a−b = c.

Therefore, as disclosed in Document 2, first, all the quotient fields of the subtractor are deleted, and new quotient registers are added by the required number of bits (c bits).
Accordingly, the size of the subtractor may be prepared by the number of bits of the dividend (a bits).

The present invention further improves the following points. That is, it is the divisor that is subtracted, and the subtractor is configured so that it can be subtracted by at least the number of digits (b bits) of the divisor. This makes it possible to eliminate the subtractor for the difference between the dividend and the number of digits of the divisor (that is, for c bits). The details are shown below.

The most significant bit of the dividend is subtracted by performing shift subtraction from the upper bits of the dividend except for the most significant bit, and the overflow of the subtractor is determined in the following manner. I didn't have to. That is, if the most significant bit of the dividend is 1, it is always possible to subtract even if the divisor takes the maximum value. Therefore, the most significant bit is directly connected to the subtraction determination circuit without being connected to the subtractor.

Further, when the most significant bit of the dividend is 0, it is necessary to make a judgment by the overflow output of the subtractor, so the overflow output of the subtractor is also connected to the subtraction judgment circuit.

Therefore, if either the most significant bit or the overflow output of the subtractor is 1, subtraction is possible, and the subtraction selection circuit makes the subtraction result the partial remainder of the next operation. When both are 0, the subtraction becomes impossible and the dividend before the subtraction is used as the partial remainder of the next operation. In this way, the subtractor can be reduced by one bit by omitting the subtraction of the most significant bit.

The divisor bits are subtracted from the upper bits of the dividend excluding the most significant bit. At this time, the dividend is a normal register from the most significant bit to the divisor bit (b bits), and the lower c bits are held in the shift register. At the time of the first subtraction, the upper bits have already been output from the shift register.

As a shift method after the subtraction, b-1 bits excluding the most significant bit of the dividend are connected to the most significant bits of the partial remainder (that is, one bit is shifted to the upper bit side by wire connection), and the maximum of the partial remainder is changed. The next bit of the shift register is input to the lower bit. This allows the subtraction to be always b bits, and eventually the number of subtractions can be reduced by c-1 bits supplied from the shift register by the subtraction shift after the second time.

By using the methods (1) and (2), after all, the subtractor for c bits can be deleted as a whole, and the configuration of the division circuit can be reduced.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention is shown in FIG. This is the 24-bit dividend divided by the 16-bit divisor to obtain 8
It is a division circuit that obtains the quotient of bits. The circuit is realized by a combination of general-purpose digital ICs.

The input selection circuit 1 is for loading the dividend data into the divider. When the load signal is 1, the input value is selected, and when it is 0, the partial remainder is selected. Select the input value at initial load, and always select the partial remainder during division.

The dividend register 2 is the upper input register 3
(16 bits) is composed of a D-type flip-flop, holds the next partial remainder by a clock, and resets the held data to zero by a reset input.

Lower input register 4 of dividend register 2
Is a P / S shift register 5 for converting parallel to serial, and the P / S
The output of the shift register 5 is connected to both the least significant bit of the adder 6 and the input selection circuit 1 as the least significant bit of the next dividend.

The subtraction of this divider is generally performed by adding a two's complement (negatively adding 1). Therefore, the input register of the divisor is an inverting buffer (16 bits) for taking the negation, and the adder 6 is included in the subtraction unit. Add 1 to the carry input of the adder to do a +1. The carry output of the adder is used to detect the subtraction overflow.

In the subtraction shift operation, the shift operation itself connects the lower bits of the output of the dividend register 2 excluding the most significant bit to the adder 6, and the least significant bit of the adder 6 is as described above. As described above, the P / S shift register 5 is supplemented by 1 bit.

The division determination circuit 7 according to claim 1 is realized by an OR circuit. The most significant bit of the dividend register and the carry output of the adder are input to the OR circuit. One of the outputs of the division determination circuit 7 is connected to the output enable (OE) of the tristate buffer which is the subtraction selection circuit 8, and the other is connected to the S / P shift register 10 which is the quotient register 9.

When the subtraction selection circuit 8 outputs 1 indicating that subtraction is possible, the subtraction selection circuit 8 sets the subtraction result to the next partial remainder. Therefore, the subtraction determination output is once received by the NOT circuit and then connected to the output enable (OE) so that the inverse logic output enable of the buffer to which the subtraction result is connected operates.

When the subtraction determination circuit 7 outputs 0 indicating that subtraction is not possible, the partial remainder before subtraction is set as the next partial remainder. In this case, the buffer holding the data before the subtraction operates for output.

The quotient register 9 holds the output of the subtraction determination circuit 7 in synchronization with the subtraction shift in the S / P shift register 10 for converting serial into parallel. The first bit held is the most significant bit of the quotient, and the last bit is the least significant bit. The subtraction shift is performed in eight stages to obtain an 8-bit quotient.

FIG. 2 shows the output of the timing generation circuit for operating this division circuit. The operation of FIG. 1 will be described with reference to FIG.

First, a reset signal is sent, and the D-type flip-flop circuit for higher bits of the dividend register 2 and the shift register of the quotient register 9 are cleared to zero. Next, the load signal for input data becomes 1, and the input value selection circuit 1 sends the upper bits of the input dividend to the selection circuit.

In this state, the output of the high-order input register 3 shows zero, while the output of the divisor register 11 has the same value (the negation of the divisor) from the beginning. The carry output of 6 becomes 1, and the subtraction determination circuit 7 indicates that subtraction is not possible.

Then, the subtraction selection circuit 8 outputs the value which is not the subtraction result (in this case, the input load is between 1 and the input value).
Are sent to the upper input register 3 of the dividend register 2. On the other hand, when the load signal (L) is 0, the P / S shift register 5, which is the lower input register 4, holds data regardless of clock input. At the time of loading, the first bit (that is, the maximum bit input to the lower input register) is output.

In this state, the first clock is inserted. The high-order input register 3 holds the input value, and the subtraction data of the first stage are available. Since the P / S shift register 5 has already output the first bit, it does not give the clock only the first time.

The adder 6 outputs an addition result and a carry output. The subtraction determination circuit 7 determines whether or not subtraction is possible based on the carry output and the most significant bit of the dividend register,
As a result, the subtraction selection circuit selects the next partial remainder and sends it to the upper input register 3 (but the data in the upper input register 3 is not changed until the next clock is inserted). The S / P shift register 10, which is the quotient register 9, latches the output of the subtraction determination circuit 7 with the clock inverted clock. This is the most significant bit of the quotient.

Next, the second clock is inserted. The upper input register 3 latches the next partial remainder in synchronization with the clock. On the other hand, the P / S shift register 4 outputs 1 bit in synchronization with the clock from the next stage. The addition and subtraction discrimination is performed to obtain the next bit of the quotient.

After that, the third to eighth clocks are sequentially sent, the same operation is performed, and the 8-bit quotient is stored in the quotient register 9. Finally, the output clock is received and transferred from the quotient register to the output register 12 as parallel data.

FIG. 3 shows an example of division. Highest 1 of dividend
The 6 bits are held in the D flip-flop, and the lower 8 bits are held in the shift register. The lower bits held in the shift register are output one bit for each number of stages of subtraction shift.

At the first stage, since the most significant bit of the dividend is 1, subtraction is possible. In the second stage, since the most significant bit of the partial remainder and the carry output of addition are both 0, subtraction is not possible and the previous partial remainder becomes the next partial remainder.

Thereafter, the same calculation is performed, the subtraction discrimination output is held for each stage, and after the subtraction shift of 8 stages, the holding of the eight subtraction discrimination outputs is the quotient, which is obtained in the first stage. The one obtained is the most significant bit, and the one obtained in the eighth stage is the least significant bit.

As an example of the present invention, the case where the 24-bit dividend is divided by the 16-bit divisor to obtain the 8-bit quotient has been described above. The data size is not limited to this example, and when the number of bits of the divisor is smaller than the number of bits of the dividend, an effect according to the number of bits of the divisor is obtained.

[0048]

As described above, according to the division circuit of the present invention, when the data size of the dividend, the divisor, and the quotient is limited as in the division in the fuzzy center-of-gravity operation described above, Is effective for making the compact.

Further, in the conventional method, a register and an arithmetic unit having a data size twice the dividend are prepared, whereas according to the present invention, division can be performed by a subtractor for the number of divisor bits. In the case of the division of the dividend of 24 bits and the divisor of 16 bits described in the embodiment, a 48-bit subtractor is conventionally prepared, but in the present invention, the divisor bit, that is, 1
A 6-bit subtractor is enough.

Along with this, the number of registers for input and output can be greatly reduced from the conventional double number of the dividend, and the number of bits for each of the divisor and the dividend is sufficient.

Also, the operation clock is 24 in the conventional method.
24 clocks are required because the subtraction shift of the stage is necessary, whereas the subtraction shift unit of the present invention uses clocks corresponding to the number of bits of the quotient (8 clocks to obtain the quotient of 8 bits in the above embodiment). ) Is sufficient, and division can be performed at high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a divider circuit of the present invention.

FIG. 2 is a diagram showing an output of a timing generation circuit for operating a division circuit of the present invention.

FIG. 3 is an operation explanatory diagram of the divider circuit of the present invention.

[Explanation of symbols]

 1 Input Selection Circuit 2 Dividend Register 3 Upper Input Register 4 Lower Input Register 5 P / S Shift Register 6 Adder 7 Subtraction Discrimination Circuit 8 Subtraction Selection Circuit 9 Quotation Register 10 S / P Shift Register 11 Divisor Register 12 Output Register

Claims (2)

[Claims] 1. A dividend register for inputting a dividend and holding a partial remainder during a division operation, a divisor register for inputting a divisor and holding a divisor during a division operation, a value of the dividend register and the divisor. A subtraction circuit that performs subtraction with the value of the register, a subtraction determination circuit that determines whether or not subtraction is possible, a subtraction result if subtraction is possible, and a dividend before subtraction is sent to the dividend register as the partial remainder for the next subtraction if subtraction is not possible A subtraction selection circuit, a quotient register that sequentially holds the subtraction determination signal,
A subtraction shift type division circuit including a timing control circuit for controlling arithmetic processing, wherein a dividend register has a most significant bit connected to a subtraction determination circuit, and outputs 1 when the divisor is larger than the dividend. The output of the overflow of the subtraction circuit is also connected to the subtraction determination circuit, and the subtraction determination circuit determines that subtraction is possible if either the most significant bit of the dividend or the overflow is 1. .. 2. A dividend register for inputting a dividend and holding a partial remainder during a division operation, a divisor register for inputting a divisor and holding a divisor during a division operation, a value of the dividend register and the divisor. A subtraction circuit that performs subtraction with the value of the register, a subtraction determination circuit that determines whether or not subtraction is possible, a subtraction result if subtraction is possible, and a dividend before subtraction is sent to the dividend register as the partial remainder for the next subtraction if subtraction is not possible A subtraction selection circuit, a quotient register that sequentially holds the subtraction determination signal,
A subtraction shift type division circuit including a timing control circuit for controlling arithmetic processing, wherein the number of digits of the subtraction circuit is equal to the number of digits of the divisor, and the dividend register has the most significant bit connected to the subtraction determination circuit, The register is held from the most significant bit of the dividend up to the divisor bit, the lower bits of the dividend are made up of shift registers by the difference between the number of digits of the dividend and the number of digits of the divisor, and the output of the register of the most significant bit of the dividend is the most significant bit. It is connected to the subtracter except bits, the serial output of the shift register is connected to the least significant bit of the subtractor, and outputs one bit from the upper bit in the shift register each time the subtraction is performed. A division circuit characterized in that.