JPH0560849U - Image recorder - Google Patents

Abstract

(57) [Abstract] [Purpose] A memory capacity for holding line data as bit data in an image recording device that takes in vector image data, develops it on a bitmap, and records it line by line with a line head. To reduce the device cost. A control circuit for generating line data for each several lines based on vector data for one screen and a line data holding unit for holding at least line data for these several lines, and a control circuit for sequentially processing every several lines are provided. Provided.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an image recording device for recording an image created by an image creating means such as a CAD device with a line printer. In particular, it relates to a device in which the data created by the image creating means is so-called vector data.

[0002]

[Prior Art]

 This type of apparatus converts vector format image data from an image creating apparatus such as CAD into so-called bit format data so that it can be recorded by a line head. A conventional general apparatus has a means for taking in one screen of image vector data from an image creating apparatus and converting it into bit data as recording data for a plurality of lines. Then, all the recording line data are aligned and the post-recording is started.

[0003]

[Problems to be solved by the device]

 In such a device, it is necessary to convert all the image vector data into line data and hold the line data. Therefore, a device that records a large size image needs a large capacity memory. was there.

[0005]

[Means for Solving the Problems]

 Therefore, in the present invention, in the image recording apparatus for recording the image vector data for one screen from the image apparatus such as the CAD apparatus as a dot image of L rows × M columns (L and M are positive integers), Screen buffer memory means for taking in at least one screen of image vector data from the image device, and line data of n (1≤n <L) row units for one screen of image data taken in the screen buffer memory means Line data creating means, line data holding means for fetching and holding line data in units of n lines created by the line data creating means, and accessing the line data holding means to obtain data of a desired line by k (1 ≤k integer) Words are fetched in sequence and the memory area where the fetched data is held is cleared. A data transmission / reception logic circuit for transmitting the fetched data to a head drive circuit, a line head driven when the data of the desired line is aligned in the head drive circuit, and a control circuit for controlling these elements Further, the control circuit is arranged such that when the line data in the line data holding means is being taken out and cleared by the data transmission / reception circuit, the n lines of lines related to the next recording are recorded. When the in-data is created by the line data creating means and the free area of the memory area of the line data holding means is ready to hold n lines of line data, it is created by the line data creating means. The n-line line data is controlled to be held by the line data holding means.

[0006]

[Action]

 This apparatus creates line data for recording, which is composed of bit data of the first n lines, based on all the image vector data, and sets the record data of the n lines as a set and holds it in the line data holding means. Bit data is taken out from the line data holding means, for example, one word (16-bit data group) for each line to be recorded, and recording is performed via a drive circuit. During this period, the line data creating means creates line data of n lines for the next recording. When the vacant area of the memory of the line data holding means is ready to hold the n-line recording data, the n-line recording data for the next recording is stored in the line data holding means. Sent from. In this way, in this device, the memory having a relatively small capacity is used cyclically and efficiently.

[0007]

【Example】

 FIGS. 1, 2 and 3 each show an apparatus according to one embodiment of the present invention. FIG. 1 is an explanatory diagram showing the overall structure of this recording apparatus, and FIG. 2 is a diagram showing the line data of this recording apparatus. FIG. 3 is an explanatory diagram schematically showing the outline of fetching and transmitting / receiving, and FIG. 3 is an explanatory diagram showing the configuration of the data transmitting / receiving logic circuit of the device of this embodiment. In the figure, 11 is a screen buffer memory, 12 is line data creating means, 13 is line data creating means, 14 is a data transmission / reception logic circuit, 15 is a control circuit, 16 is a head drive circuit, and 17 is a line head.

First, the outline of the recording apparatus of the present invention will be described with reference to FIG. Image data in vector format is input into this device from a higher-level device such as a CAD device. The vector image data includes, for example, data D (x0, y0; x1, y1) indicating that a straight line from the starting point (x0, y0) to (x1, y1) is drawn. Such data is stored in the screen buffer memory 11 for one screen.

The line data creating means 12 develops all the vector image data stored in the screen buffer memory 11 one by one on a bit map from the first line to the n-th line. Therefore, a memory (not shown) having a capacity for storing bit data of n lines is mounted in the line data creating means 12. When the first n-line line data is created by the line-data creating means 12, the n-line line data is output to and held by the line-data holding means 13. Then, the line data creating means 12 starts creating line data for the next n lines. As described above, in this apparatus, as shown in the upper diagram of FIG. 2, line data created for every n lines is stored one after another as long as there is an empty area in the line data holding means 13. There is.

The data of the n lines held in the line data holding means 13 is sequentially read from the first line by the data sending / receiving logic circuit 14 for each data group of 1 word and sent to the head drive circuit 16. At this time, the data transmission / reception logic circuit 14 clears the memory area in which the read data group is stored. As shown in the lower diagram of FIG. 2, this operation takes out the data group (11) in the first row, first column, and sends it to the head drive circuit 16 in the next stage when sending the data in the first line. The memory area of the line data holding means 13 in which the data group is stored is cleared. Then, the data group (12) in the first row, second column is similarly taken out, sent to the head drive circuit 16, and the memory area in which this data is stored is cleared. By repeating this operation one after another, the data group (1 m) in the first row and the m-th column is taken out and sent to the head drive circuit 16 to clear the memory area.

Since all data for recording one line is aligned in the head drive circuit 16, the line head 17 is driven based on this data to record the first line. At this stage, the line data holding area of the first line of the line data holding means 13 is cleared, and the line data created by the line data creating means can be written. Next, the data group (21) in the second row, first column stored in the line data holding means 13 is taken out by the data transmission / reception logic circuit 14, sent to the head drive circuit 16, and the data storage area is cleared. To be done. By sequentially performing these operations, the line head 17 can be made to perform line recording one after another. When all the data of the lines up to the n-th row are taken out and recorded by the line head 17 via the head drive circuit 16, there is a free area for at least n lines in the memory of the line data holding means 13. In such a state, the data for n lines created by the line data creating means 12 is held in the empty area of the line data holding means 13. At this time, the data transmission / reception logic circuit 14 operates in the same manner as described above, and performs the operation of fetching, transmitting and clearing the data of the (n + 1) th row and thereafter.

FIG. 3 is a configuration block diagram of the data transmission / reception logic circuit 14. A data fetching circuit 141 for reading out data, which is composed of an address counter 140, a data requesting circuit and a memory reading out circuit, and after this data fetching circuit 141 reads out the data, the storage area of the data is cleared. A data clear circuit 143 having a zero data creating circuit and a memory writing circuit, and a data sending circuit including a latch circuit for sending the data read by the data fetching circuit 141 to the head drive circuit 16 and a parallel-serial conversion circuit. And a circuit 142.

The address counter 140 generates the address of the first data of the data group to be read based on the instruction of the control circuit 15. This address information is sent to the memory read circuit of the data read circuit 141 and the memory write circuit of the data clear circuit 143. The memory reading circuit reads a group of data from the line data holding means 13 and sends it to the data transmitting circuit 142. Then, at the stage of this transmission, a clear command is issued to the data clearing means 143, zero data is created, and the storage area of the memory of the group of data read out through the data write circuit is cleared. When the data transmission circuit 142 completes the transmission of the group of data received from the data extraction circuit to the head drive circuit 16, a transmission completion signal is issued, the information is transmitted to the control circuit 15 and the next group of data is transmitted. The same data transmission / reception operation is performed. The control circuit 15 generates a command for causing the head drive circuit 16 to perform a recording operation based on the transmission completion information.

As described above, by configuring the data transmission / reception logic circuit 14 with hardware, the processing speed can be increased as compared with software processing. These circuits are composed of electronic circuits, and have a configuration of operating independently of the control of the control circuit 15 except for the start and end of the operation. That is, the data transmission / reception circuit 14 has a configuration in which information such as whether or not the line data relating to recording is held in the line data holding means 13 is obtained from the control circuit 15. Therefore, the control circuit 15 does not need to perform much control on the data transmission / reception logic circuit 14 and has the advantage of reducing the load.

[0015]

[Effect of the device]

 As described above, according to the present invention, the line data is created every several lines and processed in order, so that it is possible to perform the processing with a relatively small capacity memory without decreasing the recording speed. Therefore, the cost of the device can be reduced.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an overall configuration of an image recording apparatus showing an embodiment of the present invention.

FIG. 2 is a line data holding unit 1 shown in FIG.
3 is a schematic diagram illustrating the operations of the data transmission / reception logic circuit 3 and the data transmission / reception logic circuit 14. FIG.

3 is a configuration block diagram of a data transmission / reception logic circuit 14 shown in FIG.

[Explanation of symbols]

 11: Screen buffer memory 12: Line data creating means 13: Line data holding means 14: Data transmission / reception logic circuit 15: Control circuit 16: Head drive circuit 17: Line head

Claims (1)

[Scope of utility model registration request] 1. Image vector data for one screen from an image device such as a CAD device is L rows × M columns (L and M are positive integers).
In the image recording apparatus for recording as a dot image of, the screen buffer memory means for taking in at least one screen of image vector data from the image apparatus, and n (1 ≦ n <L integer) Line data creating means for creating line data in units of lines, line data holding means for loading and holding line data in units of n lines created by the line data creating means, and accessing the line data holding means. , A data transmission / reception logic that sequentially fetches data of a desired line in k (integer of 1 ≦ k) words, clears a memory area in which the fetched data is held, and further sends the fetched data to a head drive circuit. Circuit of the desired line to the head drive circuit. Has a line head that is driven at the stage of being aligned, and a control circuit that controls these elements. Further, the control circuit is configured such that the line data in the line data holding means stores When the taking-out and clearing operations are being performed, the line data creating means creates n lines of line data relating to the next recording, and the empty area of the memory area of the line data holding means is n.
An image recording apparatus, which controls to hold n lines of line data created by the line data creating means in the line data holding means when the line data of the row can be held.