JPH0559604B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an operational amplifier, and more particularly to a CMOS integrated circuit operational amplifier having a power-down function.

[Conventional technology]

CMOS integrated circuits are often provided with a power-down function to take full advantage of their low power consumption. Also, in order to save on external terminals of integrated circuits, input/output terminals are also used.

FIG. 2 is a circuit diagram of a conventional operational amplifier having such a power-down function and an input/output terminal. When a “H” level voltage is applied to the power-down control signal input terminal 11, pMOST M1
6 is off, nMOST M15 is on,
The potential is the same as the gate and drain of pMOST M14 and nMOST M13, and nMOST
A predetermined current flows through M12, and therefore bias currents are supplied to the differential amplifier circuit 4 and level shift circuit 5, respectively. The differential amplifier circuit 4 performs a normal operation of amplifying the difference signal between the negative phase input signal terminal 10 and the positive phase input signal terminal 9. pMOST M8 and nMOST M9 forming complementary output circuit 6
The gates of are connected to the output terminal of the differential amplifier circuit 4 and the output terminal of the level shift circuit 5, respectively,
pMOST M17 is off, feedback circuit nMOST M
10 and pMOST M11 are on, so the output circuit 6 operates normally. Also nMOST M18 and
Since both pMOST M19 are on, the analog switch 8 is conductive and the input/output terminal 12 can be used as an output terminal. Next, when a “L” level signal is applied to the power-down control signal input terminal 11, pMOST M16 is turned on, nMOST M15 is turned off, and pMOST M14 is turned off.
nMOST M5 and M6 are also turned off. pMOST M
17 is turned on, and pMOST M8 is turned off as the gate voltage increases. In this way, the bias voltage generation circuit 3, the differential amplifier circuit 4, the level shift circuit 5, and the output circuit 6 are all brought into a power-down state. Also, at this time, since the analog switch 8 is non-conductive, the input/output terminal 13 can be used as an input terminal.

[Problem that the invention seeks to solve]

The conventional operational amplifier described above has an output circuit of
Since the transistor M17 for bias voltage control is installed only on the pMOST side, the symmetry is not perfect and asymmetrical distortion occurs.In addition, the resistance due to the conduction of the analog switch inserted between the output circuit and the input/output terminal There is also the drawback that the gain decreases.

[Means for solving problems]

The operational amplifier of the present invention includes a bias voltage generation circuit that stops generating bias voltage in response to a power-down control signal, and a first constant current source driven by the output voltage of the bias voltage generation circuit, and a differential amplifier circuit that amplifies an input signal; a level shift transistor controlled by an output signal of the differential amplifier circuit; a first transistor that becomes non-conductive in response to the power down control signal; and a bias voltage generation circuit. a level shift circuit formed by serially connecting a second constant current source driven by the output voltage;
a complementary output circuit including a second transistor and a third transistor of mutually different conductivity types, each of which is supplied with an output signal of the differential amplifier circuit and an output signal of the level shift circuit; and the power down control circuit. A feedback circuit consisting of a CMOS analog switch that becomes non-conductive upon receiving a signal and a feedback capacitor, and is inserted between the output terminal of the output circuit and the output terminal of the differential amplifier circuit, and a feedback circuit that receives the power down control signal. and a fourth transistor and a fifth transistor that respectively bias the second transistor and the third transistor to a non-conductive state.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, a first constant current source consisting of an nMOST M5 is driven by the output voltage of a bias voltage generation circuit 3 that stops generating bias voltage when the voltage of the power down control signal input terminal 11 becomes "L" level. a differential amplifier circuit 4 which amplifies the input signal applied between the positive phase signal input terminal 9 and the negative phase signal input terminal 10; a level shift transistor M7 controlled by the output signal of the differential amplifier circuit 4; nMOST M20 (first transistor) and bias voltage generation circuit 3 become non-conductive when the voltage of the power-down control signal input terminal 11 becomes “L” level.
A level shift circuit 5 is formed by connecting in series a second constant current source consisting of an nMOST M6 driven by an output voltage of
A complementary type output circuit 6 including pMOST-M8 and nMOST M9, and pMOST M10 and nMOST M11 which become non-conductive when the voltage of the power-down control signal input terminal 11 becomes "L" level.
a feedback circuit 7 consisting of a CMOS analog switch and a feedback capacitor C, and inserted between the output terminal of the output circuit 6 and the output terminal of the differential amplifier circuit 4;
When the voltage of the power-down control signal input terminal 11 becomes “L”, pMOST M biases pMOST M8 (second transistor) and nMOS M9 (third transistor) to a non-conducting state.
21 (fourth transistor) and nMOST M2
2 (fifth transistor).

Next, the operation of this embodiment will be explained.

First, when "H" level, for example, power supply voltage V _DD is applied to the power down control signal input terminal 11,
pMOST M16 is off, nMOST M15 is on, the gate and drain of pMOST M14 are at the same potential, and M14 and M13 are connected in the same way.
A predetermined current flows through nMOST M12, and current can also flow through M5 and M6, which form a current mirror with nMOST M12. Also, the gate voltage of M20 is “H”
level so it's on, similarly M21 is off, M10
is turned on. Also, pMOST M22 is off,
nMOST M11 is turned on. Therefore, a bias current is supplied to the differential amplifier circuit 4 and the level shift circuit 5 to enable normal operation, and the output terminal of the differential amplifier circuit 4 (the drains of M2 and M4) is also supplied to the output circuit 6.
A bias voltage is supplied from the output terminal (drain of M6) of the level shift circuit 5. Feedback circuit 7
can also function as a negative feedback circuit consisting of resistance and capacitance. In this way, when the voltage of 11 becomes "H" level, it operates normally as an operational amplifier. At this time, there is a connection between the gate of pMOST M8 and the power supply line.
pMOST M21 is inserted in the off state,
nMOST There is an nMOST between the gate of M9 and the ground line.
Since M22 is inserted in the OFF state, the symmetry of the output circuit is always maintained from the perspective of stray impedance, so no asymmetric distortion occurs.
Further, since the output circuit and the input/output terminal 12 functioning as an output terminal are directly connected, the gain is improved compared to the conventional example.

Next, when an "L" level voltage (eg, GND terminal voltage) is applied to the power-down control signal input terminal 11, M16 is turned on, M15 is turned off, and M14 is turned off as the gate voltage increases.
Therefore, the bias voltage generation circuit 3 stops generating the bias voltage, and M5 and M6 are turned off.
pMOST M21 turns on when the gate voltage becomes "L", turning pMOST M8 off.
Similarly, nMOST M22 is turned on and nMOST
Turn M9 off. Also, since nMOST M20 is off, there is no voltage from power supply voltage terminal 1.
The current path through nMOST M7 to the drain of nMOST M22 is blocked. this
If nMOST M20 is not inserted,
Since the gate potential of nMOST M7 is in a floating state or the value obtained by subtracting the voltage drop of pMO M4 from the power supply voltage _VDD , M7 is not necessarily turned off, but is connected between the power supply line and the ground line through the above-mentioned current path. The power-down function may be impaired due to current flowing through the device. As described above, the power-down control input terminal voltage becomes "L" level. This operational amplifier is completely powered down. Then, at this time, nMOST M10 and pMOST M of the feedback circuit 7
11 are both turned off, the input/output terminal 12 is in a high impedance state and can be used as an input/output terminal to other circuit sections.

It goes without saying that the above explanation also applies to a MOS transistor of the doden type, in which the voltage and signal polarities are reversed.

〔Effect of the invention〕

As explained above, the present invention uses a power-down control signal to level-shift a differential amplifier circuit and its output using a bias voltage generation circuit that stops generating bias voltage, and then applies a bias voltage to a level shift circuit that applies the level-shifted signal to an output circuit. By inserting a first transistor in the level shift circuit that supplies power and is turned off by a power-down control signal, and similarly providing fourth and fifth transistors that turn off the output circuit in the output circuit, the output circuit An operational amplifier having a power-down function can be obtained without compromising the symmetry. In addition, by making the analog switch constituting the negative feedback circuit inserted between the output terminal of the differential amplifier and the output terminal of the output circuit non-conductive by the power-down control signal, the output of the operational amplifier is reduced in the power-down state. The terminal can be effectively used as an input terminal to other circuits.

As described above, the present invention has the advantage of providing an operational amplifier having a power-down function and an input/output terminal without impairing gain or distortion characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional example. 1...Power supply voltage terminal, 2...GND terminal, 3...
...Bias voltage generation circuit, 4...Differential amplifier circuit,
5...Level shift circuit, 7...Feedback circuit, 8...
...analog switch, 9...positive phase signal input terminal,
10... Reverse phase input signal terminal, 11... Power down control signal input terminal, 12... Input/output terminal,
I...Inverter, M1, M2, M5, M6, M
7, M9, M10, M12, M13, M15, M
18, M20, M22...nMOST, M3, M
4, M8, M11, M14, M16, M17, M
19, M21...pMOST.

Claims (1)

[Claims] 1 A differential amplifier that amplifies a predetermined input signal, which includes a bias voltage generation circuit that stops generating a bias voltage upon receiving a power-down control signal, and a first constant current source that is driven by the output voltage of the bias voltage generation circuit. an amplifier circuit, a level shift transistor controlled by the output signal of the differential amplifier circuit, a first transistor that becomes non-conductive in response to the power down control signal, and a first transistor driven by the output voltage of the bias voltage generation circuit. a level shift circuit formed by connecting two constant current sources in series; a second transistor having a different conductivity type and which is supplied with an output signal of the differential amplifier circuit and an output signal of the level shift circuit, respectively; between the output terminal of the output circuit and the output terminal of the differential amplifier circuit, which is comprised of a complementary output circuit including a transistor No. 3, a CMOS analog switch that becomes non-conductive in response to the power down control signal, and a feedback capacitor; a fourth transistor for biasing the second transistor and the third transistor into a non-conducting state in response to the power-down control signal;
An operational amplifier comprising: a transistor and a fifth transistor.