JPH055773A - Test circuit of logic ic - Google Patents

Abstract

PURPOSE:To make it unnecessary to form input data, to reduce output data, to easily form test data, and to make a test clock high-speed thereby to easily conduct real time testing. CONSTITUTION:One output signal of an LFSR 4 is input to an input testing terminal A of a data selecter 12, while all the output signals of the LFSR 4 are input to an input testing terminal A of a data selecter 13. On the other hand, an output signal SR of a RAM 1 is input to an A input terminal of a data selecter 3 at the output side of the RAM 1 to be tested. At% input terminal B of the data selecter 3 is connected to a GND. An output terminal of the data selecter 3 is connected to one input terminal to an EXOR 14. True other input terminal of the EXOR 14 is connected to an input of the final stage of an LFSR 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a logic IC, and more particularly to a test circuit for a functional circuit inside the IC.

[0002]

2. Description of the Related Art Conventionally, this type of test circuit has a test terminal 9, a data selector 3, a data selector 12 and a data selector 13 as shown in FIG. The data selectors 3, 12 and 13 select whether the output data is A or B according to the input signal S9 from the test terminal 9. In the case of this example, when the input of the test terminal 9 is “0”, A,
When "1", B is selected.

During the test, the input of the test terminal 9 is set to "0", SD is input from the test data input terminal 10 and the address SA is input from the test address input terminal 18,
The output signal SO from the test output terminal 5 was tested. Alternatively, as shown in FIG. 5, an address is generated by an internal test address generator 19.
Here, the function of the RAM under test 1 is tested.

[0004]

In this conventional logic IC test circuit, it is necessary to create all the test data, the test address, and the expected value of the output signal in the case of FIG. If the size of the RAM is large, it takes time to create the data.

Further, since the test input signal and output signal are input and output to the outside, there is a problem that the input / output delay time and the timing deviation between terminals are large. Therefore, when the circuit under test is required to operate at high speed, it is often impossible to confirm that it operates in real time.

In the case of FIG. 5, it is not necessary to input the test address, but it is necessary to separately test that the test address generator 19 itself operates normally, and the scale of the circuit under test is increased. In this case, there is a problem that the test of the test address generator 19 itself becomes complicated.

[0007]

A test circuit for a logic IC according to the present invention is a test circuit for testing a first data selector controlled by a test setting signal in a circuit under test of a plurality of logic function circuits forming the IC. Data input terminal and second
The test data and the test address are input through the test address input terminals of the data selector of FIG. 3, and the output signal of the circuit under test is input to one end of the third data selector controlled by the data output selection signal. In the test circuit of the logic IC which outputs the test output signal from the test output terminal, the test data input terminal inputs the test clock through the first exclusive OR which inputs the data inversion signal. Connected to one end of the output of the first linear feedback shift register for outputting the test input data, and the test address input end is connected to the remaining plural ends of the output of the first linear feedback shift register, respectively. The output terminal of the third data selector is connected to the input terminal of the second linear feedback shift register via one input terminal of the second exclusive OR. Continued, and outputs the test output signal of the linear feedback shift register of the second is constituted by the period the other input terminal of said second exclusive-OR is supplied to the test output terminal.

[0008]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the first embodiment of the present invention.
One of the outputs of the linear feedback shift register (hereinafter referred to as LFSR) 4 is input to the test side input terminal A of the data selector 12, and the test side input terminal A of the data selector 13 is L
All the output signals of FSR4 are input respectively. On the other hand, the output signal SR of the RAM 1 is input to the A input of the data selector 3 on the output side of the RAM under test 1, and the B input terminal is GND.
It is connected to the. The output end of the data selector 3 is EXO
It is connected to one input of R14 and the other input end of EXOR14 is connected to the final stage output of LFSR20.

Next, the operation of the two LFSRs 4 and 20 will be described. FIG. 2 is an example when the LFSR 4 is configured with 3 bits. In this LFSR, G (x) is a code logic and operates according to a rule called a generator polynomial, which is represented by the sum of the cube of x and (x + 1). This means that the cube of the output x of the final stage is added (EXOR) to the power of x of the input of the first stage and the cube of the input x of the second stage.

A circuit is constructed according to this rule, and three D
-When a clock is input from the test clock input terminal 8 after setting the initial value of the FF15 to a value other than "0", the values of the first power, the second power, and the third power of x change as shown in FIG. 2B. Then, at time 7, the value returns to the same value as time 0, and this is repeated thereafter. 1st, 2nd, and 3rd powers of x are 3 bits in one cycle
Of the values represented by, all values other than 0 are taken only once.

This rule can be similarly maintained even when the order of G (x) becomes large. Therefore, for example, when G (x) is the sum of x to the 10th power, the 3rd power and the 1st power, the power of 2 to the 10th power is used. One cycle consists of 1024 clocks.

Next, the data compression by the LFSR 20 will be described. Of the data series generated by LFSR4 in which G (x) is the cube of x, the sum of 1st power and 0th power, paying attention to the output of the last stage, “3rd power of x”, this data series is time 0 From the beginning, V0 = (0010111) is obtained. When this v0 is input to the LFSR shown in FIG. 3A, when the initial values of the three D-FFs 15 are set to 0, the operation is performed as shown in FIG. Then, the values of the first power, the second power, and the third power of x become (100), which is the same as the initial value at time 0 in FIG.

Next, when a series v1 = (0101110) starting from time 1 and ending at time 7 is input as input data, the final value becomes (010) as shown in FIG. It is the same as the value of the first power, the second power, and the third power of x at time 1. In the same way, no matter where the sequence started from time 2 to 6 is input, the power of x, 2 of x in FIG.
The final value of the power of 3 and the power of 3 correspond to the initial value of the power of 1, 2 and 3 of x in FIG.

Due to the characteristics of the LFSR described above, in the embodiment of FIG. 1, the LFSR 4 generates a test address and data corresponding to the capacity of the RAM under test 1, and RA
The output signal of M1 can be compressed by the LFSR 20.

After that, the data output selection terminal 6 is used for EX.
With one input of OR14 set to 0, a test clock is further input, and the compressed data is output to the test output terminal 5
If the data matches the initial value of LFSR4, it can be determined that the operation of RAM1 is normal.

For testing the test circuit itself, L
If the FSR 4 and the LFSR 20 are directly connected, the same test can be performed. Further, in order to write data which is "1" or "0" inverted in the RAM, "1" may be input to the data inversion signal input terminal 21.

[0017]

As described above, the present invention provides the LFSR.
By using LFSR and LFSR, generation of input data becomes unnecessary, and since output data of the conventional 1024 bits is relatively small at 10 bits, it is easy to create test data.

Furthermore, when conducting a test in real time,
Since only the test clock is input at high speed and the final result is output at low speed, real-time testing becomes easy. In addition, the test of the test circuit itself is also performed by LFSR4
If R20 is directly connected, it can be easily checked whether both LFSRs are operating normally.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

2A is a principle diagram of the LFSR 4 of FIG. 1, and FIG. 2B is an operation diagram thereof.

3A is a principle diagram of the LFSR 20 of FIG. 1, and FIG.
Is an operation diagram thereof.

FIG. 4 is a block diagram of an example of a conventional logic IC test circuit.

FIG. 5 is a block diagram of another example of a conventional logic IC test circuit.

[Explanation of symbols]

 1 RAM under test 2 RAM data output terminal 3 Data selector 4 LFSR 5 Test output terminal 6 Data output selection terminal 7 Address input terminal 8 Test clock input terminal 9 Test terminal 10 Data input terminal 12 Data selector 13 Data selector 14 EXOR 15 D-FF 16 Data series input terminal 17 Test data input terminal 18 Test address input terminal 19 Test address generator 20 LFSR 21 Data inversion signal input terminal 22, 23 EXOR

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G06F 11/22 330 B 9072-5B 6912-2G G01R 31/28 P

Claims (1)

Claim: What is claimed is: 1. A test data input terminal of a first data selector controlled by a test setting signal and a second test circuit of a plurality of logic function circuits constituting an IC. The test data and the test address are input through the test address input terminals of the data selector, and the output signal of the circuit under test is input to one end of the third data selector controlled by the data output selection signal, Logic IC that outputs a test output signal from the test output terminal
In the test circuit, the test data input terminal is
It is connected to one end of the output of the first linear feedback shift register which inputs the test clock and outputs the test input data through the first exclusive OR which inputs the data inversion signal, and The address input terminal is the first
Connected to the remaining plural ends of the output of the linear feedback shift register, and the output end of the third data selector is connected to the second end.
Is connected to the input end of the second linear feedback shift register via one input end of the exclusive OR, and the test output signal output from the second linear feedback shift register is supplied to the test output terminal. A test circuit for a logic IC, characterized in that it is input to the other input terminal of the second exclusive OR for a period. 2. The test circuit for a logic IC according to claim 1, wherein the first and second exclusive ORs are directly connected to test the function of the test circuit.