JPH0557571A - Identification system - Google Patents

Abstract

PURPOSE:To make the same data easily writable in a memory specified area of a data carrier. CONSTITUTION:Identical data are written in a specified area of a memory 1 of an identical data writing means 6 to be obtained from the host means. At the time of verifying these data, all data in the specified area are read out by a write data verifying means 7 and a congruity with the verifying data is made so as to be identified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification system for identifying various data such as parts and products.

[0002]

2. Description of the Related Art Conventionally, in order to mechanize the management of tools of machine tools and the identification of parts, products, etc. on an assembly and conveyance line in a factory, a system for identifying and managing various articles is required. Therefore, as in Japanese Patent Laid-Open No. 64-71396, a data carrier having a memory is provided for an object to be identified, and necessary information is written in the data carrier by data transmission from the outside, and the information is read out as necessary. An identification system based on the above has been proposed. Such a data carrier is used by being attached to, for example, a pallet or the like, and is configured to write or read necessary data to / from the data carrier from a write / read control unit arranged on a side of a transportation path of the pallet.

[0003]

In such a conventional identification system, it is possible to clear all the user area in the data carrier, but clear only a specific area or write all predetermined data. I couldn't. Therefore, in the conventional identification system, after initializing the use area, the host computer first transmits data to the ID controller, and then the ID controller transmits a large amount of data to the data carrier side for writing. There is a need. FIG. 8C shows a write command for writing the data “00 ... 00” from the specified memory address “0100” and its response, and all the overwritten data is transmitted. Further, FIG. 8 (d) shows a read command for reading the written portion and its response for identifying whether or not this data has been normally written, which corresponds to 80 bytes from the address "0100". When the data is read, the 80-byte data is read and returned. In this way, all the data is read and the ID is written in order to write the data and confirm the written contents.
It is necessary to confirm (verify) on the controller side,
There was a drawback that it took a lot of communication time.

The present invention has been made in view of the above problems of the conventional identification system, and enables the same data to be continuously and easily written in a predetermined area of the memory and the contents thereof can be confirmed. To do this is a technical issue.

[0005]

The present invention is based on FIG. 1 (a),
As shown in (b), a memory 1 for holding data, a data carrier 3 having a data transmission means 2 for demodulating an externally applied command and data and transmitting the data read from the memory, and a data carrier. And a write / read control unit 5 having a data transmission means 4 for transmitting data between them, wherein the write / read control unit or the data carrier is a data carrier according to a command from a host. The same data writing means 6 for writing the same data to the designated area of the memory, and the write data verifying means 7 for reading all the data in the designated area of the data carrier to identify the match with the write data.
It is characterized by including.

[0006]

According to the present invention having such a feature, the same data writing means writes all the same data in the designated area of the memory of the data carrier. Further, if there is a verify command, all the data written in the designated area is once read out, and the match with the written data is identified by the write data verifying means.
Therefore, it is not necessary to specify an address one by one and transfer and write all the data, and the initialization can be easily performed.

[0007]

2 is a block diagram showing the construction of an identification system according to an embodiment of the present invention. In the figure, the identification system is a pallet 11 on which the parts to be identified are conveyed.
A data carrier 12 directly attached to the data carrier 12, a read / write head 13 for writing and reading data to and from the data carrier 12, and an ID controller 14 connected to the read / write head 13 and controlling the operation thereof are provided. The read / write head 13 and the ID controller 14 form a write / read control unit 5. Further, the ID controller 14 is connected to the host computer 15.

The ID controller 14 controls the writing and reading of data to and from the data carrier 12 as shown in the block diagram of FIG.
U) 21 and a memory 22 for holding the system program and data thereof are provided, and an input / output interface 23 for performing input / output with the host computer 15 is provided. The read / write head 13 has a modulation circuit 24 which receives an output from the CPU 21 and modulates data to be transmitted to the data carrier 12, and a transmission unit 25 which is driven by the output. The transmitter 25 is, for example, Japanese Patent Laid-Open No. 64-71396.
, The data carrier 1 by outputting a signal that periodically combines positive and negative pulses.
2 to transmit data. Also data carrier 1
The received signal obtained from 2 is given to the demodulation circuit 27 via the receiving unit 26. The demodulation circuit 27 demodulates this signal and gives it to the CPU 21. Here, the modulation circuit 24, the transmission unit 25, the reception unit 26, and the demodulation circuit 27 of the read / write head 13 constitute data transmission means 4 for reading data from the data carrier.

Next, the structure of the data carrier 12 will be described with reference to FIG. In FIG. 4, the transmitting / receiving unit 31
Is for receiving and transmitting a signal of a frequency emitted from the read / write head 13, and the reception output thereof is given to the demodulation circuit 32. The demodulation circuit 32 demodulates this signal, converts the data into the original signal, and gives it to the CPU 33. The CPU 33 has a memory 1 via a bus, that is, a program ROM 34 and RA for holding user data.
M35 is connected. Then, the data read from the RAM 35 is converted into a serial signal and given to the transmission / reception unit 31 via the modulation circuit 36. The transmission / reception unit 31 gives a signal to the read / write head 13 side by changing the resonance frequency of the resonance circuit as in the conventional example. Here, the transmission / reception unit 31, the demodulation circuit 32, and the modulation circuit 36 constitute data transmission means 2 which demodulates the command or data given from the ID controller 14 and transmits the read data.

FIG. 5 is a diagram showing a memory map of the memory. Programs of various commands such as the same data write command and verify command are written in the ROM 34. In addition to the command receiving area, the response editing area, the flag area, the work area, and the stack area, the RAM 35 is provided with a user memory area 35a in which the user writes arbitrary data.

Next, the operation of this embodiment will be described with reference to the flowcharts of FIGS. 6 and 7 and the command example of FIG. This flow chart is for CPU3 of data carrier
3 shows the operation. When the operation is started, initialization processing such as clearing of the work area is performed in step 41, and the reception of a command is waited in step 42. I
If a command is received from the D controller 14, the process proceeds to step 43 to analyze the command, determine whether there is an error, and if there is an error, process the error (steps 44 and 45). If there is no error, it is determined in step 46 whether it is an initialization command. FIG. 8A shows an example of this initialization command. "CWA1010000
The CW of "80 *" is an initialization command indicating constant write, "0100" indicates an address, "0080" indicates the size of the area starting from the address, and the following 0 indicates data. If the initialization command is received in step 46, the process proceeds to step 47 and the designated area, in this case, the address "0100" shown in FIG.
All designated data 0 is written in "0179". Then, the process proceeds to step 48, in which this data is read and verification is performed to identify whether it matches the written data. Then, the routine proceeds to step 49, where it is judged whether the verification is normal or not, and if normal, the routine proceeds to step 50 to send a normal end response and finish the processing. “CW00” in FIG.
"*" Is a normal end response.

If the command is not the initialization command in step 46, the process proceeds to step 51 in FIG. 7 to check whether it is the initialization confirmation command. The initialization confirmation command is, for example, "CRA1010000800" as shown in FIG.
* ”. In addition to the initialization confirmation command CR (constant read), this indicates a region designated by an address and a size as in the initialization command. When this command is received, the data at the specified address is read and it is verified whether it matches the received data. Then, the process proceeds to step 53 to check whether the verification is normal, and if it is normal, the process proceeds to step 50 to send a normal end response and finish the process. “CR” in FIG.
00 * ”indicates an example of a normal end response.

If the verification is abnormal in steps 49 and 53, the process proceeds to step 54 and an abnormal end response is sent to terminate the processing. If it is not the initialization confirmation command in step 51, the process proceeds to step 55 to process other commands and sends a response corresponding to it.
(Step 56), the process ends. Here, the CPU 33 in the data carrier 12 achieves the function of the same data writing means 6 for writing the same data in the area designated in steps 46 to 49, and the data in the area designated in steps 51 to 53 is achieved. Achieves the function of the write data verifying means 7 for reading all and identifying the match with the designated data.

In this embodiment, the functions of the same data writing means and the write data discriminating means are added to the data carrier 12, but such a function is provided on the ID controller side and designated by the host computer. It is also possible to write the data continuously to the specified address in the data carrier based on the issued command and to verify the data.

[0015]

As described in detail above, according to the present invention,
When writing the same data in a specific area for initialization or the like, it is not necessary to transmit all the write data, and the transmission time can be shortened. Further, in verification, only by designating an area and setting a value to be verified, it is possible to easily verify only a necessary area and determine whether the result is normal or not.

[Brief description of drawings]

FIG. 1 is a block diagram showing a functional configuration of the present invention.

FIG. 2 is a block diagram showing an overall configuration of an identification system used in the present invention.

FIG. 3 is a block diagram showing configurations of an ID controller and a read / write head.

FIG. 4 is a block diagram showing a configuration of a data carrier.

FIG. 5 is a memory map of a memory according to this embodiment.

FIG. 6 is a flowchart (part 1) showing the operation of the data carrier according to the present embodiment.

FIG. 7 is a flowchart (part 2) showing the operation of the data carrier according to the present embodiment.

8A and 8B are command examples showing an initialization command and an initialization confirmation command of this embodiment and their responses, and FIGS. 8C and 8D are conventional initialization and initialization confirmation. Is an example showing the command and its response.

[Explanation of symbols]

 1 Memory 2, 4 Data Transmission Means 3 Data Carrier 5 Writing / Reading Control Unit 6 Same Data Writing Means 7 Write Data Verifying Means 12 Data Carrier 13 Read / Write Head 14 ID Controller 15 Upper Computer 21, 33 CPU 34 ROM 35 RAM

Claims (1)

[Claims] 1. A data transmission between a data holding carrier, a data carrier having a data transmitting means for demodulating an externally applied command and data and transmitting the data read from the memory, and the data carrier. And a write / read control unit having a data transmission means for performing the write / read control unit, wherein the write / read control unit or the data carrier is a memory of the data carrier according to a command from a host. The same data writing means for writing the same data to the designated area, and the write data verifying means for reading all the data in the designated area of the data carrier and identifying the coincidence with the write data are provided. Identification system characterized by.