JPH03210827A - Data carrier - Google Patents

Abstract

PURPOSE:To surely recognize an error at write by setting a write flag in a memory of a data carrier during data write when a write command is given and resetting the flag when the write is completely finished. CONSTITUTION:A data carrier 12 mounted directly to a pallet 11 by which parts being object of identification are carried and a read write head RW 13 writing/reading a data to/from the data carrier 12 are provided to the system. The data carrier 12 consists of a memory 1 storing a data and a write flag area, a memory control means 2 controlling the data write/read to/from the memory 1, a data transmission means 3 demodulating the command and data given externally and giving the result to the memory control means 2 and a write flag control means 4, and when a write command is given from the data transmission means 3, a write flag is set at data write and a write flag is reset at the end of write.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a data carrier used for the management of tools of machine tools, parts and products in factories, or article identification systems of logistics systems.

[Conventional technology]

In order to mechanize the tool management of conventional machine tools and the identification of parts and products on assembly lines in factories, tools 9 are required.
A system is needed to identify and manage various items such as parts and products. Therefore, as disclosed in Japanese Patent Application Laid-open No. 63-221950, a data carrier having a memory is provided in the object to be identified, necessary information is written in the data carrier by external data transmission, and the information is read out as necessary. An article identification system has been proposed.

FIG. 8 is a diagram showing the overall configuration of such a conventional article identification system, in which a data carrier for holding data is attached to an article. And this data carrier (DC
) is configured so that data transmission with the ID controller is performed via the read/write head.

[Problem to be solved by the invention]

However, according to such a conventional article identification system, data transmission is performed when the data carrier comes into a communicable area with a read/write head (hereinafter referred to as RW), and necessary data is written to the data carrier. At this time, as shown in the memory map of the data carrier in FIG. 9(a), data is written in area E where data is to be written, and the data is written as shown in FIG. 9(b). However, as shown in FIG. 9(C), data writing may not be completed normally. For example, the data carrier may move from the communication area while data is being written to the data carrier, or the metal plate shown by the broken line in Figure 8 may be damaged due to RW.
It may arrive between the head and the data carrier, making communication impossible. Furthermore, the ID controller may stop operating during data writing due to some kind of failure. In such a case, as shown in Figure 9(C), data cannot be written before the normal data writing is completed, and the original data and the written data are different between the areas where the data should be written. There was a drawback that they could be mixed.

Therefore, the next time the data carrier performs data transmission with another ID controller, the data in that area will be read as correct data. Therefore, errors cannot be detected easily thereafter, which has the disadvantage that the production line may be adversely affected.

The present invention has been made in view of the problems of the conventional article identification system, and its technical object is to ensure that errors in writing can be recognized.

[Means to solve the problem]

As shown in FIG. 1, the invention of claim 1 of the present application includes a memory 1 that holds data, a memory control means 2 that controls writing and reading of data to the memory, and demodulating commands and data given from the outside. The data carrier is attached to an article to be identified, and has a data transmission means 3 for transmitting the read data given to the memory control means, and the memory has a write flag area, The device is characterized in that it has a write flag control means 4 that sets a write flag when writing data when a command is given, and resets the write flag after the writing is completed. In addition to this, the invention of claim 2 of the present application provides an area in the memory of the data carrier to hold a write address when a write command is given, and the data carrier records the write address in the memory and performs the write operation. It is characterized by having a write address holding means 5 that clears the area after the command is completed.

[Effect]

According to the invention of claim 1 of the present application having such features, when a write command is given, a write flag is set while data is being written to the memory of the data carrier, and when the writing is completely completed, this flag is set. I'm trying to reset it. Therefore, if data writing is interrupted, this flag remains set, so that it is possible to determine whether there is an abnormality in the data.

Further, in the invention of claim 2 of the present application, in addition to the write flag, the address to be written is held in the memory, and this holding is erased when writing is completed.

Therefore, if the write flag is set, it can be determined that incorrect data is held in the write address portion.

[Explanation of Examples]

FIG. 2 is a block diagram showing the configuration of an article identification system according to an embodiment of the present invention.
A data carrier 12 that is directly attached to the data carrier 12, a read/write head (hereinafter referred to as RW head) 13 that writes and reads data to and from the data carrier 12, and an RW head 13.
ID controller 14 that is connected to and controls its operation.
is provided. RW head 13 and ID controller 1
4 constitutes a write/read control unit. Further, the ID controller 14 is connected to a host computer 15.

Now, as shown in the block diagram in FIG. 3, the ID controller 14 includes a microprocessor (CPU) 21 that controls writing and reading of data to and from the data carrier 12, and a memory 22 that holds the system program and data.
An input/output interface 23 for inputting and outputting data to and from the father's computer 15 is provided. The RW head 13 includes a modulation circuit 24 to which an output is given from the CPU 21 and modulates data to be transmitted to the data carrier 12, and a transmitter 25 driven by the output. The transmitter 25 transmits data to the data carrier 12 by outputting an FSK modulated signal from a coil, for example. Further, the received signal obtained from the data carrier 12 is given to the demodulation circuit 27 via the receiving section 26. The demodulation circuit 27 demodulates this signal and provides it to the CPU 21.

Next, the configuration of the data carrier 12 will be explained with reference to FIG. 4. In FIG. 4, a transmitting/receiving section 31 receives and transmits a frequency signal emitted from the RW head 13, and its reception output is given to a demodulation circuit 32. The demodulation circuit 32 demodulates this signal, converts the data into the original signal, and supplies the signal to the control section 33. The control unit 33 is connected to a memory 34 via a bus, such as a static RAM or EzFR backed up by a battery 35.
A memory 34 configured by OM is connected. The control unit 33 is a memory control means 2 and a write flag control means 4 that control writing or reading of data according to commands and data given from the ID controller 14, as described later, and the read data is converted into a serial signal. The signal is converted and provided to the transmitting/receiving section 31 via the modulating circuit 36. The transmitting/receiving section 31 provides a signal to the RW head 13 by changing the resonance frequency of a resonant circuit, for example, as in the conventional example. Here, the transmitting/receiving section 31. The demodulation circuit 32 and the modulation circuit 38 constitute a data transmission means 3 that demodulates command data given from the ID controller and gives it to the memory control means and transmits the read data.

Now, the operation of such a data carrier will be explained with reference to the flowchart of FIG.

When the data carrier reaches the communication area and receives a command from the RW head 13, it checks whether or not there is a CRC error in the command (step 41).

If there is no CRC error, step 42.43.44
Checks whether it is a write command, read command, or write flag reset command. If a write command is given, the process proceeds to step 45 where a write flag is set, and in routine 46 a write process is performed to write data into the memory 34 based on the data held in the given write command. Then, proceed to step 47 to reset the write flag, and step 48
Then, the response is sent to the ID controller 14. If it is a read command, the process advances from step 43 to routine 49 to perform read processing. If it is a write flag reset command, the process proceeds from step 44 to step 50 to reset the write flag. After completing these processes, the process proceeds to step 48, where a response is sent and the process ends. Here, the control unit 33 performs steps 45 and 47.
In this embodiment, the function of the write flag control means 4 is achieved, which sets a write flag before executing a write command and resets this flag after the execution of the write command. Also, the write flag reset command allows the write flag to be reset from the ID controller 14 side, since this flag cannot be reset if the write state is interrupted.

On the other hand, as shown in the flowchart of FIG. 6, when the ID controller receives a command from the host computer 15, it proceeds to step 51 and sends a status read command to the data carrier side. Data carrier 12
When the device enters the communicable area, a status code is sent by receiving a status read command. I
The D controller 14 receives this status code (step 52) and proceeds to step 53 to check for an error. If there is no error, the process proceeds to step 54, where it is checked whether a write flag is set in the memory 34 of the data carrier 12.

If the write flag is not set, it is determined that normal data is being held because the data carrier has not interrupted writing in the middle of writing in the past. Therefore, the process proceeds to step 55 and a read or write command is sent. Then, in step 56, a response from the data carrier 12 is awaited, and the process proceeds to step 57, where the response is sent to the host computer and the process ends. Also, there is an error when receiving the status code or a write error occurs.

If the flag has been set, a response to that effect is sent to the host computer 15 without sending the read/write command, and the process ends.

In this way, there is no possibility that erroneous data will be read from the data carrier in the middle of writing, and reliability can be improved.

Next, a second embodiment of the present invention will be described. In the second embodiment, the hardware configuration of the data carrier described above is the same, and the address to which data is to be written can be held simultaneously when writing the write flag. FIG. 7 is a time chart showing the operation of this data carrier. When the operation starts, a CRC error is first checked in step 61, and if there is no error, a write command and a read command are issued in steps 62 to 64.

Check whether it is a write flag reset command. In the write command, the start address and number of bytes of data to be written or the final address and data to be written are sequentially given. Therefore, if it is a write command, proceed to step 65 and set the write flag, and step 66
The write address range is held in the memory 34.

The program then proceeds to routine 67 to write the given write data to the memory 34, and then proceeds to steps 68 and 69 to reset the write flag and reset the write address range. After completing all the write processing in this manner, the process proceeds to step 70, where a response is sent to the ID controller 14, and the processing ends. If it is a read command, the process advances from step 63 to routine 71 to perform read processing.
Proceed to step 70 and send a response. If it is a write flag reset command, the process advances from step 64 to step 72 to reset the write flag, returns to step 70, resets the write address range, sends a response, and ends the process. Here, the control unit 33 achieves the function of the write flag control means 4 that sets a write flag before the write process in steps 65 and 68 and resets the write flag after the write process is completed, and in steps 66 and 6
9, the write address range is held before the write process and the memory of this range is reset after the write process is completed.

The function of the write address holding means 5 is achieved. In this way, even if the write flag is set when data is read from the ID controller side, unreliable data areas can be easily recognized from the write address range, making recovery easy.

〔Effect of the invention〕

As explained in detail above, in the invention of claim 1 of the present application,
By setting a write flag while writing data to the memory of a data carrier, even if writing is interrupted, it can be recognized as unreliable when reading data from that data carrier from now on, improving reliability. can be done. In addition to the above-mentioned effects, the invention of claim 2 of the present item (2) has the effect that the data range in which the abnormality exists can be recognized, so that recovery can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the functional configuration of the present invention, FIG. 2 is a block diagram showing the overall configuration of the article identification system used in the present invention, and FIG. 3 is a block diagram showing the configuration of the ID controller and read/write head. 4 is a block diagram showing the configuration of the data carrier, and FIG. 5 is a block diagram showing the configuration of the data carrier.
Flowchart showing the operation of the data carrier according to the embodiment, FIG. 6 is a flowchart showing the processing of the ID controller, FIG. 7 is a flowchart showing the operation of the data carrier according to the second embodiment of the present invention, and FIG. 8 is the article identification system. FIG. 9 is a memory map showing the memory area within the data carrier. 1, 34-----1 memory 2----------
1-Memory control means 3---Data transmission means 4-
---Write flag control means 5-----1.Write address holding means 12--Data carrier 13--Read/write head 14-
------- ID controller 15-- Host computer 21-- CPU 33--11-- Control unit

Claims (2)

[Claims] (1) A memory that holds data, a memory control means that controls writing and reading of data to the memory, demodulating commands and data given from the outside, and transmitting the read data to the memory control means. The data carrier is attached to an article to be identified, and the memory has a write flag area, and when a write command is given from the data transmission means, the data carrier is attached to an article to be identified. A data carrier comprising write flag control means for setting a flag and resetting the write flag after writing is completed. (2) The memory of the data carrier has an area that holds a write address when a write command is given, and the data carrier records the write address in the memory and stores the write address after the write command is completed. 2. The data carrier according to claim 1, further comprising write address holding means for clearing the area.