JPH0557550B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Fields This invention is mainly used in positron ECT devices (emission computer tomography devices), or in other fields such as radiation measurement. Concerning coincidence counting circuits used to perform .

(b) Prior art As is well known, the positron ECT device utilizes the fact that two gamma rays are emitted in a 180° direction when a positron disappears, and two sets of detectors are used to detect these gamma rays.
By detecting two gamma rays flying in a 180° direction, we know that positron nuclides exist on the line connecting the two sets of detectors, and obtain a counting profile. It is necessary to detect and count the simultaneous incidence of gamma rays on two sets of detectors (coincidence), and a coincidence circuit is used for this purpose.

By the way, separate gamma rays that are not caused by a single positron may incidentally hit two detectors at the same time (random coincidence), so it is necessary to remove such gamma rays and count only true coincidences. As a method of correcting this random coincidence, a method of measuring delay coincidence is conventionally known. As shown in Figure 1, this creates a coincidence detection circuit for two input signals A and B.
It is input to AND gate 1, detects simultaneous input of both, and produces an output from flip-flop 2, and one input signal A is sent to delay element 3 for a predetermined period of time (for example, if the pulse width of the input signal is 10 ns, it is approximately 50 ns). ) The other input signal B is input to NAD gate 4 without delay, and this AND gate 4
The output of the flip-flop 5 causes an output from the flip-flop 5. The counted output of flip-flop 2 is the true coincidence count plus the random coincidence count, whereas the counted value of the output of flip-flop 5 can be considered to be only the random coincidence count. can. Because a randomly generated signal is
This is because it can be considered that the probability that they will occur at the same time if delayed is the same as the probability that they will occur simultaneously even if there is no delay. Therefore, by subtracting the count value of the output of flip-flop 5 from the count value of the output of flip-flop 2, it is possible to correct the random coincidence. However, in this circuit, the waveform of input signal A becomes dull due to the delay element, its pulse width becomes narrower, and the coincidence time window width becomes different between the on-time side (AND gate 1 side) and the off-time side (AND gate 4 side). Therefore, the random coincidence count value cannot be sufficiently corrected.

(c) Purpose This invention provides a coincidence circuit that can strictly match the coincidence time window widths of the on-time side and the off-time side, and thereby perform more accurate random coincidence correction. The purpose is to

(d) Configuration The present invention provides a coincidence circuit that detects and counts the simultaneous input of first and second input signals, in which a destination pulse and a predetermined pulse with no relative time delay from the first input signal are used. A first coincidence detection circuit detects the simultaneity of the two pulses related to the first input signal and the second input signal, and The second coincidence detection circuit detects the simultaneity between the simultaneity detection output and the trailing pulse related to the first input signal, and the first coincidence detection circuit detects the simultaneity on the on-time side. By adopting a configuration in which both coincidence and off-time side simultaneity are detected, and later the off-time side simultaneity detection output included therein is determined by a second coincidence detection circuit, the on-time side Since the same first coincidence detection circuit is used on both the off-time side and the on-time side, the time window widths on the on-time side and the off-time side can be made completely the same, thereby improving the accuracy of random coincidence correction.

(E) Embodiment In FIG. 2, one input signal A is input to a flip-flop 7 via an OR gate 6. The inverting output terminal of the flip-flop 7 is connected to a reset terminal via an inverting circuit 8 and a delay element 9, thus forming a one-shot multivibrator. The other input signal B is input to the OR gate 11 through a delay element (specifically, for example, a delay line) 10 and without passing through anything, and is input to the OR gate 11.
The output of 1 is input to flip-flop 12.
Like the flip-flop 7, this flip-flop 12 also forms a one-shot multivibrator together with an inverting circuit 13 and a delay element 14. Therefore, as shown in FIG. 3, when the input signal A is input, a pulse C of a constant width is generated from the non-inverting output terminal of the flip-flop 7 with a slight delay, and this pulse C is generated from the AND circuit forming the coincidence detection circuit.
It is input to gate 15. When the other input signal B is input, first a leading pulse is generated from the non-inverting output terminal of the flip-flop 12 based on the signal on the non-delayed side, and then a trailing pulse is generated based on the signal on the delayed side. (See Figure 3D).
The time widths of the leading pulse and the trailing pulse are strictly equal because they are generated by the same one-shot multivibrator.
Note that the reason for using the OR gate 6 on the input signal A side is that the OR gate 11 must be used on the input signal B side, so by inserting a similar OR gate 6 on the input signal A side, This is to align the delay times of both signal systems so that the delay times of pulse C and the preceding pulse match.

AND gate 15 produces an output when pulse C and any of the leading and trailing pulses of pulse D are input simultaneously, and this output produces output E from flip-flop 16 (see FIG. 3E). This output E is input to AND gate 17. A signal F obtained from the delay tap of the delay element 10 is input to the other input terminal of the AND gate 17. The delay tap is taken from a point where the amount of delay of signal F becomes equal to the timing of generation of signal E that occurs when the preceding pulse and pulse C occur simultaneously (see Figure 3 F). ing. The output of this AND gate 16 is sent to a flip-flop 18, and an output G is produced from the non-inverting output terminal of this flip-flop 18 (see FIG. 3G).

Therefore, when the pulse C and the preceding pulse occur at the same time, the signal E is generated at the point when these two pulses coincide in time, as shown in Figure 3A.
occurs, and since signal F is also generated at this time, signal G is generated (becomes "1"). The signal E at this time is an on-time side signal, and by counting this, an on-time side count value including true coincidence and random coincidence can be obtained. On the other hand, when the trailing pulse of pulse C and the subsequent pulse occur simultaneously, signal E is generated when these two pulses coincide in time, as shown in FIG. has already ended, no output is generated from the AND gate 17, and no signal G is generated (becomes "0"). By counting only the signal E when the signal G is in this state, the count value only on the off-time side, that is, the count value only on the random coincidence side, can be obtained.

Therefore, random coincidence can be corrected by subtracting the count value on the off-time side from the count value on the on-time side. In this case, since the pulse widths of the two pulses (the leading pulse and the trailing pulse) obtained from the flip-flop 12 are strictly equal as described above, the coincidence time window width is different between the on-time side and the off-time side. are completely consistent, and accurate random coincidence correction can be performed.

In this embodiment, an AND gate 15 and a flip-flop 16 are used as a coincidence detection circuit.
However, it is also possible to use various other gate elements.

(f) Effect According to the present invention, one coincidence detection circuit detects both on-time side simultaneity and off-time side simultaneity, and later detects the off-time side simultaneity detection output included therein. By adopting a configuration in which the discrimination is made using the other coincidence detection circuit, the same coincidence detection circuit is used for both the on-time side and the off-time side, so the coincidence time window width between the on-time side and the off-time side can be reduced. can be made strictly equal, so
Accurate random coincidence correction can be performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS.
FIG. 4 is a signal waveform diagram of each part for explaining the operation shown in the figure. 1, 4, 15, 17...AND gate, 2, 5,
7, 12, 16, 18...flip flop,
3, 9, 10, 14... delay element, 6, 11...
OR gate, 8, 13...inversion circuit.

Claims (1)

[Claims] 1 In a coincidence circuit that detects and counts the simultaneous input of first and second input signals, a leading pulse with no time delay relative to the first input signal and a trailing pulse with a predetermined time delay from the first input signal. 2 with pulse
a pulse generating circuit that generates two pulses, and a first input signal that receives two pulses of the first input signal generated from the pulse generating circuit together with a second input signal, and detects the simultaneity of these input signals. It is characterized by having a coincidence detection circuit, and a second coincidence detection circuit that receives the output of the first coincidence detection circuit and the trailing pulse of the first input signal, and detects the simultaneity of these input signals. A coincidence counting circuit.