JPS60144684A - Simultaneous counting circuit - Google Patents

Abstract

PURPOSE:To make an accurate random coincidence correction by making coincidence time window width accurately coincident between an on-time and an off- time side. CONSTITUTION:When an input signal A is inputted, a delay pulse with constant width appears at the non-inverted output terminal of an FF circuit 7 and is inputted to an AND gate 15 forming a coincidence detecting circuit. When an input signal B is inputted, a preceding pulse appears at the non-inverted output terminal of an FF circuit 12 and then a succeeding pulse is generated on the basis of a signal delayed by a delay element 10. The output of the AND circuit 15 is inputted to an FF circuit 16, whose output is inputted to an AND gate 17. The output of the AND gate 17 is inputted to an FF circuit 18. The output of an AND gate 16 is counted when the AND gate 17 generates no output to obtain the counted value of only the off-time side, and the output of the AND gate 16 is counted when the AND gate 17 generates the output to obtain the counted value of the on-time side.

Description

[Detailed description of the invention] (a) Industrial application field This invention is mainly used for positron ECT devices (emission computed tomography devices), or for performing coincidence counting in other fields such as radiation measurement. Used for, same +1! +=Relates to a counting circuit.

(b) As is well known, the prior art positron ECT device utilizes the fact that when a positron disappears, it emits two gamma rays in a 180° direction. By detecting two gamma rays, it is known that positron nuclides are present on the line connecting the two sets of detectors, and a counting profile is obtained. It is necessary to detect and count the simultaneous incidence of two (coincidence), and a coincidence circuit is used for this purpose.

By the way, separate gamma rays that are not caused by a single positron may incidentally hit two detectors at the same time (random coincidence), so it is necessary to remove such cases and count only the true coincidences. . As a method of correcting this random coincidence, a method of measuring delay coincidence is conventionally known.As shown in FIG. Simultaneous input of both is detected and an output is generated from the flip-flop 2, and one input signal A is delayed by a predetermined time (for example, about 50 nsec when the pulse width of the input signal is 10 nsec) using the delay element 3. The input signal B of is inputted to the AND gate 4 without delay,
The output of the AND gate 4 causes an output from the flip-flop 5. The counted output of flip-flop 2 is the true coincidence count plus the random coincidence count, whereas the counted value of the output of flip-flop 5 is considered to be only the random coincidence count. be able to. This is because it can be considered that for randomly generated signals, the probability that they will occur at the same time if delayed is the same as the probability that they will occur at the same time even if they are not delayed. Therefore, by subtracting the count value of the output of the flip-flop 5 from the count value of the output of the flip-flop 2, the random coincidence can be corrected. However, in this circuit, the waveform of input signal A becomes dull due to the delay element, its pulse width becomes narrower, and the coincidence time window width becomes different between the on-time side (AND gate 1 side) and the off-time side (AND gate 4 side). Therefore, there is a drawback that the random coincidence count value cannot be sufficiently corrected.

(C) Purpose This invention allows the coincidence time window widths of the on-time side and the off-time side to be exactly matched,
Thereby, it is an object of the present invention to provide a coincidence circuit that can perform more accurate random coincidence correction.

(d) Configuration This invention provides a coincidence circuit that detects and counts the simultaneous input of two input signals, in which one input signal is generated without any time delay relative to the other input signal. a pulse generation circuit that generates two pulses: a leading pulse and a trailing pulse that is generated a predetermined time later than the leading pulse; a coincidence detection circuit that receives the two pulses together with the other input signal; The invention is characterized in that it has a circuit for determining whether the output of the coincidence detection circuit is due to the simultaneous input of the preceding pulse and the other input signal or the simultaneous input of the following pulse and the other input signal.

(E) Embodiment In FIG. 2, one input signal A is input to a flip-flop 7 via an OR gate 6. The inverting output terminal of this flip-flop 7 is connected to a reset terminal via an inverting circuit 8 and a delay element 9, thus forming a one-shot multivibrator. The other input signal B is input to the OR gate 11 through a delay element (specifically, for example, a delay line) 1O and without passing through anything, and is input to the OR gate 11.
The output of is input to the flip-flop 12.

Like the flip-flop 7, this flip-flop 12 also forms a one-shot multivibrator together with the inverting circuit '13 and the delay element 14. Therefore,
As shown in FIG. 3, when the input signal A is input, a pulse C of a constant width is generated from the non-inverting output terminal of the flip-flop 7 with a slight delay, and this is input to the AND gate 15 forming a coincidence detection circuit. . When the other input signal B is input, a leading pulse is first generated from the non-inverting output terminal of the flip-flop 12 based on the signal on the non-delayed side, and then a trailing pulse is generated based on the signal on the delayed side. The time widths of the leading pulse and the trailing pulse that are generated (see the third diagram) are strictly equal because they are generated by the same one-shot multivibrator. Note that the reason why OR gate 6 is used on the input signal A side is that OR gate 11 must be used on the input signal B side, so by inserting a similar OR gate 6 on the input signal A side, both signals can be This is to align the delay times of the systems so that the delay times of the pulse C and the preceding pulse match.

AND gate 15 produces an output when pulse C and any of the leading and trailing pulses of pulse D are input simultaneously, and this output produces output E from flip-flop 16 (see FIG. 3E). This output E is AN
D game) is input to 17. The other input terminal of the AND gate 17 receives a signal F obtained from the delay tap of the delay element IO.
is entered. And that delay tap is the signal F
The delay Jit is taken from such a point that it becomes equal to the generation timing of the signal E that occurs when the preceding pulse and the pulse C occur simultaneously (see FIG. 3F). The output of this AND gate 16 is sent to a Noritsubu flop 18, and an output G is produced from the non-inverting output terminal of this flip-flop 18 (see FIG. 3G).

Therefore, when the pulse C and the preceding pulse occur simultaneously, as shown in FIG. 3(a), the signal E is generated at the point when these two pulses coincide in time, and the signal F is also generated at this time. Therefore, signal G is generated (
It becomes "l"). The signal E at this time is an on-time side signal, and by counting this, an on-time side count value including true coincidence and random coincidence can be obtained. On the other hand, when pulse C and the trailing pulse occur simultaneously, signal E is generated when these two pulses coincide in time, as shown in Figure 3 (b). Signal F has already ended, and no output is produced from AND gate 17, and signal G is also not produced (becomes "O"). Signal G
If only the signal E when is in this state is counted, the count value only on the off-time side, that is, the count value only on the random coincidence side, can be obtained.

Therefore, random coincidence can be corrected by subtracting the count value on the off-time side from the count value on the on-time side. In this case, since the pulse widths of the two pulses (leading pulse and trailing pulse) obtained from the flip-flop 12 are strictly equal as described above, the coincidence time window is The widths are completely matched, and accurate random coincidence correction can be performed.

In this embodiment, A is used as the coincidence detection circuit.
Although the ND gate 15 and the flip-flop 16 are used, various other gate elements may be used.

(f) Effects According to the present invention, since the coincidence time window widths on the on-time side and the off-time side can be made strictly equal, accurate random coincidence correction can be performed.

[Brief Description of the Drawings] Fig. 1 is a block diagram of a conventional example, Fig. 2 is a block diagram of an embodiment of the present invention, and Figs. 3 (a) and (b) explain the operation of Fig. 2. FIG. l, 4.15.17...AND gate 2.5.7.1
2.18.18...Flip-flop 3.9.10.
14... Delay element 6.11... OR gate 8.13... Inverting circuit 3

Claims (1)

[Claims] (1) In a coincidence circuit that detects and counts when two human input signals are input at the same time, a leading pulse with no relative time delay and a trailing pulse with a predetermined time delay from one input signal are used. A pulse generation circuit that generates two pulses, a coincidence detection circuit to which the two pulses are input together with the other input signal, and an output of the coincidence detection circuit that is generated by simultaneous input of the preceding pulse and the other input signal. 1. A coincidence counting circuit comprising: a circuit for determining whether a trailing pulse is caused by simultaneous input of a trailing pulse and the other human input signal.