JPH0556700B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A plurality of clock signals are periodically scanned, and based on the scan results, the data stored in the area corresponding to each clock signal of the first storage means is transferred to the second storage means. The data stored in the same clock signal corresponding area of the storage means and the data stored in the respective clock signal corresponding areas of the first and second storage means are periodically compared, and if they match, the corresponding clock signal is determined to be normal. The data stored in the first storage means is changed, and if the two data do not match, it is determined that the corresponding clock signal has been interrupted.

[Industrial application field]

The present invention relates to an improved clock break detection scheme that allows the detection of breaks in multiple clock signals.

In a multiplex transmitting/receiving circuit that transmits and receives a plurality of digital signals, it is not rare that a clock signal is also received in parallel with each digital signal.

It is strongly desired to realize a clock disconnection detection method that economically detects whether or not such a plurality of clock signals have arrived normally.

[Conventional technology]

FIG. 5 is a diagram showing an example of a conventional clock disconnection detection method, and FIG. 6 is a diagram showing an example of various signals in FIG.

In FIGS. 5 and 6, a plurality of clock signals ck1-ckn are received by monostable multivibrators (MV) 11-1n, respectively.

When a clock signal cki (i is a clock number from 1 to n) arrives after time t1, the monostable multivibrator 1i is activated at each rising edge of the clock signal cki and outputs a clock disconnection detection signal dti to logic "1". The clock interruption detection signal dti is reset to logic "0" after the holding time T2 has elapsed.

Retention time of each monostable multivibrator 1i
The period of the clock signal cki received by T2
Assuming that it is set longer than T1, until time t2 when the clock signal cki arrives normally,
Since the monostable multivibrator 1i is activated again before the holding time T2 has elapsed, the clock interruption detection signal dti continues to be set to logic "1".

In this state, the clock signal cki is output after time t2.
When no longer arrives, the monostable multivibrator 1i returns the clock disconnection detection signal dti to logic "0" at time t3 when the holding time T2 has elapsed.

As a result of the above, each monostable multivibrator 1i
indicates a break in the arriving clock signal cki by changing the clock break detection signal dti from a logic "1" to a logic "0".

[Problem that the invention seeks to solve]

As is clear from the above explanation, in the conventional clock disconnection detection method, multiple clock signals are detected.
Monostable multivibrator 1i installed for each clock signal cki detects the interruption of each clock signal cki. Therefore, as the number of clock signals increases, the number of installed monostable multivibrator 1i increases, and There was a risk that the economy would be damaged.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, ck is the clock signal to which the present invention is applied.

100 is a scanning means provided according to the present invention.

200 is a first storage means provided according to the present invention.

300 is a second storage means provided according to the present invention.

400 is a transfer means provided according to the present invention.

Reference numeral 500 denotes clock break detection means provided according to the present invention.

[Effect]

The scanning means 100 periodically scans a plurality of clock signals ck and transmits the scanning results to the transfer means 400.

The transfer means 400 detects the presence or absence of each clock signal ck based on the scanning result output from the scanning means 100, and when the clock signal ck is detected,
The data d stored in the first storage means 200 in correspondence with each clock signal ck is stored in the second storage means 300 in correspondence with the clock signal ck.

The clock break detection means 500 detects the data d stored in the area corresponding to each clock signal ck of the first storage means 200 and the data d' stored in the area corresponding to the same clock signal ck of the second storage means 300. are compared every predetermined period, and both data d and
If d' match, it is determined that the relevant clock signal ck is normal, and data d different from the data d stored up to that point is stored in the area corresponding to the relevant clock signal ck of the first storage means 200. If the data d and d' do not match, it is determined that the corresponding clock signal ck is interrupted.

Therefore, there is no need to provide means for detecting clock signal disconnection corresponding to each clock signal, and the economical efficiency of the clock disconnection detection method is improved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a clock disconnection detection method according to an embodiment of the present invention, FIG. 3 is a diagram illustrating input/output signals of the selector in FIG. 2, and FIG.
This figure is a diagram illustrating the clock break detection process in FIG. 2. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, a multiplex circuit (MPX) 3 is provided as a scanning means 100, a control memory (CM) 5 is provided as a first storage means 200, and a status memory (SM) 7 is provided as a second storage means 300. Selector (SEL) 6
is provided as a transfer means 400, and a processing device (PR) 8 is provided as a clock disconnection detection means 500.

In Figures 2 to 4, each clock signal
cki is received by each clock detection circuit (CD) 2i.

The clock detection circuit 2i receives each clock signal cki.
Detects each rising edge of and outputs a clock detection signal si.

The multiplex circuit 3 scans each clock detection signal si at a predetermined period using a clock number i transmitted from a counting circuit (CNT) 4 which advances at a predetermined period.
The scan result is input to the selector 6.

On the other hand, the control memory 5 and the status memory 7 each have an area corresponding to the clock number i, and each area of the control memory 5 is provided with a logic "0" or "1" from the processing device 8 in accordance with the procedure described later. The set write data di is stored in each area of the stator memory 7, and the control memory 5 is stored in each area of the stator memory 7 according to the procedure described later.
Write data di from or status memory 7
Read data di' from is stored.

In addition, each time the clock number i transmitted from the counting circuit 4 increments, the control memory 5 and the status memory 7 store the write data di and read data stored in the area corresponding to each clock number i.
di' are extracted and input to the selector 6.

The selector 6 detects that the clock detection signal si input from the multiplex circuit 3 is logic "1", that is, the lock signal cki.
is detected, control memory 5
Select the write data di input from and store it in the area corresponding to the clock number i of the status memory 7,
Further, when the clock detection signal s is at logic "0", that is, when the clock signal cki is not detected, the read data di' inputted from the status memory 7 is selected and stored in the original area of the status memory 7.

In FIG. 3, write data stored in an area corresponding to clock number i of control memory 5
di is set to logic “1” and status memory 7
Assuming that the read data di' stored in the area corresponding to the same clock number i is set to logic "0", if the clock number i=p, the clock detection circuit 2i detects the clock signal cki. , since the clock detection signal si of logic "1" is input to the selector 6, the selector 6 transfers the write data di (="1") input from the control memory 5 to the area corresponding to the clock number i of the status memory 7. is stored as new read data di'. That is, both the write data di and the read data di' are logic "1".
becomes.

On the other hand, when clock number i=q, the clock detection circuit 2i cannot detect the clock signal cki,
Since the clock detection signal si of logic “0” is input to the selector 6, the selector 6 stores the read data di′ (=“0”) input from the status memory 7 in the same area of the status memory 7 again. . That is, the write data di and the read data di' have opposite logical values.

Furthermore, the processing device 8 periodically extracts the write data di stored in the area corresponding to the clock number i of the control memory 5 at intervals longer than the period of the clock signal cki (step S1 in FIG. The read data di' stored in the area corresponding to the same clock number i in the memory 7 is extracted (step S2), the write data di and the read data di' are compared (step S3), and if they match, It is determined that the clock signal cki has arrived normally, and the clock signal cki is stored in the area corresponding to the corresponding clock number i in the control memory 5.
The logical value of the write data di that has been stored up to the end is inverted and stored (step S4).

If the write data di and the read data di' do not match in step S3, the processing device 8 determines that the clock signal ck has been interrupted (step S5).

As is clear from the above description, according to this embodiment, only the clock detection circuit 2i, the storage areas in the control memory 5 and the status memory 7 are provided corresponding to each clock signal cki, and the multiplex circuit 3, the counter The circuit 4, selector 6 and processing device 8 are all provided in common for each clock signal cki. Note that the clock detection circuit 2i, multiplex circuit 3, and counting circuit 4 are used for purposes other than clock loss detection, and the control memory 5 and status memory 7 are used for purposes other than the present invention, so they are used exclusively for clock loss detection. There is very little equipment.

〔Effect of the invention〕

As described above, according to the present invention, there is no need to provide a means for detecting a clock signal disconnection corresponding to each clock signal, and the economical efficiency of the clock disconnection detection method is improved.

[Brief explanation of drawings]

1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram illustrating a clock disconnection detection method according to an embodiment of the present invention, FIG. 3 is a diagram illustrating input/output signals of the selector in FIG. 4 is a diagram illustrating the clock disconnection detection process in FIG. 2, FIG. 5 is a diagram illustrating an example of a conventional clock disconnection detection method, and FIG. 6 is a diagram illustrating an example of various signals in FIG. be. In the figure, 11 to 1n are monostable multivibrators (MV), 21 to 2n are clock detection circuits (CD), 3 is a multiplex circuit (MPX), 4 is a counting circuit (CNT), 5 is a control memory (CM),
6 is a selector (SEL), 7 is a status memory (SM), 8 is a processing device (PR), 100 is a scanning means, 200 is a first storage means, 300 is a second storage means, 400 is a transfer means, 500 indicates a clock break detection means.

Claims (1)

[Scope of Claims] 1. Scanning means 100 for periodically scanning a plurality of clock signals ck; and detecting the presence or absence of each of the clock signals ck based on the scanning results output from the scanning means 100;
When the clock signal ck is detected, the data d stored in the area corresponding to each clock signal ck in the first storage means 200 is transferred to the second storage means 3.
The transfer means 400 stores the same clock signal ck corresponding area of 00, the data d stored in the respective clock signal ck corresponding areas of the first storage means 200, and the same clock signal of the second storage means 300. signal ck
The data d' stored in the corresponding area is compared at predetermined intervals, and if both data (d and d') match, the corresponding clock signal ck is determined to be normal and the first storage means 200 applicable clock signals
Stores data d different from the data d stored up to then in the ck corresponding area, and stores both data (d
and d′), the corresponding clock signal
1. A clock interruption detection method comprising a clock interruption detection means 500 for determining that ck is interrupted.