JPH0556360A - Preamplifier for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a picture quality due to the asymmetry of signal edges, at the time of the rising and falling of a video signal. CONSTITUTION:In an image pickup device using the solid-state image pickup element, a preamplifier using a correlation duplex sampling method is used for removing a reset noise being a defect at the time of detecting a charge by a floating diffusion amplifier. The time constants of the charge and discharge of capacitors 24 and 31 of a clamp circuit and a sample-and-hold circuit are different, and then the signal edge at the time of the rising and falling of the video signal are asymmetrical, and as the result the picture signal deteriorates. Thus, a signal supply to the capacitors 24 and 31 is operated by using constant current circuits 45 and 50, so that the time constants of the charge and discharge of the capacitors 24 and 31 can be equal. Thus, the signal edges at the time of the rising and falling of the video signal can be symmetrical.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a preamplifier for an image pickup device using a solid-state image pickup device.

[0002]

2. Description of the Related Art Today, solid-state image pickup devices are widely used, and the operating principle of the solid-state image pickup device is well known, but since it is deeply related to the present invention, its outline will be briefly described below.

That is, a CCD type solid-state image pickup device (hereinafter C
(CD) comprises m and n photodiodes in the row and column directions and m columns of vertical transfer registers and horizontal transfer registers composed of CCDs, and a charge detector. The photodiode photoelectrically converts incident light from a subject and accumulates signal charges obtained by photoelectric conversion. The signal charges are read into the vertical transfer register via the signal reading gate, and then sequentially transferred in the horizontal transfer register direction by the vertical transfer pulse, and transferred to the horizontal transfer register for each horizontal line.

The signal charges transferred to the horizontal transfer register are sequentially transferred to the charge detection unit by the horizontal transfer pulse supplied from the horizontal transfer pulse supply terminal, converted into a voltage signal by the floating diffusion of the charge detection unit, and output as a signal. The signals are sequentially obtained from the terminals.

FIG. 3 shows a cross-sectional view of the horizontal transfer register and the charge detecting portion, and the operation of the charge detecting portion will be briefly described below. In FIG. 3, horizontal transfer pulses Φ _{H1 to} Φ _H4 are supplied to the supply terminals 5 connected to the horizontal transfer gates 1, 2, 3, and 4 which form the horizontal transfer register. The floating diffusion amplifier (hereinafter referred to as FDA) as the charge detection unit 6 includes a floating diffusion 7, a reset drain 8 connected to the power supply V1, an output gate electrode 9 connected to the Φ _G terminal, and a reset pulse Φ. it is an _R supply terminal of Φ _R terminal
It comprises a reset electrode 11 connected to 10, a FET 12 having a base connected to the floating diffusion 7 and a drain connected to the power supply V2, and a source resistor 13 connected to the source of the FET 12. Further, the floating diffusion (hereinafter referred to as FD) 7 is a stray diffusion that is not directly connected to the DC power source, and the output terminal 14 is connected to the connection point between the source of the FET 12 and the source resistance 13. Reference numeral 15 is a P-type substrate, and an insulating oxide film SiO ₂ 16 is provided on the P-type substrate 15.

FIG. 4 shows a simplified configuration of FIG. 3 by simplifying it, and FIG. 5 shows each pulse applied to the electrodes Φ _{H1 to} Φ _H4 and Φ _R terminal 10. And
FIG. 4 shows a potential model at each time t _{1 to} t ₅ in FIG.

First, time t _{1 in} FIG. 4 is in a state immediately before horizontal transfer is performed, that is, a state immediately after the signal charges are transferred from the vertical transfer register to the horizontal transfer register.
Electrodes [Phi _H1 In this time t _1, the voltage [Phi _H2 is applied, the electrodes [Phi _H1, [Phi _H2 potential under goes high, the signal charges transferred from the vertical transfer registers to the horizontal transfer register electrodes [Phi _H1, Trapped under Φ _H2 . In FIG. 4, Q ₁ ,
Q ₂ is the signal charge. At this time, the charge of the FD 7 is Φ _R pulse A which is the reset pulse Φ _R shown in FIG.
The state when applied to the _R terminal 10 is maintained. That is, when the Φ _R pulse A is applied to the Φ _R terminal 10, the potential of the FD 7 becomes about V ₁ , and unless the FD 7 is charged, V ₁
To maintain. Here, the reason why the Φ _R pulse A is applied even during the horizontal retrace period during which no signal charge is injected into the FD7 is to prevent the charge in the FD7 from varying due to a dark current.

Next, t ₂ in FIG. 4 is the signal charge (Q ₁ , Q
₂ ) has been transferred in the direction of the charge detection unit 6 by one electrode of the CCD, and the potential of the FD 7 maintains V ₁ . Further, at t ₃ in FIG. 4, the signal charge (Q ₁ , Q ₂ ) is further transferred by one electrode toward the charge detection unit 6, and the Φ _R terminal
Since Φ _R pulse A is applied to 10, the potential of FD7 is V ₁
Becomes

Further, at t ₄ in FIG. 4, the signal charges (Q ₁ , Q ₂ ) are further transferred by one electrode in the direction of the charge detection unit 6, so that part of the signal charge Q ₁ is transferred to the electrode Φ _H4. It is captured below and the rest is transferred to FD7, and the potential of FD7 drops according to the amount of signal charge.

Further, at t ₅ in FIG. 4, since the signal charges (Q ₁ , Q ₂ ) are transferred by the amount of another electrode toward the charge detecting portion 6, the signal charges Q trapped under the electrode Φ _H4. The rest of ₁ is also transferred to FD7. Therefore, FD
The potential of 7 further decreases to the potential of V _P. The potential V _P of the FD 7 is held until the Φ _R pulse is applied to the Φ _R terminal 10.

In FIG. 6, an FDA is used as the charge detection unit 6.
The outline of the video output from the solid-state image sensor is shown.
It is a schematic diagram of a video output B from the element. In addition, A is shown in FIG.
Φ _RIt is a pulse. 6, the output terminal 14 of FIG.
To reset period a, zero level period b, and signal period
The video output B that changes with c is output. This signal period c
The signal voltage from FD7 appears at the waveform shown by the solid line B1.
Is the signal waveform when the signal charge is injected into the FD7.
The waveform shown by line B2 shows whether the signal charge is injected into FD7.
It is the signal waveform when

In order to convert the signal charge from the photodiode into a voltage from the charge detection unit 6 and extract it as a signal voltage, the voltage of the FD 7 must be reset to V ₁ each time the signal charge for one pixel is extracted. When the FD 7 is reset, a low cycle noise (hereinafter this noise is referred to as reset noise) is generated due to the interface state below the reset gate electrode 11. That is, the reset potential of the FD 7 changes depending on the interface state. This reset noise is held by the capacity of FD7 until FD7 is next reset. That is, the reset noise is sampled and held and is output from the output terminal 14 of FIG.

Therefore, the zero level period b shown in FIG.
Further, during the signal period c, the video output B fluctuates due to reset noise. Therefore, when the signal processing is performed as it is to form the video signal, the signal is mixed with reset noise.

This reset noise has an electric power of frequency f.
1 / f noise that is inversely proportional to. Since the frequency of the 1 / f noise in the charge detection unit 6 is 1/10 or less of the output signal frequency, the fluctuation of the 1 / f noise is small over several bits of the output signal and can be regarded as almost constant. Then, the 1 / f noise appears as a horizontal band on the TV screen at random, and the image quality is significantly impaired.

As described above, the correlated double sampling method is generally used as a method for removing the reset noise while paying attention to the characteristic of the 1 / f noise. A schematic of a preamplifier using this practical correlated double sampling method (hereinafter referred to as CDS method) is shown in FIG. In FIG. 7, D1
Is a clamp circuit section, and D2 is a sampling circuit section in the subsequent stage. The clamp circuit portion D1 has an input terminal 21 connected to an output terminal 14 to which a signal from the FD 7 is input,
A transistor 22 that receives this input signal, its bias resistor 23, a capacitor 24 for clamping, a switch 25 controlled by a clamp pulse, a power supply 26 that supplies a reference voltage V _S of the clamp, and a termination transistor 27 of the clamp circuit section D1.
It consists of Also, the sampling circuit section D2
Is a transistor 28 connected to the emitter of the terminating transistor 27 of the clamp circuit section D1, its bias resistor 29,
It is composed of a switch 30 controlled by a sampling pulse, a capacitor 31 for holding a sampled signal, and a termination transistor 32 of a sampling circuit section D2.
Further, the signal output terminal 33 of the preamplifier by the CDS method is connected to the emitter of the termination transistor 32.

With the above configuration, the operation of the CDS method will be described below. As shown in FIG. 8, E1 is a signal waveform input to the input terminal 21, E2 is a clamp pulse waveform controlling the switch 25, and E3 is an output signal waveform of the clamp circuit section D1, that is, the base of the transistor 28. Signal waveform, E4 is a sampling pulse waveform for controlling the switch 30, E5 is an output signal waveform of the sampling circuit section D2,
That is, it is a signal waveform output from the output terminal 33. The input waveform E1 changes from the output terminal 14 of FIG. 3 in the reset period a, the zero level period b, and the signal period c.
A signal similar to the video output B of is output, but the input waveform E
In the case of 1, the levels in the periods a, b, and c change due to the influence of reset noise as shown in d1 and d2.
Further, the switch 25 is in the ON state when the clamp pulse E2 is the voltage V _H , and is in the OFF state when the clamp pulse E2 is the voltage V _L ,
In addition, the switch 30 detects that the sampling pulse E4 has the voltage V _H.
Is on, and is off when the voltage is V _L. The clamp pulse E2 has the voltage V _H during the zero level period b of the input waveform E1, and the sampling pulse E4 has the voltage V _H during the signal period c of the input waveform E1.

First, the clamp pulse E2 is the input waveform E1.
When the voltage becomes V _H during the zero level period b of
Is turned on and the power supply 26 is connected to the connection point p1 between the capacitor 24 and the base of the transistor 27, and the reference voltage V _S is applied to this connection point p1. As a result, the potential of this connection point p1 becomes the reference potential V _S. After the switch 25 is turned off, only the change in the potential at the collector end of the transistor 22, that is, the change in the signal input to the input terminal 21 is transmitted via the capacitor 24, and the potential at the connection point p1 becomes the reference potential. V
_It changes from _S. Thus, the video output B is clamped to the reference potential V _S during the zero level period b. That is, the waveform E3 shown in FIG. 8 is obtained, and the reset noise described above is removed.

Next, when the sampling pulse E4 becomes the voltage V _H during the signal period c of the input waveform E1, the switch 30
Is turned on, and the connection point between the resistor 29 and the collector of the transistor 28 becomes the connection point p2 between the capacitor 31 and the base of the transistor 32.
, And the potential of this connection point p2 becomes the same potential as the collector terminal of the transistor 28. After that, even if the switch 30 is turned off, the potential is held by the capacitor 31 until the switch 30 is turned on next time. As a result, the signal voltage from the solid-state image sensor in the signal period c is sampled. That is, only the sampling signal having the waveform E5 in FIG. 8 can be taken out from the output terminal 33.

[0019]

In the above-mentioned conventional CDS method, since the capacitors 24 and 31 are operated by charging and discharging, the charging time and discharging time of the capacitors 24 and 31 directly affect the performance. In the CDS method shown in FIG. 7, the electric charges from the capacitors 24 and 31 are discharged through the transistors 22 and 28, respectively, but the charging is performed from the voltage source through the resistors 23 and 29, respectively, so that charging and discharging are performed. At, a difference occurs in the time constant, and the charging time constant becomes longer than the discharging time constant. That is, in the preamplifier using the CDS method of FIG.
Taking the sampling circuit section D2 as an example, when the video signal becomes a black level (the signal input to the input terminal 21 is at a high level), the potential at the connection point p2 rises and the capacitor 31 is charged. When the video signal reaches the white level (the signal input to the input terminal 21 is at the low level), the potential at the connection point p2 drops and the charge of the capacitor 31 is discharged. At this time,
Since the charging time is longer than the discharging time as described above, the edge from the white level to the black level becomes dull with respect to the edge from the black level to the white level. That is, in the CDS method of FIG. 7, the edges are not symmetrical at the rising and falling edges of the signal. For this reason, there is a problem in that the image is deteriorated such as blurring or false shadows at the edge where the image changes greatly.

The present invention is to solve the above-mentioned conventional problems, and the edges are not symmetrical at the rising and falling edges of the video signal caused by the charging speed being slower than the discharging speed of the sample and hold in the correlated double sampling method. It is an object of the present invention to provide a preamplifier for a solid-state image sensor, which can prevent deterioration of image quality due to the above.

[0021]

In order to solve the above problems, a preamplifier for a solid-state image sensor according to the present invention is a clamp for clamping a reference voltage and a signal voltage from the solid-state image sensor. A preamplification device for a solid-state image pickup device using a correlated double sampling method having a circuit and a sample hold circuit for sampling the signal voltage output from the clamp circuit, wherein a response speed of a clamp in the clamp circuit, And a constant current source for supplying a signal to the clamp circuit and the sample and hold circuit so that the response speed of the sample and hold in the sample and hold circuit becomes equal at the rising edge and the falling edge of the signal edge.

[0022]

With the above structure, the constant current source for equalizing the response speed of the clamp and the response speed of the sample hold at the rising edge and the falling edge of the signal edge is used for the signal supply to the clamp circuit and the sample hold circuit. The response speed of the video signal output of the solid-state image sensor from the white level to the black level at which the image changes greatly compared to the signal supply by the voltage source via the, thereby increasing the response speed from the black level to the white level. It becomes possible to equalize the response speed from the white level to the black level, and a video signal having symmetrical signal edges can be obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. The same effects as those of the conventional example are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 1 is a circuit diagram showing the configuration of a preamplifier for a solid-state image pickup device according to an embodiment of the present invention. In FIG. 1, the power supply V _CC is grounded via a resistor 41 and a resistor 42. The connection point of the resistors 41 and 42 is connected to the base of the transistor 43, the collector thereof is connected to the power supply V _CC through the resistor 44, and the emitter thereof is the transistor.
It is connected to the connection point between the collector of 22 and the capacitor 24. With the above, a constant current circuit 45 that can supply a signal to the clamp circuit is configured.
Charge 24. Similarly, the power supply V _CC is grounded via the resistor 46 and the resistor 47. The connection point of these resistors 46 and 47 is connected to the base of the transistor 48, the collector thereof is connected to the power source V _CC via the resistor 49, and the emitter thereof is connected to the collector of the transistor 28 and the switch 30. It is connected. As described above, the constant current circuit 50 capable of supplying a signal to the sampling circuit is configured, and the constant current circuit 50 allows the capacitor 31 to be connected via the switch 30.
To charge. Therefore, the preamplifier 51 of the correlated double sampling method using the constant current circuits 45 and 50 by the transistors 43 and 48 for supplying signals by the constant current source is realized.

With the above configuration, the operation will be described below. First, in the clamp circuit portion, the switch 25 is turned on during the zero level period of the input signal, the power supply 26 is connected to the connection point p1 of the base of the capacitor 24 and the transistor 27, and the reference voltage V _S is applied to this connection point p1. As a result, the potential of this connection point p1 becomes the reference potential V _S. And switch
After 25 is turned off, the
The change in the potential at the collector end of 22, that is, the input terminal 21
The potential of the connection point p1 changes from the reference potential V _S by transmitting only the change of the signal input to. In this way, the signal clamped to the reference voltage V _S is obtained in the zero level period.

Next, in the sampling circuit section, the switch 30 is turned on during the signal period of the input signal so that the connection point between the emitter of the transistor 48 and the collector of the transistor 28 is connected to the connection point p2 of the base of the capacitor 31 and the transistor 32. , A signal is sent only when the switch 30 is on. Then, the signal passed through the switch 30 becomes the capacitor 31.
, And the signal is held until switch 30 is next turned on. This allows the switch 30 only during the signal period.
The signal passed through is sampled.

That is, the gist of the present invention is that the capacitor 24,
It is to make the time constants of charging and discharging 31 equal. The operation will be described in detail below by taking the sampling circuit unit as an example. First, when the signal input to the transistor 28, that is, the input signal voltage to the sampling circuit unit changes from high to low, the capacitor 31 is charged via the constant voltage source 50. When the signal voltage of the input signal to the sampling circuit section changes from low to high, the capacitor 31
The electric charge that has been charged to is discharged through the transistor 28. At this time, in the constant current circuit 50, which is a constant current source, a constant voltage I _S flows from the collector of the transistor 48 to the emitter because the predetermined voltage determined by the resistors 46 and 47 is always applied to the base of the transistor 48. Become. When the current flowing through the transistor 28 when the input signal voltage is maximum is I _H and the current flowing through the transistor 28 when the input signal voltage is minimum is I _L , the current I _H and the current I _L are averaged. When I _S is defined, the current for charging the capacitor 31 when the input signal voltage becomes the maximum to the minimum and the current discharged from the capacitor 31 when the input signal voltage becomes the minimum to the maximum are both the current I _S. And the time constant becomes the same. That is, the rising and falling edges are symmetrical.

Similarly, the clamp circuit section
The average current I _S that can flow from the collector of the transistor 43 to the emitter of the transistor 43 can be set in the same manner as in the sampling circuit section so that the current flowing when the capacitor 24 is charged and the current flowing when the capacitor 24 is discharged are equal. This makes the rising and falling edges symmetrical.

Further, a signal waveform when an actual subject is imaged will be described with reference to FIG. In FIG. 2, 52 is
The signal schematic diagram in the broken line part XY when the image | video 53 was image | photographed is shown. 54 shows a schematic diagram of the output signal when the preamplifier of the conventional CDS method in FIG. 7 is used.
In this case, the falling edge 54a and the rising edge 54
b is asymmetric. 55 is a signal when detail (high-frequency emphasis) is applied to the signal 54 in the signal schematic diagram. 56
Shows a schematic diagram of an output signal when the preamplifier of the CDS method of this embodiment in FIG. 1 is used. in this case,
The falling edge 56a and the rising edge 56b are symmetrical. 57 is a signal when detail is applied to the signal 56 of the signal schematic diagram. As described above, the edges 54a and 54b in the conventional CDS method shown in FIG. 7 are asymmetrical, whereas the CDS method of the present embodiment shown in FIG. Is obtained.

Therefore, by using a constant current source for the signal supply to the clamp circuit section and the sample hold circuit, the white level of the video signal output of the solid-state image pickup device can be reduced as compared with the conventional signal supply by the voltage source via the resistor. By increasing the response speed to the black level, the response speed from the black level to the white level and the response speed from the white level to the black level are made equal, that is, the charge time and the discharge time of the clamp and sample hold are made equal. It is possible to obtain a video output with symmetrical edges. This allows you to
The problem of blurring and false shadows at the edges where the image changes drastically is resolved, resulting in a high quality image.

[0031]

As described above, according to the present invention, by using a constant current source for the signal supply to the clamp circuit and the sample hold circuit, compared with the conventional signal supply by the voltage source via the resistor, the solid-state imaging By increasing the response speed from the white level to the black level of the image signal output of the device, the response speed from the black level to the white level is made equal to the response speed from the white level to the black level, that is, the charging time of the sample hold and The discharge time can be made equal, and an image with symmetrical edges can be obtained, resulting in a high quality image.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a preamplifier for a solid-state image sensor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a difference between a conventional example and a present example regarding a signal waveform when an actual subject is imaged.

FIG. 3 is a cross-sectional view of a horizontal transfer stage and a charge detection unit of a conventional CCD type image pickup device.

FIG. 4 is a diagram showing a simplified version of FIG. 3 and a potential model at each time.

5 is a diagram showing a relationship between a horizontal transfer pulse and a reset pulse and respective times shown in FIG.

6 is a diagram showing an output signal and a reset pulse from the FDA of FIG.

FIG. 7 is a circuit diagram showing a configuration of a preamplifier for a solid-state image pickup device using a conventional correlated double sampling method.

FIG. 8 is a waveform diagram of each main part in FIG.

[Explanation of symbols]

 22, 27, 28, 32, 43, 48 Transistor 25, 30 Switch 24, 31 Capacitor 41, 42, 44, 46, 47, 59 Resistor 45, 50 Constant current circuit 51 Preamplifier

Claims (1)

[Claims] 1. A clamp circuit for inputting a reference voltage and a signal voltage from a solid-state image sensor to clamp the reference voltage to a predetermined voltage, and a sample hold circuit for sampling the signal voltage output from the clamp circuit. A preamplifier for a solid-state imaging device using a correlated double sampling method, wherein a response speed of a clamp in the clamp circuit and a response speed of a sample hold in a sample hold circuit are made equal at a rising edge and a falling edge of a signal edge. A preamplifier for a solid-state image sensor, which includes a constant current source for supplying a signal to the clamp circuit and the sample hold circuit as described above.