JPH0555934A - Code transmitter and method - Google Patents

Abstract

PURPOSE:To simplify the address generation procedure by decreasing a memory access frequency for generating an external code and an internal code in the code transmitter in which an error check correction code comprising a product code is added to a code and the resulting code is sent. CONSTITUTION:An external code coding circuit 18 generates a check point of an external code of an information data from a memory 14 and writes it to a memory 22, and simultaneously, an internal code coding circuit 20 generates a check point of an internal code of an information data from which the check point of the external code is eliminated and stores in the memory 24. An inner code coding circuit 26 reads the storage data in the memories 22, 24 to generate a check point of the inner code in which the external code check point is added. A selection circuit 28 outputs the information data, the check point of the external code and the check point of the internal code according to a prescribed sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error code transmission apparatus and method, and more particularly to a code transmission apparatus and method for adding an error detection / correction code by a product code and sending it to a transmission line or the like.

[0002]

2. Description of the Related Art In digital data transmission, for example, digital recording of a magnetic recording medium, a magnetic recording medium (transmission path)
It is necessary to suppress the low-frequency component of the digital code recorded (transmitted) in. When there is a correlation between data such as image data, the low frequency component of the code sequence can be suppressed in the information data portion by using mapping coding that utilizes the correlation. However, the error detection and correction code has no correlation, and thus it is difficult to suppress the low frequency component.

For this, the following methods have been proposed. That is, in the data matrix shown in FIG.
An information code (data) for generating an outer code is diagonally scanned as indicated by an arrow in FIG. 2 to generate an outer code check point. At this time, the outer code check points can be dispersed in the two-dimensional array on the memory as shown in FIG. 3 by performing the basic row operation of the matrix on the check matrix that generates the check points. However, in FIG. 3, each outer code is obliquely configured. In this way, by scanning the data matrix to which the outer code is added in the horizontal direction (for each row) and sending it to the next stage, the outer code check points are dispersed on the time axis.

Next, the same operation is performed for the inner code. At this time, the inner code check points are dispersedly arranged in the code of each row of FIG. 3 so as not to be continuous with the previously generated outer code check points. FIG. 4 shows the two-dimensional arrangement of generated codewords.
In FIG. 4, by scanning in the horizontal (row) direction and sending out to the transmission path, both the outer code check point and the inner code check point are
Disperse on the time axis. In this way, the low frequency components generated by the error detection and correction code can be reduced.

[0005]

However, in the above method, in order to encode the outer code and the inner code, the information code stored in the memory is scanned / extracted (read), and the extracted information code and the generated information code are generated. There is a problem that the writing of the outer code to the memory must be sequentially performed over the entire data matrix, and a memory having a high access rate must be used. In addition, there is a problem that the memory address generation procedure becomes complicated.

An object of the present invention is to provide a code transmission device and method which solves the above problems.

[0007]

A code transmission device according to the present invention is a code transmission device for performing code transmission by adding an error detection or correction code by a product code, and a check point of an outer code from information data. Outer code encoding / storing means for generating and storing, inner code encoding / storing means for generating and storing inner code check points from only information data, and outer code encoding / storing means And inner code coding means for completing the inner code check points stored in the inner code coding / storing means with reference to the code check points.

A code transmitting method according to the present invention refers to a first step of generating outer code check points and some inner code check points from information data, and an outer code check point in the first step, A second step of completing the inner code check point partially generated by the first step, and a step of adding a synchronization code to the information data, the outer code check point and the inner code check point, and outputting in a predetermined format. It is characterized by comprising three steps.

[0009]

By the above means, a part of the inner code is generated while the outer code is generated by reading the information data once, so that the number of memory accesses can be reduced and the processing speed can be increased. Moreover, since the read address may be simply changed, the address generating procedure is simplified.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Reference numeral 10 is an input terminal of information to be recorded (for example, an image signal), and the mapping encoding circuit 12 suppresses the information input to the input terminal 10 in the low frequency band by utilizing the correlation. The data low-pass suppressed by the circuit 12 is written on the memory 14 so as to form a data matrix. The data matrix stored in the memory 14 is sequentially read out in the horizontal (row) direction of FIG.

FIG. 6 shows the relationship between the data matrix on the memory 14 and the check points of the outer code and the inner code. Although the synchronous data does not exist in the memory 14, it is shown in order to clearly indicate the transmission direction. 40 is a data matrix stored in the memory 14, 42 is an outer code check point, and 44 is an inner code check point.

The outer code encoding circuit 18 has an arrow 46 in FIG.
The output of the memory 14 is fetched so that the data matrix 40 is obliquely scanned as shown by, and the check points of the outer code are generated and written in the memory 22. A concrete circuit example of the outer code encoding circuit 18 is shown in FIG. 50 is an input terminal, 52 is a Galois field multiplier, 54 is a Galois field adder, and 56 is an adder 5.
The delay circuit 58 delays the output of 4 by one row of the data frame + 1 data and feeds it back to the adder 54, and 58 is the adder 5
4 is an output terminal for outputting the output of 4. The data read from the memory 14 is applied to the multiplier 52 via the input terminal 50, multiplied by the predetermined coefficient of the generator matrix, and added by the adder 54.
Applied to. The adder 54 and the delay circuit 56 perform cumulative addition of the generation matrix in the diagonal direction indicated by the arrow 46 in FIG. 2 or 6 to generate the check point 42. The generated inspection point 42 is output to the memory 32 from the output terminal 58.

The inner code encoding circuit 20 has an arrow 48 in FIG.
Check point 4 of inner code by horizontal (row) direction scanning as shown in
4 is generated and written in the memory 24. (15,11) short
The generator matrix of the reduced cyclic Hamming code is G, the information matrix is X,
When the codeword is W, the encoding is performed by obtaining a matrix operation of w = x · G. Outer code Code
The digitization circuit 18 outputs the (11,7) shortened cyclic Haiming code.
If used, of each element of the information matrix x
x₁, X₂, X₃, ・ ・ ・, X₇Is the information data, so the code
W of each element of the word w ₁, W₂, W₃・ ・ ・, W₇Is outside
It can be obtained before the generation of the code check point.

In this embodiment, since the inner code is encoded with respect to the data of the data matrix 40 before the generation of the check point of the outer code, the data reading from the memory 14 is performed laterally (row). Inspection points can be added while going in the direction.

After the outer code check points are stored in the memory 22, the inner code coding circuit 26 reads the stored value in the memory 22, adds the inner code at the outer code check points, and checks the inner code. Generate points. Specifically, the elements w ₈ , w ₉ , w ₁₀ , w ₁₁ of the codeword w are generated using the elements x ₈ , x ₉ , x ₁₀ , x ₁₁ of the information matrix x which is the check point of the outer code. , Code word w
To complete.

The selection circuit 28 shows the information data output from the FIFO memory 16, the check points of the outer code output from the memory 22, and the check points of the inner code output from the inner code encoding circuit 26. 4 are selected and output as shown in FIG. The synchronization adding circuit 30 adds a synchronization code to the output of the selection circuit 28, and the recording circuit 32 adds the synchronization code to the synchronization adding circuit 3.
The output of 0 is recorded on a recording medium such as a magnetic tape, a magnetic disk, an optical disk.

[0018]

As can be easily understood from the above description, according to the present invention, the number of memory accesses can be reduced, the processing speed can be increased, and the address generating procedure can be simplified. There are advantages.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a scanning direction of a data matrix and an outer code.

FIG. 3 is a diagram showing outer code check points.

FIG. 4 is a diagram showing outer code check points and inner code check points.

FIG. 5 is a circuit specific example of an outer code encoding circuit 18.

FIG. 6 is a diagram showing scanning directions and check points of outer and inner codes according to the present embodiment.

FIG. 7 is a diagram showing a scanning (or transmission) order of information data.

[Explanation of symbols]

10: input terminal 12: mapping encoding circuit 14:
Memory 16: FIFO memory 18: Outer code encoding circuit 20: Inner code encoding circuit 22, 24: Memory 2
6: Inner code encoding circuit 28: Selection circuit 30: Synchronization addition circuit 32: Recording circuit

Claims (2)

[Claims] 1. A code transmission device for performing code transmission by adding an error detection or correction code by a product code, comprising outer code encoding / storing means for generating and storing outer code check points from information data. , Referring to the inner code encoding / storing means for generating and storing the inner code inspecting point from only the information data and the outer code inspecting point stored in the outer code encoding / storing means,
An inner code encoding means for completing an inner code check point stored in the inner code encoding / storing means. 2. A code transmission method for performing code transmission by adding an error detection or correction code by a product code, the first step of generating outer code check points and some inner code check points from information data. And a second step of referring to the outer code check point by the first step to complete the inner code check point partially generated by the first step, and information data, the outer code check point and the inner code check point. A third step of adding a synchronization code to a code check point and outputting the code in a predetermined format.