JPH0555661U - Genlock circuit of television camera controller - Google Patents

Abstract

(57) [Abstract] [Purpose] In a genlock circuit of a camera device used in combination with a camera head unit and a camera control unit, the lock-in time is long due to the effect of multiple phase locked loops due to the combination of a plurality of PLL circuits. The lock-in time is shortened. [Structure] A signal selection circuit for switching a VCO input signal of a PLL circuit for phase-locking a feedback signal from a PLL circuit of a final stage and a reference signal, a lock detector of a PLL circuit of a preceding stage, a timing signal generator, and a fixed bias generation. Composed of circuits. When the circuit is activated, a fixed bias is supplied to the VCO input to open loop until the previous PLL circuit is locked, and then the output phase error signal of the phase comparator is switched to closed loop.

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a genlock circuit of a television camera device.

[0002]

[Prior Art]

 Some television camera devices include a so-called genlock circuit in order to phase-synchronize the output video signal of the camera with an external synchronization signal. In a broadcasting camera device used in a studio or the like, in most cases, a camera head unit and a camera control unit (CCU) are used in combination. In this case, the genlock circuit is generally composed of a plurality of PLL circuits because the PLL circuit built in the camera head section and the PLL circuit of the camera control unit section are combined.

FIG. 3 shows a system diagram of a conventional genlock circuit. In this example, it is composed of three PLL circuits. The PLL circuits 2 and 4 are built in the camera control unit section, and the PLL circuit 6 is built in the camera head section. As an internal circuit configuration of the PLL circuit, as shown in FIG. 4, it is composed of a phase comparator 8, a VCO 9, and a synchronization signal generator 11. This operation is performed by outputting an external horizontal reference synchronization signal 1 and a synchronization signal generator 11. The horizontal synchronizing signal 12 is phase-compared by the phase comparator 8, and the oscillation frequency of the VCO 9 is controlled by the obtained phase error voltage. The obtained output signal 10 is supplied as a clock signal input to the synchronization signal generator 11.

Therefore, a phase locked loop (PLL) is formed, and the sync signal output of the sync signal generator 11 is phase-locked with the external reference sync signal 1. The PLL circuit 4 has the function of synchronizing the phase of the camera head and the camera control unit and varying the phase of the video signal. Operates in phase synchronization. The PLL circuit 6 incorporated in the camera head unit operates so that the output synchronizing signal 7 is in phase synchronization with the output synchronizing signal 5 of the PLL circuit 4. Therefore, the synchronization signal as a total system that combines the camera head and camera control unit is in phase synchronization with the external reference synchronization signal.

[0005]

[Problems to be solved by the device]

 In the above-mentioned prior art, when the camera head unit and the camera control unit are used in combination, a plurality of PLL circuits are connected as a genlock circuit, so that the lock-in time at power-on becomes long. There are drawbacks. Recently, CCD cameras have been widely used, and the stabilization time when the camera is activated is fast. In this case, the stabilization time of genlock is required to be as short as possible. The present invention aims to eliminate these drawbacks and shorten the lock-in time of genlock.

[0006]

[Means for Solving the Problems]

 In order to achieve the above-mentioned object, the present invention achieves the above-mentioned object. In order to prevent a plurality of PLL circuits connected in series from operating in a closed loop at the same time, a PLL for phase-locking the feedback signal from the final-stage PLL circuit and the reference synchronization signal. First, make the genlock circuit an open loop. Next, the lock detector detects the stable state of the PLL circuit in the previous stage, and when locking is completed, it is configured to switch to the closed loop after a certain time has elapsed. Lock detection that detects that the PLL circuit in the previous stage has locked After the circuit is started, the fixed bias signal is first supplied to the VCO input of the PLL circuit by adding the voltage generator, timing signal generator, fixed bias generation circuit, and signal selection circuit to the conventional circuit, and then the PLL circuit at the previous stage locks. The output phase error voltage of the phase comparator is supplied to the VCO input to switch to the closed loop.

[0007]

[Action]

 The lock detector determines whether the preceding PLL circuit is locked or unlocked, and the VCO input signal of the PLL circuit is switched from the fixed bias signal to the phase error signal by the signal selection circuit about 1 second after the lock. As a result, after the circuit starts, the genlock circuit is first made into an open loop, and the VCO oscillation frequency of all the PLL circuits is switched to the closed loop after the oscillation frequency of the VCO becomes close to the center frequency, that is, the frequency at the time of lock. ..

[0008]

【Example】

 An embodiment of the present invention will be described below with reference to FIGS. In the present invention, the configurations of 13 to 18 are added to the conventional circuits shown in FIGS. A lock detector 13 is supplied with the phase error signal obtained by the phase comparator 8 (FIG. 4) in the PLL circuit 2. In this embodiment, a voltage comparator is used, and lock detection is performed by comparing the reference voltage and the phase error voltage. When unlocked, it outputs a “0” level signal, and when locked, it outputs a “1” level logic level signal. A timing signal generator 14 is driven by the output signal of the lock detector 13. In this embodiment, the contents of the timing generator 14 are composed of a monostable multivibrator and a gate circuit. The operation outputs a "0" level when the PLL circuit 2 is unlocked, and outputs a "1" level approximately one second after the lock detector 13 outputs the lock signal. The output signal 15 of the timing signal generator 14 is supplied to the PLL circuit 4.

FIG. 2 shows the internal configuration of this PLL circuit. The output signal 15 of the PLL circuit 14 is supplied to the signal selection circuit 18 shown in FIG. A fixed bias generation circuit 16 outputs a voltage value at which the oscillation frequency of VCO becomes the center value. That is, a DC voltage having the same potential as the VCO input phase error voltage when locked is output. This fixed bias voltage 17 is supplied to the signal selection circuit 18 shown in FIG. The operation of the signal selection circuit 18 is driven by the output signal 15 of the timing signal generator 14, and when the output signal 15 is at “0” level, that is, the PLL circuit 2 is unlocked, the fixed bias voltage 17 is selected. And is supplied to the VCO 9. When the output signal 15 is at "1" level, that is, when the PLL circuit 2 is locked, the output phase error voltage of the phase comparator 8 is selected and supplied to the VCO 9. Therefore, as the operation of the genlock circuit as a whole, when the power of the apparatus is turned on, the PLL circuit 2 is phase-locked, the PLL circuit 4 is in an open loop until about 1 second elapses, and then switched to the closed loop.

[0010]

[Effect of the device]

 According to the present invention, in the genlock circuit of the television camera device, the disadvantage that the synchronization pull-in time becomes long due to the influence of multiple loops by the combination of a plurality of PLL circuits is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is an internal configuration diagram of a PLL circuit of the present invention.

FIG. 3 is a block diagram showing an example of a conventional technique.

FIG. 4 is an internal configuration diagram of a general PLL circuit.

[Explanation of symbols]

1: external reference synchronizing signal, 2, 4, 6: PLL circuit, 1
3: Lock detector, 14: Timing signal generator, 1
6: fixed bias generation circuit, 18: signal selection circuit

Claims (1)

[Scope of utility model registration request] 1. A genlock circuit of a camera control device composed of a plurality of PLL circuits connected in series, wherein a lock detector for determining a locked state of these PLL circuits is provided, and the plurality of the lock detectors are determined based on a result of the determination. In the above PLL circuit, a fixed voltage is supplied to the VCO input of the PLL circuit for phase-synchronizing the synchronization signal and the reference synchronization signal fed back from the camera head section, and if the preceding PLL circuit is unlocked, the above genlock circuit is supplied. A genlock circuit for a television camera controller, characterized in that the genlock circuit is configured to be in an open loop and to supply the output phase error voltage of the phase comparator of the PLL circuit after locking to switch the genlock circuit to a closed loop.