JPH0555629U - Connection impedance correction circuit between logic differential circuits - Google Patents
Connection impedance correction circuit between logic differential circuitsInfo
- Publication number
- JPH0555629U JPH0555629U JP11081591U JP11081591U JPH0555629U JP H0555629 U JPH0555629 U JP H0555629U JP 11081591 U JP11081591 U JP 11081591U JP 11081591 U JP11081591 U JP 11081591U JP H0555629 U JPH0555629 U JP H0555629U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- coaxial cable
- differential circuit
- circuit
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】
【目的】 論理差動回路1の正負出力11・12を同軸
ケーブル2A・2Bとプリント基板3のパターン3A・
3Bにより論理差動回路4の正負入力4A・4Bまで伝
送する場合に、反射波の少ない接続インピーダンス補正
回路を提供する。
【構成】 同軸ケーブル2Aとパターン3Aの接続点3
Cと、同軸ケーブル2Bとパターン3Bの接続点3Dの
間に補正抵抗6を接続する。
(57) [Abstract] [Purpose] The positive and negative outputs 11 and 12 of the logic differential circuit 1 are connected to the coaxial cables 2A and 2B and the pattern 3A of the printed circuit board 3.
Provided is a connection impedance correction circuit with less reflected waves when transmitting to the positive / negative inputs 4A and 4B of the logical differential circuit 4 by 3B. [Configuration] Connection point 3 between the coaxial cable 2A and the pattern 3A
The correction resistor 6 is connected between C and the connection point 3D of the coaxial cable 2B and the pattern 3B.
Description
【0001】[0001]
この考案は、第1の論理差動回路の正負出力を同軸ケーブルとプリント基板の パターンで第2の論理差動回路の正負入力に伝送する場合の接続インピーダンス 補正回路についてのものである。 This invention relates to a connection impedance correction circuit for transmitting the positive / negative output of the first logical differential circuit to the positive / negative input of the second logical differential circuit by the pattern of the coaxial cable and the printed circuit board.
【0002】[0002]
次に、従来技術によるインピーダンス補正回路を図2により説明する。図1の 1と4は論理差動回路、2Aと2Bは同軸ケーブル、3はプリント基板、3Aと 3Bはプリント基板3のパターン、5Aと5Bは終端抵抗である。 Next, a conventional impedance correction circuit will be described with reference to FIG. In FIG. 1, 1 and 4 are logical differential circuits, 2A and 2B are coaxial cables, 3 is a printed circuit board, 3A and 3B are patterns of the printed circuit board 3, and 5A and 5B are terminating resistors.
【0003】 図2では、論理差動回路1からの正出力11は同軸ケーブル2Aで伝送され、 論理差動回路1からの負出力12は同軸ケーブル2Bで伝送される。同軸ケーブ ル2Aはプリント基板3のパターン3Aに接続され、同軸ケーブル2Bはプリン ト基板3のパターン3Bに接続される。パターン3Aは論理差動回路4の正入力 4Aに接続され、パターン3Bは論理差動回路4の負入力4Bに接続される。論 理差動回路4の正入力4Aは終端抵抗5Aで終端され、論理差動回路4の負入力 4Bは終端抵抗5Bで終端される。In FIG. 2, the positive output 11 from the logical differential circuit 1 is transmitted by the coaxial cable 2A, and the negative output 12 from the logical differential circuit 1 is transmitted by the coaxial cable 2B. The coaxial cable 2A is connected to the pattern 3A of the printed board 3, and the coaxial cable 2B is connected to the pattern 3B of the printed board 3. The pattern 3A is connected to the positive input 4A of the logical differential circuit 4, and the pattern 3B is connected to the negative input 4B of the logical differential circuit 4. The positive input 4A of the logical differential circuit 4 is terminated by the terminating resistor 5A, and the negative input 4B of the logical differential circuit 4 is terminated by the terminating resistor 5B.
【0004】[0004]
図2のパターン3A・3Bは、同軸ケーブル2A・2Bに比べて線長が短く、 インピーダンスのばらつきが大きい。パターン3A・3Bは高密度化に伴い、イ ンピーダンスは高くなっている。 The patterns 3A and 3B shown in FIG. 2 have a shorter line length than the coaxial cables 2A and 2B, and have large variations in impedance. Patterns 3A and 3B have higher impedance with higher density.
【0005】 次に、図2の各部の波形例を図3により説明する。図3アで論理差動回路1の 正出力波形であり、図3イは論理差動回路4の正入力波形である。図3アは例え ば 300〜 500MHz の周波数帯域で、立上り時間 1nsの波形である。図3イでは位 置P1・Q1で反射波が出ている状態を示す。図3イの反射係数は、例えば0.17 ρ程度である。図3イの反射波がおきるのは、論理差動回路1から論理差動回路 4までの伝送路のインピーダンスが整合していないためである。図3ウは論理差 動回路1から論理差動回路4までの伝送路のインピーダンスが整合している場合 の論理差動回路4の正入力波形であり、図3イの反射波は出ない。Next, a waveform example of each part of FIG. 2 will be described with reference to FIG. 3A shows the positive output waveform of the logical differential circuit 1, and FIG. 3A shows the positive input waveform of the logical differential circuit 4. Figure 3a shows a waveform with a rise time of 1 ns in the frequency band of 300 to 500 MHz, for example. FIG. 3A shows a state in which reflected waves are generated at the positions P1 and Q1. The reflection coefficient in FIG. 3A is, for example, about 0.17 ρ. The reflected wave in FIG. 3A occurs because the impedance of the transmission path from the logical differential circuit 1 to the logical differential circuit 4 is not matched. FIG. 3C shows the positive input waveform of the logical differential circuit 4 when the impedances of the transmission lines from the logical differential circuit 1 to the logical differential circuit 4 are matched, and the reflected wave of FIG. 3A does not appear.
【0006】 図2の回路で反射波をなくすには、インピーダンス整合が必要になる。従来技 術では、プリント基板3のインピーダンスは製造上のばらつきが大きく、制御が 困難である。このため、同軸ケーブルをプリント基板3上に実装しなければなら なかった。従来のインピーダンス補正回路では、補正用の同軸ケーブルを実装す る空間の確保が困難であった。Impedance matching is required to eliminate reflected waves in the circuit of FIG. In the conventional technique, the impedance of the printed circuit board 3 has a large manufacturing variation and is difficult to control. For this reason, the coaxial cable had to be mounted on the printed circuit board 3. In the conventional impedance correction circuit, it was difficult to secure a space for mounting the correction coaxial cable.
【0007】 この考案は、論理差動回路1の正負出力を同軸ケーブル2A・2Bとプリント 基板3のパターン3A・3Bにより論理差動回路4の正負入力4A・4Bまで伝 送する場合に、同軸ケーブル2A・2Bとプリント基板3のパターン3A・3B の接続点間に補正抵抗を追加することにより接続インピーダンスを補正し、反射 波を少なくすることを目的とする。According to the present invention, when the positive and negative outputs of the logic differential circuit 1 are transmitted to the positive and negative inputs 4A and 4B of the logic differential circuit 4 by the coaxial cables 2A and 2B and the patterns 3A and 3B of the printed circuit board 3, the coaxial outputs are transmitted. The purpose is to correct the connection impedance by adding a correction resistor between the connection points between the cables 2A and 2B and the patterns 3A and 3B on the printed circuit board 3 and reduce the reflected waves.
【0008】[0008]
この目的を達成するため、この考案では、同軸ケーブル2Aとパターン3Aの 接続点3Cと、同軸ケーブル2Bとパターン3Bの接続点3Dの間に補正抵抗6 を接続する。 In order to achieve this object, in the present invention, a correction resistor 6 is connected between a connection point 3C between the coaxial cable 2A and the pattern 3A and a connection point 3D between the coaxial cable 2B and the pattern 3B.
【0009】[0009]
次に、この考案によるインピーダンス補正回路の構成を図1により説明する。 図1の3Cは同軸ケーブル2Aとパターン3Aの接続点、3Dは同軸ケーブル2 Bとパターン3Bの接続点、6は補正抵抗であり、その他は図2と同じものであ る。すなわち、図1は図2の接続点3C・3D間に補正抵抗6を接続したもので ある。 Next, the configuration of the impedance correction circuit according to the present invention will be described with reference to FIG. 1C is a connection point between the coaxial cable 2A and the pattern 3A, 3D is a connection point between the coaxial cable 2B and the pattern 3B, 6 is a correction resistor, and the others are the same as those in FIG. That is, in FIG. 1, the correction resistor 6 is connected between the connection points 3C and 3D of FIG.
【0010】 図1では、同軸ケーブル2A・2Bのインピーダンスを等しくし、プリント基 板3のパターン3A・3Bのインピーダンスを等しくする。また、パターン3A ・3Bのインピーダンスは同軸ケーブル2A・2Bのインピーダンスより高く、 終端抵抗5A・5Bの値と等しく設定する。図3ウのように反射波がおきないよ うに、接続点3C・3Dの間に接続した補正抵抗6で補正する。In FIG. 1, the coaxial cables 2A and 2B have the same impedance, and the patterns 3A and 3B of the printed board 3 have the same impedance. The impedance of the patterns 3A and 3B is higher than the impedance of the coaxial cables 2A and 2B, and is set to be equal to the value of the terminating resistors 5A and 5B. As shown in FIG. 3C, correction is performed by the correction resistor 6 connected between the connection points 3C and 3D so that reflected waves do not occur.
【0011】[0011]
例えば、ECLロジックを使用し、同軸ケーブル2A・2Bのインピーダンス =50Ω、パターン3A・3Bのインピーダンス=70Ω、終端抵抗5A・5B =70Ωの場合、補正抵抗6の抵抗値は約350Ωである。 For example, when the ECL logic is used and the impedance of the coaxial cables 2A and 2B is 50Ω, the impedance of the patterns 3A and 3B is 70Ω, and the termination resistors 5A and 5B are 70Ω, the resistance value of the correction resistor 6 is about 350Ω.
【0012】[0012]
この考案によれば、第1の論理差動回路の正負出力を同軸ケーブルとプリント 基板のパターンにより第2の論理差動回路の正負入力まで伝送する場合に、同軸 ケーブルとプリント基板のパターンの接続点間に補正抵抗を追加するので、同軸 ケーブルとプリント配線による伝送の反射波を少なくすることができる。 According to this invention, when the positive / negative output of the first logical differential circuit is transmitted to the positive / negative input of the second logical differential circuit by the pattern of the coaxial cable and the printed circuit board, the connection of the coaxial cable and the printed circuit board pattern is connected. Since a correction resistor is added between the points, the reflected wave of the transmission by the coaxial cable and the printed wiring can be reduced.
【図1】この考案による接続インピーダンス補正回路の
構成図である。FIG. 1 is a configuration diagram of a connection impedance correction circuit according to the present invention.
【図2】従来技術によるインピーダンス補正回路の構成
図である。FIG. 2 is a configuration diagram of an impedance correction circuit according to a conventional technique.
【図3】図2の信号波形図である。FIG. 3 is a signal waveform diagram of FIG.
1 論理差動回路 2A・2B 同軸ケーブル 3A・3B プリント配線 3C・3D 接続点 4 論理差動回路 4A 正入力 4B 負入力 5A・5B 終端抵抗 6 補正抵抗 11 正出力 12 負出力 1 Logic differential circuit 2A / 2B Coaxial cable 3A / 3B Printed wiring 3C / 3D Connection point 4 Logic differential circuit 4A Positive input 4B Negative input 5A / 5B Termination resistor 6 Correction resistor 11 Positive output 12 Negative output
Claims (1)
第1の同軸ケーブル(2A)とプリント基板(3) の第1のパ
ターン(3A)で第2の論理差動回路(4) の正入力(4A)に伝
送し、第1の論理差動回路(1) の負出力(12)を第2の同
軸ケーブル(2B)とプリント基板(3) の第2のパターン(3
B)で第2の論理差動回路(4) の負入力(4B)に伝送し、第
2の論理差動回路(4) の正入力(4A)に第1の終端抵抗(5
A)を接続し、第2の論理差動回路(4) の負入力(4B)に第
2の終端抵抗(5B)を接続する場合に、 第1の同軸ケーブル(2A)と第1のパターン(3A)の第1の
接続点(3C)と、第2の同軸ケーブル(2B)と第2のパター
ン(3B)の第2の接続点(3D)の間に補正抵抗(6)を接続す
ることを特徴とする論理差動回路間の接続インピーダン
ス補正回路。1. The positive output (11) of the first logic differential circuit (1) is provided with a second logic difference between the first coaxial cable (2A) and the first pattern (3A) of the printed circuit board (3). To the positive input (4A) of the drive circuit (4) and the negative output (12) of the first logic differential circuit (1) to the second coaxial cable (2B) and the second output of the printed circuit board (3). Pattern (3
B) transmits to the negative input (4B) of the second logic differential circuit (4) and the positive input (4A) of the second logic differential circuit (4) to the first terminating resistor (5
When connecting A) and connecting the second terminating resistor (5B) to the negative input (4B) of the second logic differential circuit (4), the first coaxial cable (2A) and the first pattern Connect the correction resistor (6) between the first connection point (3C) of (3A) and the second connection point (3D) of the second coaxial cable (2B) and the second pattern (3B). A connection impedance correction circuit between logic differential circuits characterized by the above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11081591U JPH0555629U (en) | 1991-12-19 | 1991-12-19 | Connection impedance correction circuit between logic differential circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11081591U JPH0555629U (en) | 1991-12-19 | 1991-12-19 | Connection impedance correction circuit between logic differential circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0555629U true JPH0555629U (en) | 1993-07-23 |
Family
ID=14545367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11081591U Pending JPH0555629U (en) | 1991-12-19 | 1991-12-19 | Connection impedance correction circuit between logic differential circuits |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0555629U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008289144A (en) * | 2007-05-07 | 2008-11-27 | Natl Semiconductor Corp <Ns> | Termination compensation for differential signal on glass |
JP2013251870A (en) * | 2012-06-04 | 2013-12-12 | Fujitsu Ltd | Electronic apparatus and semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02164159A (en) * | 1988-12-19 | 1990-06-25 | Mitsubishi Electric Corp | Digital signal transmission/reception circuit |
JPH03171849A (en) * | 1989-11-21 | 1991-07-25 | Hitachi Ltd | Signal transmission system and circuit |
-
1991
- 1991-12-19 JP JP11081591U patent/JPH0555629U/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02164159A (en) * | 1988-12-19 | 1990-06-25 | Mitsubishi Electric Corp | Digital signal transmission/reception circuit |
JPH03171849A (en) * | 1989-11-21 | 1991-07-25 | Hitachi Ltd | Signal transmission system and circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008289144A (en) * | 2007-05-07 | 2008-11-27 | Natl Semiconductor Corp <Ns> | Termination compensation for differential signal on glass |
JP2013251870A (en) * | 2012-06-04 | 2013-12-12 | Fujitsu Ltd | Electronic apparatus and semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3585399A (en) | A two impedance branch termination network for interconnecting two systems for bidirectional transmission | |
US4086534A (en) | Circuit for wire transmission of high frequency data communication pulse signals | |
US8081487B2 (en) | Signal transmission circuit, IC package, and mounting board | |
US5376904A (en) | Directional coupler for differentially driven twisted line | |
US5265038A (en) | Computer system peripheral connection pulse filtering technique and circuit | |
JPH0555629U (en) | Connection impedance correction circuit between logic differential circuits | |
JPH1027049A (en) | Interconnected bus | |
CA1241084A (en) | Bidirectional bus arrangement for a digital communication system | |
US7746195B2 (en) | Circuit topology for multiple loads | |
US20020130680A1 (en) | Method and apparatus for terminating emitter coupled logic (ECL) transceivers | |
US6366972B1 (en) | Multi-user communication bus with a resistive star configuration termination | |
US6570463B1 (en) | Signal transmission system | |
JPH0323693Y2 (en) | ||
US6268783B1 (en) | Printed circuit board including signal transmission line capable of suppressing generation of noise | |
JP3070570B2 (en) | Terminal load automatic setting device | |
JPS62176153A (en) | Ic package | |
JPH0575551A (en) | Clock signal transmitting circuit | |
CN112398540B (en) | Optical module and signal processing system comprising same | |
JP2000151721A (en) | Bus line terminating circuit for electronic equipment | |
JPH04264609A (en) | Inter-package connection system | |
JPH03272579A (en) | Connector | |
JP2596413Y2 (en) | Waveform compensation circuit for motherboard and daughter board | |
JPH05341892A (en) | Information processor | |
JP3493650B2 (en) | Communication device | |
JPH0514360A (en) | Bus transmission system |