JPH0555601A - Nonvolatile electronic memory device - Google Patents

Abstract

PURPOSE:To provide a nonvolatile electronic memory device which realizes a FLOTOX-type EEPROM high in integration. CONSTITUTION:In a nonvolatile electronic memory device, which is equipped with floating gate type MOS transistor structure, and in which one part of the insulating film 3 right below the floating gate is a thin layer part 3a, and the entrance and exit of the tunnel current to the floating gate 4 is done through the thin layer part 3a, the thin layer part 3a is positioned near a MOS structure of channel formation area CH.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to non-volatile electronic memory devices.

[0002]

2. Description of the Related Art In recent years, microcomputers have been built into equipment in almost all fields. A memory device is indispensable for mounting a microcomputer. As a memory device,
SRAMs and DRAMs are used, but these have the disadvantage that the contents stored in them are lost when the power is turned off. It is a non-volatile electronic memory device that has improved this so that the stored contents are not erased even when the power is turned off. Among them, electrically writable / erasable ones are EEPROMs (ELectrically Erasable and
Programmable ROM). However, the EEPROM has the advantages of a non-volatile memory function and electrically writable / erasable, but on the other hand, it has a disadvantage that the integration degree is low and the price per bit is high due to the large cell area.

The EEPROM is structurally divided into a MNOS type and a FLOTOX type. The former MNOS type is an element that exhibits a non-volatile memory function by storing electrons in a trap at the interface between an oxide film and a nitride film, and the latter FLOTOX.
The mold is an element that exerts a non-volatile memory function by storing electrons in a polysilicon floating gate that is electrically insulated from anywhere by an oxide film (insulating film). The latter FLO
TOX (FLOating-gate Tunnel OXide) type EEPROM
Has been widely used since it has a long memory retention time and good compatibility with MOS processes.

In the case of a FLOTOX type EEPROM in which electrons are stored in a polysilicon floating gate, a polysilicon control gate for controlling tunnel current flow in and out of the floating gate is provided on the polysilicon floating gate.
There are a layer type and a one layer type in which the control gate is formed by diffusing impurities into the single crystal semiconductor substrate. The latter one-layer type has the advantages that the manufacturing process is simple and a single crystal silicon oxide film can be used on the control gate side, so that the retention characteristics are good.

FIGS. 6 and 7 show a conventional one-layer type FL.
Represents an OTOX type EEPROM. FIG. 6 shows Y of FIG.
-Y cross section is shown. In the FLOTOX type EEPROM, one cell is composed of a floating gate type MOS transistor structure and its control gate (control gate line).
That is, the p-type well (p
Type impurity diffusion layer) 52 is provided, and the source region (n type impurity diffusion layer) 5 is formed on the surface of the p type well 52.
2a and a drain region (n-type impurity diffusion layer) 52b are formed, and a polysilicon floating gate 54 is formed on the drain region 52b via an insulating film 53. This MOS
The transistor structure is an n-channel type, and a channel formation region CH is between the source region 52a and the drain region 52b. Then, a part of the insulating film 53 directly below the floating gate 54 of the MOS transistor structure is a thin layer portion 5 having a thickness of about 100Å for tunneling current in and out of the floating gate 54.
3a.

On the other hand, a control gate 52c is provided on the surface portion of the p-type well 52 of the semiconductor substrate 51, the floating gate 54 reaches above the control gate 52c, and the floating gate 54 and the control gate 52c have a capacitance. Are connected.
By driving the control gate 52c, a tunnel current can flow. In FIG. 6, the floating gate 54 is a MOS
Although it is divided into two in the transistor structure region, as shown in FIG. 7, they are connected in the control gate 52c region and are one.

In this EEPROM, an appropriate voltage is applied to each of the control gate 52c and the drain region 52b, a tunnel current is passed through the thin layer portion 53a to exchange charges, and the threshold voltage is changed to electrically write. / Can be erased. As described above, the one-layer type FLOTOX EEPROM
Although the manufacturing process is simple and the holding characteristics are good, the cell area is large due to the control gate being lateral and it is difficult to increase the degree of integration. Even if an attempt is made to achieve high integration, it is not possible because the MOS transistor structure portion becomes large. Since the thin layer portion 53a for tunneling in and out of the tunnel current is brought to a position considerably distant from the channel forming region CH, the drain region 52b becomes larger and the cell area becomes wider accordingly. The thin layer portion 53a for tunneling current in and out is formed at a position apart from the channel formation region CH.
This is because it has been considered that a should be separated as much as possible because it has an unfavorable influence on the characteristics of the channel formation region CH.

[0008]

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a non-volatile electronic memory device capable of realizing a FLOTOX type EEPROM having a high degree of integration.

[0009]

In order to solve the above-mentioned problems, the nonvolatile electronic memory device according to claim 1 or 2 is provided with a floating gate type MOS transistor structure, and a part of an insulating film immediately below the floating gate is formed. In the thin layer portion, the tunnel current to and from the floating gate is made to flow through the thin layer portion, and the thin layer portion is located in the vicinity of the channel formation region of the MOS transistor structure. I am trying to let you.

In the case of the non-volatile electronic memory device of the present invention, in particular, the control gate for controlling the input and output of the tunnel current is formed with the source region and the drain region of the MOS transistor structure as in the second aspect. This is very effective in the case of a single layer type formed on a semiconductor substrate, but is not limited to this.

[0011]

According to the nonvolatile electronic memory device of the present invention,
The thin layer part of the insulating film for the tunnel current flow
Even if it comes close to the channel formation region of the S-transistor structure, the channel formation region is not so badly affected, and the memory operation is not particularly hindered. Then, since the thin layer portion is close to the branch portion 54a of the floating gate 54 in the conventional case, the impurity diffusion region for the drain region can be reduced accordingly, so that the cell area is reduced and the integration degree is reduced. Increase.

The driving condition is also in a sufficiently practical range as follows.
Can be kept. 1 layer type FLOTOX EEPROM
In this case, the capacitive coupling constant K, which is an important indicator of driving conditions,
_WIs the oxide film (insulating film) volume between the floating gate and the p-type well.
Amount C_GT, N-type impurity diffusion for floating gate and drain regions
The oxide film capacity with the diffusion layer is C_TNFor floating gates and control gates
The oxide film capacitance with the n-type impurity diffusion layer of_PPAnd then the edge
V to child Ta_PP(V), O (V) is applied to terminals Tb and Tc
When writing, K_W= C_PP/ (C_GT+ C_TN+ C _PP)
Becomes However, the terminal Ta is the terminal of the control gate and the terminal Tb.
Is a drain region terminal, and terminal Tc is a p-type well terminal
is there. The equivalent circuit is shown in FIG. Capacitive coupling constant K_WIs floating
What percentage of the program voltage is thin when there is no charge on the free gate
It indicates whether it is applied to the layer part, and if this value is small
Secures a certain size because the write voltage becomes high
Otherwise, the driving conditions will be severe. However, the place of this invention
Required capacitance coupling constant K_W(About 0.7) is no problem
It is secured. This is the floating gate and drain
The oxide film capacitance with the n-type impurity diffusion layer for the region_TNIs small
Because it will be.

In the conventional case, as shown in FIG. 7, the floating gate 54 has a branch portion 54a extending to the thin layer portion 53a, which greatly increases the oxide film capacitance C _TN. Since the thin layer portion comes close to the channel formation region, the branch portion 54a is practically omitted, and the oxide film capacitance C _TN becomes small. As a result, the required amount of capacitive coupling constant K
_W is secured, and the driving conditions do not become severe.

[0014]

Embodiments of the non-volatile electronic memory device of the present invention will be described in detail below with reference to the drawings. The present invention is not limited to the following embodiments. FIG. 1 and FIG. 2 show a main part configuration of a one-layer type FLOTOX EEPROM of the embodiment. FIG. 1 shows the XX cross section of FIG. In this FLOTOX type EEPROM, a floating gate type MO
S-transistor structure and control gate (control gate line)
One cell is composed of. 1 and 2 for convenience in FIGS.
Although only cells are shown, it goes without saying that a large number of cells are integrated.

The FLOTOX type EEPROM of the embodiment is
A p-type well (p-type impurity diffusion layer) 2 is provided on an n-type single crystal semiconductor substrate 1, and a source region (n-type impurity diffusion layer) 2a and a drain region (n-type) are formed on the surface of the p-type well 2. The impurity diffusion layer) 2b is formed, and the polysilicon floating gate 4 is formed on the impurity diffusion layer 2b via the insulating film 3. This MOS transistor structure is an n-channel type and has a source region 2a and a drain region 2
A channel formation region CH is located between b.

A part of the insulating film 3 immediately below the floating gate 4 of the MOS transistor structure is a thin layer part 3a having a thickness of about 100Å for injecting a tunnel current into the floating gate 4. As described above, since the thin layer portion 3a is located in the vicinity of the channel formation region CH of the MOS transistor structure, the cell area and the floating gate 4 are smaller than in the conventional case. As will be described later, the thin layer portion 3a is formed into a channel formation region CH of the MOS transistor structure.
It can be easily placed in the vicinity of, without any difficulty.

In this EEPROM, an appropriate voltage is applied to the control gate 2c and the drain region 2b,
Writing / erasing can be performed by changing the threshold voltage by exchanging electric charges by passing a tunnel current through the thin layer portion 3a. Then, the FLOTOX type EE of the embodiment
The manufacturing of the PROM will be described. First, as shown in FIG. 3, after a p-type well (p-type impurity diffusion layer) 2 is formed on an n-type single crystal semiconductor substrate 1 through a photolithography process, an ion implantation process, etc., a separation LOCOS oxide film ( Insulating film) 3b is formed.

Then, as shown in FIG. 4, an n-type impurity diffusion layer for the control gate 2c is formed at a position below the floating gate, and the unnecessary oxide film is once removed and then the thickness 500 is formed.
An oxide film (insulating film) of Å is formed, and the oxide film is selectively removed only at the thin layer portion (using a photolithography process and a hydrofluoric acid etching process), and then an oxide film of about 100 Å thickness is formed. A thin layer portion 3a made of (insulating film) is formed to complete the MOS transistor structure insulating film 3.

Subsequently, 4500 Å of P (phosphorus) -doped poly (polycrystalline) silicon is deposited by the LPCVD process,
As will be seen in the above, the thin layer portion 3a is patterned in the form of a floating gate in the photolithography process and the RIE etching process. Then, a mask including the remaining polysilicon pattern and the LOCOS oxide film (insulating film) 3b as a part is formed, and As is doped and diffused to complete the source region 2a and the drain region 2b. At this time, since the tunnel current flow portion is formed in a self-aligning manner by lateral diffusion of the impurities for forming the drain region 2b using the floating gate 4 as a mask, the thin layer portion 3a is well positioned near the channel formation region CH. ..

The present invention is not limited to the above embodiment. The above embodiment is based on the one-layer polycrystalline silicon type FLOTO.
Although the X-type EEPROM is used, it may be a two-layer polycrystalline silicon FLOTOX-type EEPROM.

[0021]

As described above, the non-volatile electronic memory device according to the first and second aspects of the present invention can reduce the cell area, so that the degree of integration is increased and the required size is increased. Since the capacitive coupling constant K _{W is} also secured, the driving condition remains within an appropriate range, which is very useful.

Since the non-volatile electronic memory device according to the second aspect of the present invention is a single-layer type device, in addition, it is easy to manufacture and has excellent holding characteristics, and is more useful.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a configuration of a main part of a FLOTOX type EEPROM according to an embodiment.

FIG. 2 is a plan view showing a configuration of a main part of a FLOTOX EEPROM of an embodiment.

FIG. 3 is a cross-sectional view for explaining a state of a p-well formation stage of the FLOTOX EEPROM of the embodiment.

FIG. 4 is a sectional view for explaining a state of an insulating film forming step of the FLOTOX EEPROM of the example.

FIG. 5 is an equivalent circuit diagram showing a coupling relation of capacitances generated in respective portions of the one-layer type FLOTOX EEPROM.

FIG. 6 is a cross-sectional view showing a configuration of a main part of a conventional FLOTOX EEPROM.

FIG. 7 is a plan view showing a configuration of a main part of a conventional FLOTOX EEPROM.

[Explanation of sign]

 1 semiconductor substrate 2 p-type well 2a source region 2b drain region 2c control gate 3 insulating film 3a thin layer portion 4 floating gate CH channel formation region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication G11C 16/04

Claims (2)

[Claims] 1. A floating gate type MOS transistor structure is provided, wherein a part of an insulating film directly under the floating gate is a thin layer portion, and tunnel currents to and from the floating gate are made through the thin layer portion. In the non-volatile electronic memory device, the thin layer portion is a MOS.
A non-volatile electronic memory device characterized by being located in the vicinity of a channel formation region of a transistor structure. 2. A non-volatile electronic memory device, wherein a control gate for controlling the entrance and exit of a tunnel current is formed on a semiconductor substrate in which a source region and a drain region of a MOS transistor structure are formed.