JPH0555574A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To shorten the gate length of a buried gate electrode and to suppress the extension of the electrode in a depth direction to a necessary limit by suppressing the extension of a recess in which the electrode is to be buried. CONSTITUTION:An etching resistant film 5 covering grooves 4 formed on insulating films at both sides of an element forming layer 3, is formed, openings 6 of the film 5 are formed partly at the grooves 4 of both sides at the side of the layer 3, etchants are introduced from both the openings 6, and recesses 7 of an insulating film 2 to be connected under the layer 3 are formed. Thus, since the impregnation of the etchant toward a depth direction is suppressed to a certain degree, the etchant can be concentrically impregnated toward the film 2 under the layer 3 through the openings 6. Accordingly, the recesses 7 passed under the layer 3 can be formed before the etching is proceeded in gate length and depth directions. Therefore, the size of a buried gate electrode 9 is also suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a field effect transistor having a gate electrode on both sides of a semiconductor layer to be a channel region layer. Regarding

[0002]

2. Description of the Related Art Here, a conventional method of manufacturing a semiconductor device will be described with reference to the drawings. In this conventional example,
An n-channel MOS field effect transistor will be described as an example.

20 to 23 are process diagrams of forming a semiconductor device according to a conventional example. Note that Fig. 20 (a), Fig. 21 (a), and Fig. 22
20A is a top view of the semiconductor device, and FIG. 20B is X ₁ of FIG. 20A.
-Y ₁ line cross-sectional view, and FIG. 20 (c) is X ₂ -Y ₂ line sectional view of FIG. 20 (a).

Further, FIG. 21 (b) is the X of FIG. 21 (a).₃-Y₃line
Cross-sectional view, Figure 21 (c) is X of Figure 21 (a)_Four-Y_FourIt is a line sectional view
It Further, FIG. 22 (b) shows X of FIG. 22 (a)._Five-Y_FiveLine cross section,
Figure 23 shows X in Figure 22 (a)₆-Y ₆It is a line sectional view.

First, as shown in FIGS. 20 (a) to 20 (c), a supporting substrate 1j and a silicon substrate to be an element forming layer are formed by sandwiching the SiO ₂ film 2j by a bonding method, and then the silicon substrate is polished. Form a thin layer. Subsequently, the thin layer is patterned by a photolithography method to form a strip-shaped element forming layer 3j.

Next, after forming a resist film Rj on the entire surface, an opening 4j for introducing an etching solution is formed in the resist film Rj on both sides of the SiO ₂ film 2j with the element forming layer 3j interposed therebetween. Hydrofluoric acid, which is an etching solution, is poured from the opening 4j to selectively etch the SiO ₂ film 2j. As a result, hydrofluoric acid isotropically permeates into the SiO ₂ film 2j and forms a recess 7j penetrating the lower part of the element forming layer 3j as shown in FIG.

Then, the resist film R is removed by a stripping solution.
After removing j, a thermal oxide film 8j is formed on the surface of the element forming layer 3j by a thermal oxidation method. Further, a polysilicon film as a conductor film is formed in the recess 7j by the CVD method to form a buried gate electrode 9j.

Next, after removing the polysilicon film on the element forming layer 3j, a polysilicon film is newly formed by the CVD method and the polysilicon film is patterned to cross the surface of the strip-shaped element forming layer 3j. The strip-shaped gate electrode 10j is selectively formed. As a result, the element forming layer 3j sandwiched by the buried gate electrode 9j and the gate electrode 10j becomes the channel region layer C5.

Further, with the gate electrode 10j as a mask, the channel region layer C is formed by an ordinary ion implantation method.
Arsenic ions (As ⁺ ) are implanted into the element forming layers 3j on both sides of 5 to form source / drain (S / D) region layers 11j and 12j.

Next, an interlayer insulating film made of SiO ₂ or the like is formed on the entire surface.
By forming 13j and patterning, S / D
Contact holes 14j are formed in the region layers 11j and 12j.
As a result, a field effect transistor is formed as shown in FIGS.

[0011]

According to the method of the above-mentioned conventional example, as shown in FIGS. 22 and 23, the buried gate electrode 9j is formed.
Is considerably larger than that of the gate electrode 10j, and if excessive etching is performed so as to surely form the recess 7j under the element forming layer 3j, the gate length of the buried gate electrode 9j becomes larger than that of the gate electrode 10j. In some cases, the buried gate electrode 9j may reach below the contact hole 14j in the source / drain regions 11j and 12j.

By the way, originally, when a negative voltage is applied to the gate, the drain current does not flow as shown in the graph of the gate voltage-drain current characteristic of FIG. 19 (a). However, since the buried gate electrode 9j has a long gate length,
In the case where the buried gate electrode 9j reaches below the drain electrode contact hole 14j, when the negative voltage is applied to the buried gate electrode 9j, the source region 11
j, the n-type region of the drain region 12j is inverted to p-type. This phenomenon is particularly remarkable when the thin element forming layer 3j is used as in the conventional example.

Therefore, all the element forming layers 3j below the buried gate electrode 9j are rendered conductive. Therefore, as shown in Fig. 19 (b), even if the gate voltage is negative,
Drain current will flow.

Further, as shown in FIGS. 22 and 23, the buried gate electrode 9j penetrates deeply in the depth direction, and the SiO ₂ film 2
It is very close to the lower supporting substrate 1j. Therefore, when forming the recess 7j by etching, if the etching is performed too deeply, the recess 7j reaches the support substrate 1j, so that the embedded gate electrode 9j also supports the support substrate 1j.
It comes into direct contact with j and becomes conductive.

Therefore, there arises a problem that the transistor does not operate normally at all. The present invention was created in view of the above problems of the conventional technique, and shortens the gate length of the buried gate electrode by suppressing the spread of the recess in which the buried gate electrode is to be buried, as compared with the related art. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can suppress the spread of the buried gate electrode in the depth direction to a necessary limit.

[0016]

To solve the above problems, firstly, as shown in FIGS. 3 to 9, a strip-shaped element forming layer 3 is selectively formed on an insulating film 2 formed on a supporting substrate 1. And a step of forming a groove 4 in the surface layer of the insulating film 2 on both sides of the element forming layer 3 sandwiching the element forming layer 3, and the groove 4 and the element forming layer 3
To form a first etching-resistant film 5, and the first etching-resistant film is formed in a partial region of the groove 4 on both sides, which is close to the element forming layer 3 side. 5 to form the opening 6; and to etch the insulating film 2 by introducing an etching solution from both of the openings 6 to form a recess 7 penetrating under the element forming layer 3. Removing the first etching resistant film 5 and then thermally oxidizing it to form a gate insulating film 8 on the surface of the device forming layer 3;
A step of forming a conductor film P1 that fills the recess 7 and covers the element forming layer 3, and selectively etches the conductor film P1 to form an upper portion of the recess 7 on the element forming layer 3. Forming a gate electrode 10 via the gate insulating film 8 and forming a buried gate electrode 9 in the recess 7 via the gate insulating film 8;
And a source region 11 and a drain region 12 are formed in the element forming layer 3 on both sides of the region below the gate electrode 10 which is to be the channel region layer C1, and a method for manufacturing a semiconductor device. Second, Fig. 10-Fig.
As shown in 13, the insulating film 2 formed on the supporting substrate 1a
a step of forming an element forming layer 3a having a narrow band-shaped area in the central area on a, and forming a second etching resistant film R2, and then sandwiching the central area of the element forming layer 3a. And forming an opening 4a of the second etching resistant film R2 on the insulating film 2a on both sides, and introducing an etching solution from the opening 4a on both sides to form the insulating film 2a.
Are etched to form a recess 7a penetrating under the element forming layer 3a, and after removing the second etching resistant film R2, the gate insulating film 8a is formed on the element forming layer 3a.
A step of forming on the surface, a step of growing a conductor film that fills the recess 7a and covers the element forming layer 3a, and a gate electrode 10a and a buried gate electrode by selectively etching the conductor film. 9a at the same time, and a step of forming a source region 11a and a drain region 12a in the device forming layers 3a on both sides of the region below the gate electrode 10a which will be the channel region layer C2. Thirdly, it is achieved by the method of manufacturing a semiconductor device, and thirdly, as shown in FIGS. 14 to 18, it is a surface layer of the insulating film 2b formed on the supporting substrate 1b and corresponds to a region where a gate electrode is to be formed. In the region, a step of forming a region layer F1 having a higher etching rate than the peripheral portion thereof, and a strip-shaped element forming layer 3b crossing over the region layer F1 having a higher etching rate. Selectively forming,
After forming the third etching resistant film R3 by covering the element forming layer 3b, the third etching resistant film R3 is formed on the region layer F1 having a large etching rate on both sides of the element forming layer 3b. The step of forming the opening 6b of the etching resistant film R3, and the etching of the insulating film 2b by introducing an etching solution from the openings 6b on both sides to form a recess 7b penetrating under the element forming layer 3b. A step of forming the gate insulating film 8b on the surface of the element forming layer 3b by thermal oxidation after removing the third etching resistant film R3; and filling the recess 7b and forming the element. Layer 3
b forming the conductor film P1 and selectively etching the conductor film P1 to form the gate insulating film 8b on the element forming layer 3b above the recess 7b.
Forming a gate electrode 10b via the gate insulating film 8b and forming a buried gate electrode 9b in the recess 7b via the gate insulating film 8b; and sandwiching a region to be a channel region layer C1 below the gate electrode 10b. And a step of forming the source region 11b and the drain region 12b in the element forming layers 3b on both sides of the semiconductor device manufacturing method.

[0017]

[Operation] According to the method for manufacturing a semiconductor device of the present invention, the etching resistant film 5 covering the grooves 4 formed in the insulating film 2 on both sides of the element forming layer 3 is formed, and the grooves 4 on both sides are formed. The opening 6 of the etching resistant film 5 is formed in a part of the element forming layer 3 side, and the etching liquid is introduced from both of the openings 6 to form a recess in the insulating film 2 to be connected under the element forming layer 3. Forming 7.

For this reason, the etching solution is prevented from penetrating in the depth direction to some extent, so that the etching solution can be concentratedly permeated toward the insulating film 2 below the element forming layer 3 through the opening 6. .

Therefore, since the insulating film 2 under the element forming layer 3 is intensively etched, the recess 7 penetrating under the element forming layer 3 is formed before the etching progresses in the gate length direction and the depth direction. Can be formed. Therefore, the buried gate electrode 9 formed in the recess 7 is also suppressed to the required size.

On the insulating film 2a formed on the support substrate 1a, a strip-shaped element forming layer 3a having a narrowed central region where a gate is to be formed is formed. Therefore, the insulating film 2a can be etched in a short time by introducing the etching liquid into the opening 4a, whereby the lower portion of the element forming layer 3a can be etched before the etching progresses in the gate length direction and the depth direction. It is possible to form a recess 7a penetrating therethrough. Therefore, it becomes possible to form the buried gate electrode 9a in which the gate length is shortened as compared with the conventional one, and the expansion in the depth direction is suppressed to a necessary limit.

Further, a region layer F1 having a high etching rate is formed in the region corresponding to the region where the gate electrode is to be formed on the surface layer of the insulating film 2b. Therefore, when the etching liquid is introduced from the openings 4b on both sides of the element forming layer, the insulating film 2b under the element forming layer 3a and under the region where the gate is to be formed is more than the insulating film 2b in other regions. Is also etched faster.

Therefore, the insulating film 2 under the region where the gate is to be formed is faster than the etching proceeds in the gate length direction.
Since the surface layer b is etched, the concave portion 7b can be penetrated under the element forming layer 3b before the concave portion 7b becomes so large.

Therefore, it becomes possible to form the buried gate electrode 9b in which the gate length is shortened to the required limit and the spread in the depth direction is suppressed to the required limit as compared with the conventional case.

[0024]

Embodiments of the present invention will now be described with reference to the drawings.
I will explain. (1) First Embodiment FIGS. 1 and 2 show a semiconductor device according to a first embodiment of the present invention.
It is a block diagram of. Note that FIG. 1A shows the upper surface of the semiconductor device.
It is a figure, and FIG.1 (b) is X of FIG.1 (a).₁─ Y ₁Line cross section
It is a figure. In addition, FIG. 2 shows X in FIG.₂─ Y₂Line cross section
Is.

In FIGS. 1A and 1B, 1 is a support substrate made of silicon, 2 is a film thickness of about 2 μm on the support substrate 1.
SiO ₂ film (insulating film), 3 has a thickness of 1000Å and a width of 1-2 μm
This is an element forming layer made of a strip-shaped silicon layer and serves as a channel region layer C1 in a substantially central region of the element forming layer 3. Reference numeral 8 is a thermal oxide film as a gate insulating film, 9 is a buried gate electrode embedded in the SiO ₂ film 2 below the channel region layer C1 via the gate insulating film 8, and 10 is above the channel region layer C1. A gate length of 0 formed through the gate insulating film 8.
Band-shaped gate electrodes of about 5 μm, 11 and 12 are sources / sources formed on the element forming layer 3 on both sides of the channel region layer C1.
Drain (S / D) region layer, 13 is an interlayer insulating film made of SiO ₂ covering the element formation layer 3, and 14 is the S / D region layer 1
Contact holes are formed in the interlayer insulating film 13 on the electrodes 1 and 12, and the distance from the gate electrode 10 is about 0.8 μm.

As described above, the field effect transistor having the gate electrodes 9 and 10 on both surfaces of the element forming layer 3 with the channel region layer C1 interposed therebetween is constituted. Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention, which is for producing the above-mentioned field effect transistor, will be described with reference to FIGS.

3 (a), 4 (a), 5 (a), 6 (a), and 7 (a) are top views, and FIG. 3 (b) is shown in FIG. 3 (a). A cross-sectional view taken along line X ₁ -Y ₁ , FIG.
Is X ₂ -Y ₂ line cross-sectional view of (a).

Further, FIG. 4 (b) shows X ₃ -Y of FIG. 4 (a).
_{3 is a} sectional view taken along line ₃ and FIG. 4C is a sectional view taken along line X ₄ -Y ₄ of FIG. Furthermore, X ₅ -Y in FIG. 5 (b) FIGS. 5 (a)
_{5 is a} sectional view taken along line 5 and FIG. 5C is a sectional view taken along line X ₆ -Y ₆ of FIG.

Further, FIG. 6B shows X ₇ -Y of FIG. 6A.
6 is a cross-sectional view taken along line ₇ and FIG. 6C is a cross-sectional view taken along line X ₈ -Y ₈ in FIG. Further, FIG. 7 (b) is X ₉ -Y of FIG. 7 (a).
_{9 is a} sectional view taken along the line ₉ and FIG. 8C is a sectional view taken along the line X ₁₀ -Y ₁₀ of FIG.

First, a support substrate 1 and a silicon substrate to be an element forming layer are formed by sandwiching the SiO ₂ film 2 therebetween, and then the silicon substrate is polished to form a thin layer having a film thickness of about 1000 Å. Then, by the photolithography method,
The thin layer is patterned to form a strip-shaped element forming layer 3.

Next, as shown in FIGS. 3 (a), 3 (b) and 3 (c), the surface portions of the SiO ₂ film 2 on both sides of the device forming layer 3 are sandwiched by RIE (Reactive Ion Etching: reactivity). The groove 4 into which the etching solution is introduced is formed by etching about 500 Å in the depth direction by ion etching).

Next, as shown in FIGS. 4 (a), 4 (b) and 4 (c), Si ₃ N ₄ having etching resistance against hydrofluoric acid is used.
A (silicon nitride) film (first etching resistant film) 5 is formed on the entire surface.
After forming about 300 Å, the opening 6 of the Si ₃ N ₄ film 5 is formed so as to expose the side wall on the element forming layer 3 side in the groove 4.

Here, a method of forming the opening 6 will be described with reference to FIG.
Will be described with reference to. FIG. 9 is a supplemental explanatory diagram of the process diagram (No. 2) of forming the semiconductor device according to the first embodiment of the present invention.

First, a positive type resist film R1 is applied on the upper surface of the Si ₃ N ₄ film 5 and selectively exposed by a mask,
By developing, as shown in FIG. 9A, patterning is performed so that a part of the groove 4 is exposed.

Next, as an etching solution for the Si ₃ N ₄ film 5,
A phosphoric acid (H ₃ PO ₄ ) solution is introduced from the exposed portion of the groove to etch the Si ₃ N ₄ film 5. Then, phosphoric acid solution penetrates the isotropically the Si ₃ N ₄ film 5, since the phosphoric acid solution does not only insignificant react with SiO ₂ film, Si ₃ N ₄ as shown in FIG. 9 (b)
Only part of the membrane 5 is removed.

Then, the resist film R1 is removed by a stripping solution. As a result, as shown in FIG.
Si on the side surface of the groove 4 on the element forming layer 3 side
The opening 6 of the ₃ N ₄ film 5 can be formed.

Next, as shown in FIG. 5, a hydrofluoric acid aqueous solution is introduced as an etching solution from the opening 4. Then Si
_{Since the 3} N ₄ film 5 has etching resistance against the hydrofluoric acid aqueous solution, the hydrofluoric acid penetrates into the SiO ₂ film 2 only through the opening 6.

As a result, the hydrofluoric acid aqueous solution becomes the element forming layer 3
First, the SiO ₂ film 2 under the element forming layer 3 is first etched. Therefore, the SiO ₂ film 2 under the element forming layer 3
Of the element formation layer 3 before the etching progresses in the gate length direction and the depth direction.
It is possible to form a recess 7 connecting below. Therefore, the embedded gate electrode 9 formed in the recess 7 is also suppressed to the required size.

Therefore, like the semiconductor device according to the conventional example shown in FIGS. 22 and 23, the recess 7 formed by etching is used.
However, it becomes sufficiently long in the gate length direction, and does not reach below the source / drain contact hole 14 when forming the buried gate electrode, and does not reach deep enough in the depth direction.

Next, after removing the remaining Si ₃ N ₄ film 5, a thermal oxide film 8 as a gate insulating film is formed on the surface of the element forming layer 3 by thermal oxidation to a thickness of about 100 Å. Furthermore,
As shown in FIG. 6, the recess 7 is filled and the element forming layer 3 is formed.
CVD of a polysilicon film P1 which is a conductor film for covering
About 2000Å is formed by the method.

Next, patterning with a resist is performed, and the RIE is performed by using the resist pattern as a mask.
The polysilicon film P1 is selectively etched. Thereby, the gate electrode 10 and the buried gate electrode 9 are simultaneously formed.

Next, using the gate electrode 10 as a mask,
By an ordinary ion implantation method, an acceleration voltage of 50 keV and a dose of 4 × 10 ^{15 are} applied to the element forming layer 3a on both sides of the channel region layer C2 below the gate electrode 10a in the element forming layer 3a.
Injecting As ⁺ at cm ⁻² , source region 11 and drain region
Forming twelve. Through the steps up to this point, a field effect transistor having a structure in which the channel region C1 is sandwiched between the gate electrode 10 and the buried gate electrode 9 via the thermal oxide film is formed.

Further, an interlayer insulating film 13 made of SiO ₂ or the like is formed on the entire upper surface thereof by a CVD method or the like to a thickness of about 5000 Å, patterned by a resist, and the interlayer insulating film 13 is selectively etched using the resist pattern as a mask. Thus, the contact holes 14 of the source region 11 and the drain region 12 are formed. (FIGS. 7 and 8) As a result, the buried gate electrode 9 having a gate length sufficiently shorter than the conventional one and the expansion in the depth direction is suppressed to a necessary limit is formed. It is possible to prevent the element formation layer 3 from becoming a channel and being brought into a conductive state when the electrode 9 reaches below the contact holes 14 of the source region 11 and the drain region 12. Therefore, even if the gate voltage is negative, the drain current does not flow and the pinch-off is performed.

It is also possible to prevent the embedded gate electrode 9 from directly contacting the supporting substrate 1. Therefore, the field effect transistor formed by the manufacturing method according to this embodiment operates perfectly normally.

(2) Second Embodiment FIGS. 10 to 13 are process diagrams of forming a semiconductor device according to a second embodiment of the present invention. 10 (a), 11 (a), and 12 (a) are top views, FIG. 10 (b) is a cross-sectional view taken along line X ₁ -Y ₁ of FIG. 10 (a), and FIG. 10 (c) is 10 is a sectional view taken along line X ₂ -Y ₂ of FIG.

[0046] Further, FIG. 11 (b) X ₃ -Y ₃ cross-sectional view taken along line of FIG. 11 (a), FIG. 11 (c) are X ₄ -Y ₄ line sectional view of FIG. 11 (a). Alternatively, FIG. 12 (b) Fig. 12 X ₅ -Y ₅ line cross-sectional view of (a), FIG. 13 is a X ₆ -Y ₆ line sectional view of FIG. 12 (a).

First, a supporting substrate 1a and a silicon substrate which will be an element forming layer are formed by sandwiching the SiO ₂ film 2a therebetween, and then the silicon substrate is polished to form a thin layer having a film thickness of about 1000Å. Then, the thin layer is patterned by the photolithography method to form the strip-shaped element forming layer 3a.

Next, as shown in FIGS. 10 (a), 10 (b) and 10 (c), a resist film (second etching resistant film) R2 is formed on the entire surface.
After that, the opening 21a of the resist film R2 is formed so as to expose the narrow central region of the element forming layer 3a and the SiO ₂ films 2a on both sides of the central region.
As a result, a pair of openings 4a for introducing the etching solution composed of the resist film R2 and the element formation layer 3a is formed in the opening 21a on both sides of the element formation layer 3a.

Then, a hydrofluoric acid aqueous solution is introduced as an etching solution through the opening 4a. Then, the element forming layer 3
Since the central portion of a is narrowed, the distance between the two openings 4a formed with the element forming layer 3a sandwiched therebetween is shorter than in the conventional case. Therefore, in FIGS. As shown, by introducing the hydrofluoric acid aqueous solution,
Element forming layer 3a in the central region where the two openings 4a are narrow
It is possible to form a recess 7a that penetrates through the lower part of the and has a minimum size necessary for forming the buried gate electrode 9a.

Next, after removing the resist film R2 with a stripping solution, a thermal oxide film 8a as a gate insulating film is formed on the surface of the element forming layer 3a by a thermal oxidation method to a thickness of about 100 Å.

Next, a polysilicon film as a conductor film is formed to a thickness of about 2000 Å by the CVD method to fill the recess 7a and cover the element forming layer 3a. Next, the resist film R2 is patterned, and the polysilicon film is selectively etched by RIE using the formed resist pattern as a mask to simultaneously form the gate electrode 10a and the buried gate electrode 9a.

Next, using the gate electrode 10a as a mask, an acceleration voltage of 50 keV and a dose of 4 × are applied to the element formation layers 3a on both sides of the channel region layer C2 by a normal ion implantation method.
As ⁺ is implanted at 10 ¹⁵ cm ^-2 to form S / D region layers 11a and 12a.
To form. As a result, a field effect transistor having a structure in which the channel region layer C2 is sandwiched between the gate electrode 10a and the buried gate electrode 9a is formed.

Next, an interlayer insulating film 13a made of SiO ₂ or the like is formed on the entire upper surface by a CVD method or the like to a thickness of about 5000 Å.
The resist film is patterned, and the contact hole 14a is formed by selectively etching the interlayer insulating film 13a on the S / D region layers 11a and 12a using the formed resist pattern as a mask (FIGS. 12 (a) and (a). b)).

As described above, according to the method of manufacturing the semiconductor device of the second embodiment of the present invention, it is possible to suppress the spread of the concave portion in the gate length direction as compared with the conventional method. Buried gate electrode 9a in contact hole 14a
By reaching the bottom, it is possible to prevent the element forming layer 3a from becoming a channel and becoming conductive. Therefore, even if the gate voltage is negative, the drain current does not flow, and the channel is pinched off.

Further, since the spread of the recess 7a in the depth direction can be suppressed to a necessary extent, it is possible to prevent the buried gate electrode 9a embedded in the recess 7a from directly contacting the supporting substrate 1a. You can Therefore, the field effect transistor formed by the manufacturing method according to this embodiment operates perfectly normally.

(3) Third Embodiment FIGS. 14 to 17 are process diagrams of forming a semiconductor device according to a third embodiment of the present invention. FIG. 14 (a), the FIG. 16 (a), the FIG. 17 (a) is a top view of the semiconductor device, X in FIG. 14 (b) Fig. 14 (a) ₀₀
Is -Y ₀₀ line cross-sectional view.

Further, FIG. 16 (b) shows X of FIG. 16 (a).₁-Y₁line
Sectional view, Figure 16 (c) is X of Figure 16 (a)₂-Y₂It is a line sectional view
It Furthermore, FIG. 17 (b) is the X of FIG. 17 (a).₃-Y₃Line cross section,
Figure 18 shows X in Figure 17 (a)_Four-Y _FourIt is a line sectional view.

Further, FIGS. 15 (a) to 15 (d) show X ₀₁ − of FIG. 14 (a).
A cross-sectional view taken along line Y ₀₁ shows an ion implantation step. First, Fig. 14
As shown in (a) and (b), the supporting substrate 1 made of silicon is used.
A SiO ₂ film (insulating film) 2b having a thickness of about 2 μm is formed on the
By depositing a polysilicon layer on the O ₂ film 2b by the CVD method and then patterning it, a Si region layer S1 as an introduction control layer having a thickness of about 0.1 to 0.3 μm is formed. The introduction control layer can be similarly formed by patterning after stacking the silicon layers by a bonding method or the like.

Details of this step are shown in FIGS. 15 (a) to 15 (c).
You That is, the acceleration voltage of 150
keV, dose 1 × 10¹⁵cm^-2With phosphorus (P⁺)I
Inject ON (FIG. 15 (b)). Then, the Si region layer S1
Unformed SiO₂P in membrane 2b⁺The more ions there are
Although it penetrates deeply (depth of about 0.3 μm), it is a Si region
SiO under the area where the layer S1 is formed₂Si region in film 2b
P by layer S1⁺Some penetration of ions into the depths is suppressed
P, because it is controlled⁺Ions are near the surface of the Si region layer S1
(Depth 0 to 0.2 μm). Diagonal lines in Figure 15 (b)
Area F1 is P ⁺The region where the ions are distributed is shown.
This region F1 is made of phosphorus glass, and other SiO₂Membrane 2b
The etching rate is higher than that of.

Next, after the Si region layer S1 is selectively removed by RIE (FIG. 15C), a silicon layer is formed on the SiO ₂ film 2b. Further, the element forming layer 3b is formed by the photolithography method. At this time, on the SiO ₂ film 2b
Positioning is performed so that the region where the gate of the element forming layer 3b is to be formed is exactly on the region where the Si region layer S1 was formed.

Next, after forming a resist film (third etching resistant film) R3 on the entire surface, a central region where the gate electrode of the element forming layer 3b is to be formed, and SiO on both sides sandwiching the central region. ₂ The opening 21b of the resist film R3 is formed so that the film 2b is exposed. As a result, a pair of openings 4b for introducing the etching solution composed of the resist film R3 and the element formation layer 3b is formed inside the opening 21b and on both sides of the element formation layer 3b.

Then, a hydrofluoric acid solution which is an etching solution is poured from the opening 4b to selectively etch the SiO ₂ film 2b. As a result, the hydrofluoric acid aqueous solution isotropically permeates into the SiO ₂ film 2b, and as shown in FIGS. 16 (a) to 16 (c),
A recess 7b penetrating the lower part of the element forming layer 3b is formed.
At this time, since the surface layer of the SiO ₂ film 2b below the element forming layer 3b in the central region where the gate electrode is to be formed has the region layer F1 having a high etching rate, the hydrofluoric acid which is an etching solution from the opening 4b. 16 is etched, the portion of the SiO ₂ film 2b below the region where the gate is formed is etched more rapidly and intensively than the other portions, resulting in FIG.
As shown in (a) to (c), it becomes possible to form the recess 7b which is not too large as compared with the conventional one and is sufficiently short in the gate length direction.

Then, after removing the resist film R3 with a stripping solution, a thermal oxide film 8b as a gate insulating film is formed on the surface of the element forming layer 3b by a thermal oxidation method to a thickness of about 100 Å. Next, a polysilicon film, which is a conductor film that fills the recess 7b and covers the element forming layer 3b, is grown to about 2000 Å by the CVD method. Next, the resist film R3 is patterned and selectively etched by RIE or the like using the formed resist pattern as a mask to simultaneously form the gate electrode 10b and the buried gate electrode 9b.

Then, using the gate electrode 10b as a mask,
Both sides of the channel region layer C3 are formed by an ordinary ion implantation method.
In the element forming layer 3b of, the acceleration voltage is 50 keV and the dose is 4
× 10 ¹⁵cm^-2With As⁺And S / D region layer 11
b, 12b are formed. Thereby, the channel region layer C3
Is sandwiched between the gate electrode 10b and the buried gate electrode 9b.
A field effect transistor having such a structure is formed.

Next, the interlayer insulating film 13 made of SiO ₂ or the like is formed on the entire surface.
b is formed to a thickness of about 1 μm by the CVD method or the like, and then the interlayer insulating film 13b on the S / D region layers 11b and 12b is selectively etched using the resist pattern formed on the interlayer insulating film 13b as a mask to form a contact hole. 14b is formed (FIGS. 17A and 17B).

As described above, according to the semiconductor device of the third embodiment of the present invention, it is possible to suppress the expansion of the concave portion 7b in the gate length direction as compared with the conventional case, and therefore, it is possible to embed it like the conventional case. When the gate electrode 9b reaches below the contact hole 14b, it is possible to prevent the element formation layer 3b from becoming a channel and being in a conductive state. Therefore,
Even if the gate voltage is negative, the drain current does not flow and the channel is pinched off.

Further, since the recess 7b can be prevented from spreading in the depth direction, it is possible to prevent the buried gate electrode 9b from coming into direct contact with the supporting substrate 1b. Therefore, the field effect transistor formed by the manufacturing method according to this embodiment operates perfectly normally.

[0068]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the recess 7 in the gate length direction or the depth direction is formed.
Since the expansion of b can be suppressed, the expansion of the buried gate electrode in the gate length direction and the depth direction can also be suppressed to a necessary limit.

Therefore, it is possible to prevent the element formation layer from becoming a channel and being in a conductive state due to the buried gate electrode reaching below the contact hole of the S / D electrode as in the conventional case. Therefore, it is possible to prevent the problem that the drain current flows when a negative voltage is applied to the gate electrode. Further, it becomes possible to prevent the problem that the buried gate electrode penetrates too much in the depth direction and short-circuits with the supporting substrate.

As described above, a normally operating transistor can be manufactured.

[Brief description of drawings]

FIG. 1 is a configuration diagram (part 1) of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram (No. 2) of the semiconductor device according to the first exemplary embodiment of the present invention.

FIG. 3 is a process diagram (part 1) of forming a semiconductor device according to the first embodiment of the invention.

FIG. 4 is a process diagram (No. 2) of forming the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a process diagram (No. 3) of forming the semiconductor device according to the first example of the invention.

FIG. 6 is a process diagram (4) of forming a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a process view (No. 5) of forming the semiconductor device according to the first example of the invention.

FIG. 8 is a forming process diagram (6) of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a supplementary explanatory diagram of the forming process of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a process diagram (1) of forming a semiconductor device according to a second embodiment of the invention.

FIG. 11 is a manufacturing process diagram (2) of the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a forming process diagram (3) of the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a forming process diagram (4) of the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a forming process diagram (1) of a semiconductor device according to a third embodiment of the present invention.

FIG. 15 is a forming process diagram (2) of the semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a forming process diagram (3) of the semiconductor device according to the third embodiment of the present invention.

FIG. 17 is a forming process diagram (4) of the semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a forming process diagram (5) of the semiconductor device according to the third embodiment of the present invention.

FIG. 19 is an explanatory diagram of a problem of the conventional example.

FIG. 20 is a process diagram (part 1) of forming a semiconductor device according to a conventional example.

FIG. 21 is a second manufacturing process diagram of the semiconductor device according to the conventional example.

FIG. 22 is a process chart (3) of forming a semiconductor device according to a conventional example.

FIG. 23 is a forming process diagram (4) of the semiconductor device according to the conventional example.

[Explanation of symbols]

1, 1a, 1b supporting substrate, 2, 2a, 2b SiO ₂ film (insulating film), 3, 3a, 3b element forming layer, 4, 4a, 4b, 6, 21a, 21b opening, 5 Si ₃ N ₄ film (First etching resistant film), 7, 7a, 7b Recessed portion, 8, 8a Thermal oxide film (gate insulating film), 9, 9a Buried gate electrode, 10, 10a Gate electrode, 11, 11a, 11b, 12, 12a, 12b S / D region layer, 13, 13a interlayer insulating film, 14, 14a contact hole, C1, C2 channel region layer, F1 region layer with high etching rate, P1 polysilicon film, R1 resist film, R2 resist film ( Second etching resistant film), R3 resist film (third etching resistant film), S1 SiC region layer (introduction control layer).

Claims (3)

[Claims] 1. A step of selectively forming an element forming layer (3) on an insulating film (2) formed on a supporting substrate (1), and both side portions sandwiching the element forming layer (3). The insulating film of (2)
Forming a groove (4) on the surface layer of the device, and forming a first etching resistant film (5) by covering the groove (4) and the device forming layer (3), and forming the groove (4) on both sides. )
Forming an opening (6) of the first etching resistant film (5) in a region that is a partial region of the first etching resistant film (3) side and is close to the element forming layer (3) side; An etching solution is introduced from (6) to etch the insulating film (2) to form the element forming layer (3).
A step of forming a recess (7) penetrating thereunder, and after removing the first etching resistant film (5), it is thermally oxidized to form a gate insulating film (8) on the surface of the device forming layer (3). And a step of forming a conductor film (P1) that fills the recess (7) and covers the element forming layer (3), and selectively etches the conductor film (P1). As a result, a gate electrode (10) is formed on the element forming layer (3) above the recess (7) via the gate insulating film (8), and the gate insulating film (10) is formed in the recess (7). 8) via which a buried gate electrode (9) is formed, and a channel region layer (C1) below the gate electrode (10).
A step of forming a source region (11) and a drain region (12) in the element forming layers (3) on both sides with the region to be formed therebetween being sandwiched therebetween. 2. A step of forming an element forming layer (3a) having a narrow region in a central region on an insulating film (2a) formed on a supporting substrate (1a), and a second etching resistance. Of the second etching resistant film (R2) on the insulating film (2a) on both sides of the element forming layer (3a) with the central region of the element forming layer (3a) interposed therebetween. 4a), and a recess (7a) penetrating under the element formation layer (3a) by introducing an etching solution from the openings (4a) on both sides to etch the insulating film (2a). Forming a gate insulating film (8a) on the surface of the element forming layer (3a) after removing the second etching resistant film (R2); and filling the recess (7a), And the element forming layer (3
a) growing a conductor film covering the gate electrode, simultaneously forming a gate electrode (10a) and a buried gate electrode (9a) by selectively etching the conductor film, and the gate electrode (10a ) Lower channel region layer (C
2) A step of forming a source region (11a) and a drain region (12a) in the element forming layers (3a) on both sides sandwiching the region to be a semiconductor device manufacturing method. 3. A surface layer of an insulating film (2b) formed on a supporting substrate (1b), which has a larger etching rate in a region corresponding to a region where a gate electrode is to be formed than in a peripheral portion thereof. Forming a region layer (F1), selectively forming an element forming layer (3b) across the region layer (F1) having a high etching rate, and covering the element forming layer (3b) Then, the third etching resistant film (R3) is formed, and then the third etching resistant film (R3) is formed on both sides of the element forming layer (3b) on the region layer (F1) having a large etching rate. Etching film (R
3) the step of forming the opening (6b), and etching the insulating film (2b) by introducing an etching solution through the openings (6b) on both sides, and under the element formation layer (3b). Forming a penetrating recess (7b); forming a gate insulating film (8b) on the surface of the device forming layer (3b) after removing the third etching resistant film (R3); Forming a conductor film (P1) which fills at least a part of the recess (7b) and covers the element forming layer (3b); and by selectively etching the conductor film (P1), A gate electrode (10b) on the device forming layer (3b) above the recess (7b) via the gate insulating film (8b).
And forming a buried gate electrode (9b) in the recess (7b) through the gate insulating film (8b), and a channel region layer (C below the gate electrode (10b)).
1) A step of forming a source region (11b) and a drain region (12b) in the element forming layers (3b) on both sides of the region to be the region, and a method of manufacturing a semiconductor device.