JPH0555467A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent malfunction of another circuit without an effect of variation of an input signal on Vcc and GND in a semiconductor device whose integrated circuit operates and stops by the input signal. CONSTITUTION:In a semiconductor device wherein an integrated circuit 7 operates by an input signal, a consumption current of the integrated circuit 7 is generated when the integrated circuit 7 is in a state of operation and the input signal affects Vcc and GND by a line resistance 8 at the time. Therefore, a consumption current of an entire of a circuit becomes constant, the input signal does not affect Vcc and GND, off-set and bias become constant and malfunction of another circuit is prevented by installing a dummy circuit 12 whose consumption current is equal to an absolute value of a consumption current of the integrated circuit 7 when the integrated circuit 7 is not in a state of operation and which operates in a reverse phase of a consumption current of the integrated circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a switch circuit for operating an integrated circuit according to an input signal.

[0002]

2. Description of the Related Art A conventional semiconductor device having a switch circuit for operating an integrated circuit by an input signal will be described below. FIG. 3 shows a semiconductor device having a conventional switch circuit. In FIG. 3, 1 is a _Vcc terminal, 2 is an input terminal, and 3 is a switch circuit. 4 is N of the switch circuit 3
It is a PN transistor, the base is connected to the input terminal 2, the collector is connected to the V _cc line through the resistor 5,
The emitter is connected to GND via the resistor 6. 7
Indicates that the transistor 1 is ON, that is, the switch circuit 3
It is an integrated circuit that operates in the operating state of. _{Reference numeral} 8 is a line resistance of the _Vcc line.

FIG. 4 is a specific operation timing chart for explaining the operation of FIG. In FIG. 4, 9 is the operation timing of the input signal applied to the input terminal 2, 10 is the operation timing of the consumption current (I _cc ) flowing through the switch circuit 3 and the integrated circuit 7, and 11 is the V _cc voltage after passing through the line resistor 8. The respective operation timings of are shown.

A semiconductor device having such a configuration will be described. First, a voltage at which the switch circuit 3 and the integrated circuit 7 operate is applied to the V _cc terminal 1. Next, as shown in FIG.
Input signal 9 is given. When the input signal 9 is in the low level state, the transistor 4 is cut off, the switch circuit 3 is cut off, and the integrated circuit 7 is stopped. Next, when the input signal 9 is in the high level state, the transistor 4 is activated, the switch circuit 3 is activated, and the integrated circuit 7 is activated. At this time, a consumption current 10 is generated, and the V _cc voltage 11 after passing through the line resistor 8 from the V _cc terminal 1 drops due to the line resistor 8 and becomes the state of the integrated circuit operating section by V _cc as shown in FIG. ..

[0005]

However, in the above-mentioned conventional configuration, the input signal 9 affects the V _cc voltage 11 as shown in the operation timing chart of FIG. 4 due to the consumption current 10 by the switch circuit 3 and the integrated circuit 7. Although not shown,
It also affects GND as well. Therefore, there is a problem that the input signal affects the offset and bias circuits and the malfunction of other circuits is likely to occur.

The present invention solves the above-mentioned conventional problem, and the current consumption of the circuit becomes constant regardless of the state of the input signal 9, and a semiconductor which can prevent the malfunction of other circuits due to the input signal 9 can be prevented. The purpose is to provide a device.

[0007]

In order to achieve this object, the semiconductor device of the present invention is provided with a dummy circuit which operates when the integrated circuit is stopped and consumes the same current as that of the integrated circuit. is there.

[0008]

With this configuration, since the current consumption of the circuit is the same regardless of the state of the input signal, V _cc and GND
The input signal does not affect the input signal and the offset and bias become constant, so that malfunction of other circuits can be prevented.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor device including a switch circuit in which an integrated circuit operates according to an input signal in one embodiment of the present invention.

In FIG. 1, 1 is a _Vcc terminal, 2 is an input terminal, and 3 is a switch circuit. 4 is N of the switch circuit 3
It is a PN transistor, the base is connected to the input terminal 2, the collector is connected to the V _cc line through the resistor 5,
The emitter is connected to GND via the resistor 6. 7
Indicates that the transistor 1 is ON, that is, the switch circuit 3
Is an integrated circuit that operates in the operating state. _{Reference numeral} 8 is a line resistance of the _Vcc line. These are the same as the conventional ones.

Reference numeral 12 is a dummy circuit. 13 is a dummy circuit 12
The NPN transistor of which the base is connected to the input terminal 2, the collector is connected to the V _cc line through the resistor 14, and the emitter is connected to the GND through the resistor 15. Reference numeral 16 is another NPN transistor of the dummy circuit 12, whose base is connected to the collector of the transistor 13 and whose collector is connected to the V _cc line through the resistor 17.
The emitter is connected to GND via the resistor 18. At this time, the constant in the dummy circuit 12 is set so that the current consumption of the dummy circuit 12 becomes equal to the absolute value of the current consumption of the integrated circuit 7.

FIG. 2 is a specific operation timing chart for explaining the operation of FIG. In FIG. 2, 9 indicates the operation timing of the input signal applied to the input terminal 2, and 10 indicates the operation timing of the consumption current (I _cc ) flowing through the switch circuit 3 and the integrated circuit 7, which is the same as the conventional one. 19 is a dummy circuit 12
The operation timing of the consumption current ( _ID ) flowing through the line, 20 is the operation timing of the V _cc voltage after passing through the line resistor 8, and 21 is the V
The operation timing when the switching noise of the input signal 9 is added to the _cc voltage 20 is shown.

The operation of the semiconductor device of this embodiment having the above structure will be described below. First, V _cc terminal 1
Is applied to the switch circuit 3, the integrated circuit 7, and the dummy circuit 12. Next, the input signal 9 of FIG.
give. When the input signal 9 is in the low level state, the transistor 4 is turned off, the switch circuit 3 is turned off, and the integrated circuit 7 is turned off. Similarly, when the input signal 9 is in the low level state, the transistor 13 is cut off, the transistor 16 is activated, and the dummy circuit 12 is activated. At this time, the consumption current 19 of the dummy circuit 13 is generated, and the V _cc voltage 20 after passing through the line resistor 8 from the V _cc terminal 1 causes a voltage drop due to the line resistor 8. Next, when the input signal 9 is in the high level state, the transistor 4 is activated, the switch circuit 3 is activated, and the integrated circuit 7 is activated. At this time, the consumption current 10 is generated, and the V _cc voltage 20 after passing through the line resistor 8 from the V _cc terminal causes a voltage drop due to the line resistor 8. Similarly, when the input signal 9 is in the high level state, the transistor 13 is in the operating state, so that the transistor 16 is in the cutoff state and the dummy circuit 12 is in the stop state.

As described above, according to the present embodiment, by installing the dummy circuit 12, the current consumption becomes constant regardless of the presence or absence of the input signal 9, and the V _cc voltage 20 is as shown in FIG. Become. As a result, the input signal 9 does not affect _Vcc and GND, and the offset and bias become constant, so that malfunction of other circuits can be prevented. However,
Although switching noise such as _Vcc voltage 21 in FIG. 2 may occur due to phase shift, switching noise can be removed by adding a relatively small capacitance because it is a narrow pulse. ..

In this embodiment, the dummy circuit 12 is replaced by the NPN.
Although it is composed of transistors, the dummy circuit has constant current consumption and constant value so that the current consumption of the dummy circuit is equal to the current consumption of the integrated circuit 7 in absolute value, synchronized with the input signal 9 and fluctuating in a phase opposite to the current consumption of the integrated circuit. Other circuits may be used if set to. Further, although the bipolar transistor is used in this embodiment, it goes without saying that a transistor such as MOS may be used.

[0016]

As described above, according to the present invention, by providing the dummy circuit, the fluctuation of the input signal can be reduced to _Vcc and GN.
It is possible to prevent malfunction of other circuits without affecting D. Further, it is possible to obtain the effect that the offset and the bias become constant and the circuit operation becomes stable.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of FIG.

FIG. 3 is a circuit diagram of a conventional semiconductor device.

FIG. 4 is an operation timing chart of FIG.

[Explanation of symbols]

1 V _cc terminal 2 input terminal 3 switch circuit 4, 13, 16 NPN transistor 7 integrated circuit 8 line resistance 12 dummy circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G06F 3/02 320 7313-5B H01L 27/06 H03K 17/16 G 9184-5J

Claims (1)

[Claims] 1. A switch circuit which operates an integrated circuit by an input signal, and a dummy circuit which operates when the integrated circuit is stopped and consumes the same current as the consumption current of the integrated circuit. A semiconductor device characterized in that it is configured so as not to affect the circuit of.