JPH0555265A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a fluctuation in a threshold value due to the storage of a Hall, which is generated by an avalanche multiplication, a reduction in a gain due to an increase in a nonlinear element or the like from being generated in a gallium-arsenic field-effect transistor. CONSTITUTION:A non-doped gallium-arsenic (GaAs) layer 2 (grown at 292 deg.C) grown by a molecular beam epitaxy method in such a way as to control a growth substrate temperature at 300 deg.C or lower and 200 deg.C or higher and a non-doped gallium-arsenic (GaAs) layer 7 grown by the molecular beam epitaxy method at a growth substrate temperature of 600 deg.C are grown on a semi- insulative substrate 1 in 500 to 1000 angstroms and after a channel (an Si-doped GaAs layer) 3 is formed on the layer 7, an annealing is performed at 800 deg.C for 25 minutes in an arsine atmosphere and a gallium-arsenic field-effect transistor is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a manufacturing method thereof, and more particularly to a field effect transistor in which a high electric field is concentrated such that avalanche multiplication occurs between a gate and a drain and a manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional field effect transistor using a compound semiconductor is non-doped gallium arsenide or non-doped aluminum gallium arsenide grown on a semi-insulating substrate at a substrate temperature of 600.degree. Those having Si ^28- doped gallium arsenide grown at the same temperature, or non-doped aluminum gallium arsenide and Si ^28- doped aluminum grown at the same temperature on the substrate at 600 ° C. There is a transistor in which gallium arsenide is formed and a channel is formed by 2DEG (two-dimensional electron gas), and in a case of using silicon, there is a transistor in which a channel is formed by growing silicon on an insulator. .

[0003]

In the conventional field effect transistor, when the gate-drain distance is, for example, about 0.5 μm, a voltage of 5 V is applied between the gate and the drain due to the reduction in size. , The electric field is 1 × 10 ⁵ V / cm
Therefore, avalanche multiplication occurs, holes generated by it are accumulated on the substrate side, change the threshold value of the transistor, and generate non-linear elements during large signal operation, lowering the transistor gain. There was a problem of making it happen.

[0004]

According to the present invention, non-doped gallium arsenide grown on a substrate by a molecular beam epitaxy method (hereinafter referred to as MBE) at a substrate temperature of 300 ° C. or lower and 200 ° C. or higher, and A non-doped gallium arsenide film having a thickness of 500 to 1000 angstroms grown at a substrate temperature of 600 ° C., and a channel layer formed on the undoped gallium arsenide film, and 800 ° C. in an arsine atmosphere at 25 ° C.
Then, a field-effect transistor in which source / drain / gate electrodes are formed and a method for manufacturing the same are obtained.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip according to an embodiment of the present invention. In manufacturing this chip, first, non-doped gallium arsenide 2 is grown on the semi-insulating substrate 1 by MBE while the substrate temperature is controlled at 292 ° C. Then, the substrate temperature is set to 600 ° C., non-doped gallium arsenide 7 is grown to 500 angstroms, and then S
Gallium arsenide 3 is grown while doping i ²⁸ .
Next, capless annealing is performed at 800 ° C. for 25 minutes in an arsine atmosphere. Finally, ohmic contacts are made to the gallium / arsenic to form drain / source electrodes 4 and 5, and a gate electrode 6 having a Schottky junction is formed at a position of 0.5 μm from each.

For high output operation, the source-drain voltage is set to 8V, the gate-source voltage is set to -1.5V, and a large signal operation is performed.
A voltage of 0 V is applied, and the gate-drain distance is 0.
Since it is 5 μm, the electric field reaches 2 + 10 ⁵ V / cm, and avalanche multiplication occurs. Some of the holes generated thereby flow into the gate electrode, but most of them diffuse to the side of the substrate having a low potential.

However, the gallium arsenide grown at 292 ° C. of the present invention has a high level of activation energy and a deep trap cross-section at a high concentration as shown in FIG. 2, and is occupied by electrons with a high probability. Therefore, it acts as a recombination center for holes generated out of thermal equilibrium. Therefore, the diffused holes are not accumulated and all disappear, so that the influence thereof does not appear at all. In addition, non-doped gallium arsenide 7
Since gallium arsenide grown at 292 ° C. has the effect of hindering the effect on the channel, the effect can be maintained even when high temperature annealing is required.

[0009]

As described above, according to the present invention, non-doped gallium arsenide grown at 300 ° C. or lower and 200 ° C. or higher is grown between the substrate and the channel layer, and 500 to 600 ° C. grown on the undoped gallium arsenide. By growing 1000 Å of undoped gallium arsenide, 2
While preventing the adverse effect of gallium arsenide grown at 00 ° C to 300 ° C on the channel, the holes generated by the avalanche multiplication between the gate and the drain are all recombined and disappeared without accumulating, so that the It has an effect of preventing the shift of the threshold value and the decrease of the gain due to the increase of the non-linear element.

[Brief description of drawings]

FIG. 1 is a sectional view of a chip according to an embodiment of the present invention.

[Explanation of symbols]

 1 Semi-insulating substrate 2 292 ° C. grown non-doped gallium arsenide 3 Si-doped gallium arsenide 4 Source electrode 5 Drain electrode 6 Gate electrode 7 600 ° C. grown non-doped gallium arsenide

Claims (2)

[Claims] 1. A molecular beam epitaxy method on a substrate,
Growth substrate temperature 300 ° C. or lower Non-doped gallium arsenide grown at 200 ° C. or higher, and growth substrate temperature 600
Undoped gallium arsenide having a thickness of 500 angstroms to 1000 angstroms grown at ℃, a channel layer formed thereon, a drain electrode and a source electrode having ohmic contact with the channel layer, and a current flowing through the channel layer And a gate electrode for controlling the temperature of 800 ° C. in an arsine atmosphere.
A field effect transistor characterized by being subjected to capless annealing at 900 ° C. for about 25 minutes. 2. A step of growing non-doped gallium arsenide on a semi-insulating substrate by a molecular beam epitaxy method at a growth substrate temperature of 200 ° C. or higher and 300 ° C. or lower, and a growth substrate temperature of 600 ° C. and a thickness of 500 Å. -10
A step of growing 00 angstrom non-doped gallium arsenide, a step of forming a channel layer thereon, a step of capless annealing at 800 ° C. to 900 ° C. in an arsine atmosphere, and a source electrode which makes ohmic contact with the channel layer. And a step of forming a drain electrode, and a step of forming a gate electrode for controlling a current flowing in the channel layer between the source electrode and the drain electrode, the method for manufacturing a field effect transistor.