JPH0554653A - Semiconductor device - Google Patents

Abstract

PURPOSE:To read with a high speed by using a signal line for read and a signal line for write in common and also using NMOS transistors in an amplifier circuit as MOS transistors in a read out circuit. CONSTITUTION:In the case of writing a low level VS in D and a high level VD in the inverse of D, IO is inverted from the high level to the low level and the inverse of IO is inverted from the low level to the high level by the circuit of a postrtage. Consequently, D is discharged to the low level IO by means of the MOS transistors M3, M5, and the inverse of D is charged from the high level the inverse of IO by means of the MOS transistors M4, M6. When the potential of D, the inverse of D varies, they are immediately amplified by the MOS transistors M1, M2 and an SAP circuit, and D is inverted to the low level VS and the inverse of D to the high level. At this time, as a word line W is a high level VW, the potential of D is writen in a memory cell MC. Thus, the differential voltage signal of D and the inverse of D can be read out with a high speed as a current differential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reduction in the number of read / write circuits and amplifier circuits connected to a data line of a dynamic memory and a reduction in occupied area.

[0002]

2. Description of the Related Art In order to speed up the access time of a conventional dynamic memory, I.E.E.Journal of Solid State Circuits, October 1990, pages 1102-1111 (IEEE Journal of so
lid-state Circuits October 1990, pp.1102-
1111) is known. The circuit is shown in FIG. The feature is that there is a read circuit RM. In the following description, complementary signals are represented by overlining the symbols in the drawings and / in the text in front of the symbols. Unless otherwise specified, a symbol representing a terminal name also serves as a wiring name and a signal name, and in the case of a power supply, also serves as its voltage value. Figure 8
, MC is a memory cell, W is a word line, D, / D
Is a data line, RA is a data line amplifier circuit, and PP, P
N is the drive signal. PCC is a precharge circuit, PC is its control signal, and HVD is a precharge voltage supply line. RM is a read circuit, and data lines D, /
Readout signal lines RO, / RO corresponding to the minute signal voltage difference of D
A small signal current difference is generated. YSR is a control signal of RM. WM is a write circuit, and WI and / WI are write signal lines. YSW is a WM control signal. Figure 9
Indicates the read operation of this DRAM. Of the signal levels shown in the figure, VS is the low-side power supply voltage V
C is the high potential of the peripheral circuit, VW is the high potential of the word line, VD
Is the high potential of the data line. First, the data lines D and / D are precharged to the voltage of HVD by the precharge circuit PCC, and then PC is set to the low level to make D and / D floating. Next, by setting the word line W to a high level, a read signal voltage is generated from the memory cell MC to the data line D. No memory cell is connected / D remains at HVD level. The column selection signal YSR is raised to a high level at the same time as the word line W, the read circuit RM is activated, and a current corresponding to the voltage difference between D and / D flows from RO and / RO toward VS. Although not shown in the figure, this minute current difference is amplified by the amplifier in the subsequent stage. Next, PP, PN
As a result, RA is activated and the voltage difference between D and / D is amplified. Next, writing will be described. For writing, when YSW is raised to a high level, D is pulled to a low level by WI, / D is charged to a high level by / WI, and the previous data is inverted. The amplification circuit RA further amplifies this change.

[0003]

FIG. 8 shows a read-only R
By adding M, high-speed reading is possible, but the number of elements increases accordingly. As a result, when the chip area is 1 megabit compared to the conventional common sensing method without RM,
Increase by about 5%. The challenge is to prevent this increase.

[0004]

In order to solve the above problems, the read signal lines RO and / RO and the write signal line W are provided.
Make I and / WI common. Further, the NM of the amplifier circuit RA
The number of constituent elements is reduced by using the OS transistor and the NMOS transistor of the read circuit RM as both transistors and operating them not only during the rewriting operation but also during the reading operation and the writing operation.

[0005]

With the number of constituent elements and the number of wirings reduced, the area is reduced, which in turn reduces the area of the DRAM chip.

[0006]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a diagram showing a first embodiment of the present invention. A DRAM amplifier circuit is taken as an example. MC is a memory cell, and when the word line W is selected, its information is output to D. D and / D are MOS transistors M1 to M6
Is an input / output terminal of the amplifying and reading / writing circuit, and F is its control signal. IO and / IO double as output terminals for reading and input terminals for writing,
YS is the control signal. PCC is a circuit that shorts D and / D and precharges to the same potential HVD.
Is a control signal thereof, and HVD is a power supply for precharge.
SAP is also a PMOS amplifier circuit having D and / D as input / output terminals, and its control signal is PP.

YS is a column selection signal which is the output of the Y decoder. The read operation of this embodiment will be described with reference to FIG. Initially, PC is at high level VC and D and / D are precharged to the voltage of HVD. In FIG. 1, IO,
The operation waveform of / IO has been described by converting the current difference into a voltage difference by the load resistance of the subsequent circuit. At this time F, W, Y
S and PP are low level VS voltages. The MOS transistors M3 to M6 are off. First, the PC changes from the high level VC to the low level VS, and D and / D become floating. Next, the word line W is at the low level V
When S goes to the high level VW, a signal is generated from MC to D and a differential voltage signal is generated at D and / D. YS is raised to a high level, the MOS transistors M5 and M6 are turned on, and the current difference according to the differential voltage signal of D and / D is IO and /.
Appears in IO. Although not explained here, IO, / IO
The current difference is captured and latched as a voltage difference by the circuit at the subsequent stage. Next, a rewriting operation is started, F becomes high level VC, M3 and M4 are turned on, and the same configuration as a normal sense amplifier which cross-connects M1 and M2, and a gate and a drain is obtained. As a result, the voltage difference between D and / D is amplified. When a relatively large signal voltage is generated, PP is changed from HVD to VD, and D and / D are amplified to high level VD and low level VS.

Next, the rewriting operation of the first embodiment will be described with reference to FIG. Word line W is at high level VW, Y
S becomes the high level VC, and the signal from the memory cell MC becomes D
Occurs on the I, D and / D differential voltage signal is generated, IO, / IO
A current difference corresponding to this appears. Next, PP and F become the high level VD, and the operation is the same as the read operation of FIG. 2 until the MOS transistors M1 and M2 and the SAP circuit amplify D and / D to the high level VD and the low level VS. Here, when writing a low level VS to D and a high level VD to / D, first, IO and / IO are
IO is inverted from high to low and / IO is inverted from low to high. As a result, D is discharged to a low level IO by the MOS transistors M3 and M5,
/ D is charged from high level / IO by MOS transistors M4 and M6. As soon as the potentials of D and / D fluctuate, they are amplified by the MOS transistors M1 and M2 and the SAP circuit so as to accelerate the change. D changes from high level VD to low level VS, and / D changes from low level VS to high level VD. Is reversed. At this time, since the word line W is at the high level VW, the potential of D is written in the memory cell MC. As described above, according to the present invention, even if the number of NMOS transistors is reduced by two from the conventional circuit of FIG. 8, the differential voltage signals of D and / D can be read at high speed as a current difference as in the conventional case. In addition, a common signal source of the MOS transistors M1 and M2 is a pulse signal in the related art, but the power source line VS is used, so that a wide signal line is not necessary. Further, by using IO and / IO that also serve as read output / write input, it is possible to reduce the number of wirings and the number of control signals by one, and the circuit area can be made smaller than before. Power supply voltages VC, VS, V used in FIGS.
Examples of D and VW have the following values. VC = 2.0V, VS
= 0V, VD = 1.5V, VW = 2.5V. Also,
As an example of the memory cell MC, a normal DRAM cell having one transistor and one capacitor, a two transistor, a twin cell having one capacitor, a special DRAM cell such as a gain cell having two transistors and three transistors, or a non-volatile cell using a dielectric, Or 4-transistor, 2-load resistance or 6-transistor SRAM cell or EEPRO
M nonvolatile cell etc. are mentioned.

FIG. 4 is a diagram showing a second embodiment of the present invention. W is a word line, D and / D are data lines, MC is a memory cell, PCC is a precharge circuit, PC is its control signal, NMOS transistors M1 to M6 are read / write amplifier circuits, YS is a read / write control signal, F is an amplification control signal. In the first embodiment of FIG. 1, the SAP control signal PP is abolished and the amplification of the data lines D and / D is controlled only by F. The operation will be described with reference to FIG. First, PC is at high level VC, and D and / D are precharged to HVD. F is a low level VS, I
O and / IO are HVD, and W and YS are low level VS. When PC becomes low level VS, D and / D become floating. Here, W becomes high level VW and YS becomes high level VC, a signal is generated from MC to D, and NMOS transistors M5 and M6 are turned on to set D and / D.
The voltage difference occurring in the
Signals are transmitted through O and / IO. Next, when F becomes high level VC, amplification is started by the PMOS transistor and the NMOS transistors M1 and M2 of the SAP circuit. As described above, according to the present embodiment, the differential voltage signals on the data lines D and / D can be read at high speed as a current difference similarly to the embodiment shown in FIG. 1, and the VD and VS of D and / D can be read. Since only one signal controls the amplification operation, the area of the circuit can be reduced as compared with the embodiment of FIG.
Further, it is possible to make the timings of the D and / D amplification operations the same.

FIG. 6 is a diagram showing a third embodiment of the present invention. MC and PCC are the same as those in the embodiment of FIGS. 1 and 2, but the control signal PP of the SAP circuit is abolished as in the embodiment of FIG. 2, and a PMOS transistor M7 is newly added to the common source of the PMOS transistors of the SAP circuit. Power supply line V
It is connected to D. F2 is an input terminal of the gate of the PMOS transistor M7. The PMOS transistor and the NMOS transistors M1 and M2 of the SAP circuit have the same configuration as the conventional circuit of FIG. 8, but the drains of M1 and M2 are connected through D, / D and the NMOS transistors M3 and M4. , F1 is the control signal. IO,
Similar to FIG. 1, / IO doubles as an output terminal for reading and an input terminal for writing, and YS is its control signal. This operation will be described with reference to FIG. First, PC is at high level VC, and D and / D are precharged to HVD. F1 is a low level VS, F2 is a high level VD,
W and YS are low level VS. When PC becomes low level VS, D and / D become floating. Where W
Becomes a high level VW, YS becomes a high level VC, a signal is generated from MC to D, and an NMOS transistor M
When M5 and M6 are turned on, the voltage difference generated at D and / D is transmitted as a current difference to the subsequent circuit through IO and / IO. Next, when F2 becomes low level VS and F becomes high level VC, amplification is started by the SAP circuit and the NMOS transistors M1 and M2. As described above, according to the present embodiment, the common source of the PMOS transistor of the SAP circuit in the conventional circuits of FIGS. 1, 2 and 8 is the pulse signal, and the power source line VD is set, whereby the NMOS transistors M1 and M2. As in the case where the power source line VS is used as the common source of, the wide signal line is not necessary. As a result, the area of the circuit can be reduced even when the control signal F2 of the PMOS transistor M7 and the control signal F2 are increased. In addition, the data line D,
In contrast to the conventional pulse signal amplification of / D,
In this embodiment, since the power supply VS and VD are used, it is possible to eliminate the influence of the wiring resistance and wiring capacitance of the signal wiring on the access time.

[0012]

According to the present invention, the number of constituent elements can be reduced by using the NMOS transistor of the amplifier circuit also as the MOS transistor of the read circuit. Further, by making the read signal line and the write signal line common, the number of wirings can be reduced. As a result, the area of the circuit can be reduced, so that a semiconductor device capable of reducing the area of the DRAM chip while achieving high-speed reading equivalent to the conventional one is realized.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a read operation of the first embodiment.

FIG. 3 is a diagram explaining a write operation of the first embodiment.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of the second embodiment.

FIG. 6 is a diagram showing a third embodiment of the present invention.

FIG. 7 is a diagram for explaining the operation of the third embodiment.

FIG. 8 shows a conventional example.

FIG. 9 is a diagram illustrating an operation of a conventional example.

[Explanation of symbols]

D, / D ... Amplification circuit input / output terminals, DRAM data lines, MC ... Input signal generating circuits, DRAM memory cells, VD ... I / O line amplified high level, VS ... I / O line amplified Low level, low potential power supply voltage, VC ... High potential power supply voltage, W ... Word line, VW ... Word line high level, PC
C ... Short circuit, precharge circuit, SAP ... PMOS amplifier circuit, RM ... Read switching transistor circuit, WM ... Write switching transistor circuit, P
C ... Short circuit, precharge circuit control signal, HVD ... I / O line precharge voltage, PP ... PMOS amplification circuit control signal, YSR ... RM control signal, YSW ... WM control signal, M1-M6 ... NMOS amplification circuit MOS transistors, F, F1, F2 ... Amplifier circuit control signal, YS
... Read / write circuit control signals, IO, / IO ... Read / write signal lines.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takayuki Kawahara 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Goro Tachikawa, 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoshiki Kawajiri 1-280, Higashi Koikekubo, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Yasushi Kawase 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (1)

[Claims] 1. In two MOS transistors M1 and M2 forming a differential amplifier circuit, a signal line pair D and / D to which a signal generating circuit is connected is connected to the gates of the two MOS transistors, A means for supplying the same potential VS to the two sources of the MOS transistor is provided, and the two M
First switch MOS transistors M3 and M4 are respectively provided between the drains of the OS transistors M1 and M2 and the signal line pair D and / D to which the signal generating circuit is connected, and the two MOS transistors M1 and M2 are provided. Of the second switch MOS between the drains a and b of the other and the other terminals IO and / IO, respectively.
A semiconductor device having transistors M5 and M6.