JPH03296989A - Dynamic type sense-amplifier - Google Patents

Abstract

PURPOSE:To enable a low voltage operation of sense-amplifier by providing a node line boosting part to boost through boosting capacitances for a coupling on the node line in the sense-amplifier, and changing a potential of the node line. CONSTITUTION:A node line boosting signal line Pu and the node line boosting part 5 having the boosting capacitances Cu with the linear electrical performance are provided in addition to the normal circuit dynamic type sense- amplifier 1. That is, by providing the node line boosting part to connect the node lines N0, N1 inside of the sense-amplifier 1 and the node line boosting signal line Pu respectively through two boosting capacitances Cu, the potentials of node lines N0, N1 are made high by a signal on the boosting signal line Pu. The operation is thereby enabled by the lower source voltage than in a conventional sense-amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic sense amplifier, and more particularly to a dynamic sense amplifier that operates at low voltage.

[Conventional technology]

FIG. 8 shows a circuit diagram of an example of a CMOS dynamic sense amplifier used in a semiconductor memory, and FIG. 9 shows waveforms of various signals to explain the operation of the circuit.

This is a conventionally well-known CMOS sense amplifier using an ordinary intermediate potential bit line precharge method, and it was published in the Proceedings of the 1989 International Solid State Device Circuits Conference (l5
SCC89Digest, Pp246-247).

As shown in FIG. 8, the dynamic sense amplifier IC has a switch section 2, a CMO8FF section 3, and a precharge section 4, which input signals from bit lines BO and Bl connected to a pair of memory cells MC. .

As shown in FIG. 9, bit line BO is activated during standby.

B1 is precharged to the intermediate level ■P of the high level ■CC.

When this circuit chip is accessed, first, at time to, the bit line precharge signal line PB is set to low level to put the bit lines BO and Bl in a floating state, and at the same time, at time t
1, the signal goes to a high level where, for example, the word line WO is selected as one of many word lines according to the external address.

As a result, the information stored in the memory cell MC is “0”.
" is read out to the bit line BO, and is read out to the node lines No and Nl of the sense amplifier IC via the transfer gate TG of the switch section 2.

In this way, bit lines BO, Bl and node line NO
, N is a P-type MOSFET TPO that amplifies the minute difference signal read out onto a large amplitude signal.

TPI flip-flop 3P and N type MO3FETTN
CMO composed of Flip Flora 13N of O, TNI
This is a dynamic sense amplifier IC having an 8FF section 3.

This sense amplifier IC is a flip-flop 3P and 3N
The operation is controlled by signals on the latch signal lines SAP and SAN, which are connected to the latch signal lines SAP and SAN, respectively.

Furthermore, by setting the transfer gate signal line TG to a low level at time t2 before the operation of the sense amplifier IC, bit & IBO, Bl and the node lines No, N of the sense amplifier IC
1, that is, the bit line capacitance CB and the node line capacitance CN within the sense amplifier are separated by the switch section 2, thereby reducing the effective load capacitance of the sense amplifier IC and achieving high performance of the sense amplifier.

The latch signal lines SAP and SAN change in level from time t4, respectively, from an intermediate level P to a high level CC stored in the memory cell capacitor C8 and a low level (ground potential). The minute difference signal between lines No. and Nl is amplified to vCC and ground potential.

After this, from time t5, the transfer gate signal line TG is returned to a high level, and the node lines NO, N are amplified to a large amplitude.
Signals vcc and o on the bit lines BO and Bl are written to the bit lines BO and Bl and the memory cell MC, respectively.

When this circuit chip becomes unselected, the selected word line WO is changed to low level from time t7, and the bit line precharge signal line PB begins to return to high level from time t8, and the bit line which is at vCC and ground potential is changed to low level from time t7. BO, BL
and precharges the node lines No and Nl to intermediate level ■P.

This intermediate level VP is normally set to half the high level and low level written into the memory cell. Therefore, in this example, VP=VCC/2.

[Problem to be solved by the invention]

In the conventional dynamic sense amplifier as described above, when the power supply voltage, that is, the write high level vCC to the memory cell becomes low, the precharge level VP of the bit line decreases.
will also be proportionately lower.

For this reason, when lowering the power supply voltage, the operating speed of the sense amplifier becomes slower, the S/N ratio worsens, and the normal operation margin becomes extremely small. There was a very serious problem.

An object of the present invention is to provide a dynamic sense amplifier suitable for lowering the power supply voltage.

[Means to solve the problem]

The dynamic sense amplifier of the present invention reads a minute signal from a memory cell to a pair of bit lines to which a plurality of dynamic semiconductor memory cells are connected.
In a dynamic sense amplifier using an intermediate level bit line precharging method, which inputs a signal to a complementary input signal line through a switch section having a transfer gate and amplifies it to a large amplitude signal, a node is connected to the complementary input signal line through a boost capacitor, respectively. It is configured by adding a node line boosting section that connects the line boosting line.

Further, the dynamic sense amplifier of the present invention has a nonlinear boosting capacitance.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a waveform diagram of signals of various parts shown to explain the operation of the circuit of FIG. 1.

In this embodiment, the same symbols are used for the same parts as the conventional dynamic sense amplifier and memory cell shown in FIG. 8, but in addition to the conventional circuit dynamic sense amplifier, the node line The difference is that a node line boosting section 5 having a signal line Pu and a boosting capacitance Cu whose electric characteristics are linear is provided.

As in the conventional example, consider the case where memory cell MC is selected.

First, the bit line precharge signal line is set to a low level at time to, the word line WO is selected at time t1, a minute signal is read out from the memory cell MC to the bit line BO, and at the same time, the transfer gate TG of the switch section 2 is activated. A minute signal is also transmitted to the node line ND via the node line ND.

Then, in order to disconnect the bit line capacitance CB from the sense amplifier, the transfer gate signal line TG is set to a low level at time t2. Up to this point, the operation is similar to that of the conventional sense amplifier IC.

Next, from time t3, the node line boost signal line Pu of the node line booster 5 is started at a high level.

At this time, the level of the node line N09N1 is boosted via the boost capacitor Cu.

That is, if the parasitic capacitance of the node lines No and Nl is CN, the precharge level is vP, and the boost amplitude of the node line boosted signal line Pu is Vu, then the level of the node line N1 after boosting is V.
PI is shown in equation (1), where Cu=CN, Vu=
Assuming VCC, VP=VCC/2, VPI is ■CC
is equal to

This means that the sense amplifier 1 of the present invention requires only △vP of the voltage applied to the node line of the sense amplifier when considering the same supply voltage VCC than the conventional sense amplifier IC using the intermediate potential precharge method. This indicates that the power supply voltage can be lowered even further.

The operation after time t4 is similar to the conventional example except that the node line boosted signal line Pu is set to a low level from time t7.

The timing for setting the node line boosted signal line Pu to a low level may be any time after the sense amplification operation of the sense amplifier ends until the time point t8 when the precharging of the bit line ends.

As described above, this embodiment has a node line boosting section that connects the node lines No, Nl inside the sense amplifier 1 and the node line boosted signal line Pu via two boosting capacitors Cu, and has a boosted signal 1iPu. The above signal connects node lines No. and N.
By increasing the potential of l, it is possible to operate at a lower power supply voltage than the conventional sense amplifier. In other words, it is excellent as a low voltage sense amplifier.

FIG. 3 is a circuit diagram of a dynamic sense amplifier showing a second embodiment of the present invention, and FIG. 4 is a waveform diagram of signals at various parts of the third circuit.

The sense amplifier 1a of this embodiment differs from the embodiment shown in FIG. 1 in that a nonlinear capacitance Cua is used as a coupling boost capacitor.

Other parts and driving procedures are the same as in the first embodiment shown in FIGS. 1 and 2.

The term "nonlinear capacitance" as used herein refers to a device whose capacitance value existing between two electrodes changes depending on the magnitude of the voltage between the two electrodes, such as a MOS capacitor.

Here, the relationship between the applied voltage Vi and the capacitance value Ci is Ci
The following explanation will be given assuming that =AV i.

As explained in the above embodiment, the word mwo is selected, and the information stored in the memory cell MC (here, "0" is processed) is read onto the bit line BO, and the transfer gate signal line TG of the switch section 2 is set low. After setting the node line to the high level, the node line boost signal line Pi is set to the high level. At this time, the potentials of the node lines No and Nl are their respective initial potentials (VP-Δ■1
).

It increases in proportion to vp.

This is because the size (capacitance value) of the boosting capacitor Cua changes in proportion to the voltage between its two electrodes.

Therefore, the potential difference between the node lines No and Nl after boosting, that is, the difference signal Δ■2, is larger than the initial value ΔV1, which means that the signal has been amplified.

This indicates that the S/N ratio of the sense amplifier 1a is improved, resulting in stable operation, and that its operating margin is also increased.

The operation after time t5 is similar to that of the first embodiment shown in FIG.

As described above, in this embodiment, the boosting capacitance of the node line boosting unit 5a connected to the node lines No, Nl of the sense amplifier la is made into a non-linear capacitance, and the signal on the boosting signal line Pu is applied to the node lines No, Nl. By increasing the potential of the node line, it is possible to amplify the difference signal between the node lines No. and N1, making it possible to operate at a lower power supply voltage than conventional sense amplifiers, and reducing the normal operation margin of the sense amplifier. It is also possible to increase

FIG. 5 is a circuit diagram of a dynamic sense amplifier showing a third embodiment of the present invention, and FIG. 6 is a waveform diagram of signals at various parts in FIG.

The dynamic sense amplifier 1b of this embodiment is different from the embodiment shown in FIG. It is a point.

By doing this, the parasitic capacitance CNa of the node lines No and Nl inside the sense amplifier 1b is reduced to
~ Since the capacitance CN of the second embodiment is smaller, the boosting capacitance Cu can be made smaller by that amount.

That is, it is possible to downsize the circuit.

However, the signal generation on the latch signal line SAP for the P-type MOSFET of the flip-flop 3P starts the transfer gate signal line TG at a high level from time t5, and the amplified signal on the node lines No and Nl is generated at the time t2. This is performed after the bit lines BO and Bl are written from 1 to 3, and has the effect of raising the potential of the high-level bit line to the CC level.

FIG. 7 is a waveform diagram of signals at various parts in FIG. 1 for explaining the operation of the fourth embodiment of the present invention.

This embodiment differs from the embodiment shown in FIG. 1 in that the polarity of the boosted signal on the node line boosted signal line Pua supplied to the same circuit is changed.

That is, in other embodiments, the transfer gate signal line T
After making G low level from time t2, the boost signal line Pu
The node line N begins to change to a high level from time t3.
Whereas the potentials of node lines No and Nl were made high, in this embodiment, the boosted signal line Pua is set to a low level from time t3 to lower the potentials of node lines No and Nl.

By doing this, the effect obtained is the same as that of the embodiment shown in FIG. 1, but it is also possible to make the boost signal on the boost line Pua the same as the signal on the transfer gate signal line TG, and the type of signal can be changed. can be reduced.

Further, it is also possible to arrange the boost capacitor Cu near the transfer gate signal line TG and to combine the signal line TG and the boost signal line Pua into one.

〔Effect of the invention〕

The dynamic sense amplifier of the present invention enables low-voltage operation of the sense amplifier by providing a node line booster that boosts the voltage on the node line in the sense amplifier via a boosting capacitor for coupling and changing the potential of the node line. can be made possible.

Further, by making the characteristics of the coupling boost capacitor non-linear, the minute difference signal taken into the sense amplifier can be amplified by the coupling operation, which has the effect of improving the S/N of the sense amplifier.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the first embodiment of the present invention, FIG. 2 is a waveform diagram of various signals shown to explain the operation of the circuit in FIG. 1, and FIGS. 3 and 5 are respectively Circuit diagrams showing the second and third embodiments of the present invention, and FIGS. 4 and 6 are waveform diagrams of signals of various parts shown to explain the operation of the circuits shown in FIGS. 3 and 5, respectively. , FIG. 7 is a waveform diagram of various signals in FIG. 1 for explaining the operation of the fourth embodiment of the present invention, FIG. 8 is a circuit diagram of an example of a conventional dynamic sense amplifier, and FIG. 9 is a waveform diagram of signals of various parts shown for explaining the operation of the circuit of FIG. 8. FIG. 1, la, lb...dynamic sense amplifier, 2
...Switch section, 3...CMOSFF section, 3P...
・PMO3FF section, 3N...NMOSFF section, 4...
・Precharge section, 5... Node line boost section, BO, B
1... Bit line, CB, CBa... Parasitic capacitance, WO
lWl...word line, MC...memory cell, LO,
Ll... Complementary input signal line, Cu, Cua... Boosting capacitor, PB... Bit line precharge signal line, Pu, P
ua...Node line boosted signal line, VP...Power supply voltage for bit line precharge, vCC...High level voltage of the bit line, TG...Transfer gate.

Claims (1)

[Claims] 1. A minute signal from a memory cell read out to a pair of bit lines to which a plurality of dynamic semiconductor memory cells are connected is transferred to a complementary input signal line through a switch section having a transfer gate. In a dynamic sense amplifier using an intermediate level bit line precharging method which inputs a signal to a signal and amplifies it to a large amplitude signal, a node line boosting section is added to each of the complementary input signal lines to connect a node line boosting line via a boosting capacitor. A dynamic sense amplifier characterized by: 2. The dynamic sense amplifier according to claim 1, wherein the node line booster includes a nonlinear capacitance having a nonlinear value with respect to an applied voltage.