JP2003168294A - Drive method for sense amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive method for a sense amplifier by which amplification speed being almost same as the case in which a transfer gate is a non- conduction state can be realized and occurrence of noise can be suppressed largely. <P>SOLUTION: Before a control signal SEP1 and SEN of a sense amplifier are made respectively GND and VCL and amplification is started, the prescribed voltage VTG is supplied as a control signal of a transfer gate. The prescribed voltage VTG is set so that bit line potential difference after amplification is assumed to VDL and voltage of the control signal when a current of 1 μm is made to flow in a transistor used in the transfer gate is assumed to VT and 1/5×VDL+VT≤VTG≤1/2×VDL+VT is satisfied. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a sense amplifier in a DRAM, and more particularly to a method of driving a sense amplifier capable of significantly reducing noise without lowering the operating speed.

[0002]

2. Description of the Related Art Some DRAMs have a transfer gate (TG) provided on a bit line for the purpose of speeding up the amplification operation of a sense amplifier. This transfer gate temporarily electrically disconnects a part of the bit line (the part to which the memory cell, the precharge circuit, etc. are connected) from the sense amplifier when the sense amplifier performs an amplifying operation (or The current flowing through the sensor is limited) and the load on the sense amplifier is reduced to realize high-speed amplification operation.

A method of driving the sense amplifier while controlling the transfer gate in this way is called a TG clocking method, and is described in, for example, Japanese Patent Application Laid-Open No. 3-283183 and Japanese Patent Application Laid-Open No. 4-321994. Has been done.

The read and restore (refresh) operations of the DRAM using the conventional sense amplifier driving method based on the TG clocking method will be described below with reference to FIGS. 11 and 12.

First, referring to FIG. 11, a conventional DRAM
The configuration of will be described.

Generally, a DRAM has a large number of memory cells arranged in rows and columns and corresponding sense amplifiers. FIG. 11 shows one of the memory cells and the corresponding sense amplifier. However, the one in FIG.
A bit line pair BLT0 and BLN0 (only one bit line is connected) to which a large number of memory cells are connected (left side in the figure, hereinafter referred to as a left side bit line (pair)) and a large number of memory cells (not shown) are also connected. The bit line pair BLT1 and BLN1 (right side in the figure, hereinafter referred to as right side bit line (pair)) is a type in which one sense amplifier is shared by two pairs of bit lines.

In FIG. 11, the sense amplifier 101 is
N-channel flip-flop 102 composed of a pair of N-channel MOS transistors, and a pair of P-channel MOS
P-channel flip-flop 10 composed of a transistor
3 and 3. The sense amplifier 101 is connected between the pair of bit lines 104 and 105. The N-channel flip-flop 102 includes an N-channel MOS transistor and is controlled by the control signal SEN to supply the ground potential GND.
06 is connected. The P-channel flip-flop 103 includes a pair of P-channel MOS transistors and a VDL stabilizing capacitor, supplies the high-voltage operating potential VOD to the P-channel flip-flop under the control of the first control signal SEP1. A drive potential supply circuit 107 that is controlled by the second control signal SEP2 and applies the array portion potential VDL is connected.

The high voltage operating potential VOD is a potential boosted from a power supply voltage VCC supplied from the outside.
The array portion potential VDL gives the data "H" level of the memory cell, and is a potential equal to or stepped down from the power supply voltage VCC supplied from the outside.

Further, in the following description, the peripheral operating potential VCL operates peripheral circuits such as the timing generating circuit. The boosted potential VPP is a potential boosted from the power supply voltage VCC supplied from the outside.

The bit lines 104 and 105 are the above-mentioned left bit line pair BLT0 and BLN0 and right bit line pair BLT.
1, BLN1 and a portion located between them and connected to the sense amplifier (hereinafter referred to as sense amplifier section bit line (pair) BLT, BLN). Left bit line pair BLT0, BLN0 and sense amplifier section bit line pair BL
Between T and BLN, and right bit line pair BLT1 and BL
N1 and the sense amplifier section bit line pair BLT and BLN are connected via transfer gates 108 and 113 each consisting of a pair of N channel MOS transistors.

The sense amplifier bit lines BLT and BLN have a pair of data buses 1 on the right side of the sense amplifier 101.
A column gate 112 composed of a pair of N-channel MOS transistors connected to 11 is connected. The bit lines 104 and 105 connect between a large number of memory cells connected thereto and the data bus 111, and are used for writing / reading a data signal to / from the memory cells.

Further, the bit line pair BLT0 and BLN0 includes a precharge circuit 109 composed of three N-channel MOS transistors, and a large number of memory cells each composed of an N-channel MOS transistor and a capacitor (only the memory cell 110 is shown). It is connected.

A precharge circuit 114 and a large number of memory cells (not shown) are connected to the bit line pair BLT1 and BLN1. As described above, the transfer gate 113 and the precharge circuit 114 are for sharing the sense amplifier 101 and the column gate 112 in the left and right bit line pairs.

A method of driving the sense amplifier 101 will be described below with reference to FIG. 12 in addition to FIG.

First, in the initial state, the precharge circuit 1
09, 114 control signals PDLL, PDLR, and transfer gates 108, 113 control signals TGL, T
Since both GR are equal to the boosted potential VPP, bit line 1
The potentials of 04 and 105 are equal to 1/2 × VDL over the entire line.

In this state, when the control signal PDLL of the precharge circuit 109 and the control signal TGR of the transfer gate 113 are made equal to the ground potential GND and the word line WL is selected (equal to the boosted potential VPP), the transfer gate 113 becomes On the left side, the memory cell 110
Left bit line pair BLT according to the data written in
0, BLN0 and the sense amplifier section bit line pair BLT,
A potential difference occurs between BLN. Here, FIG. 12 shows a case where a low potential is written in the memory cell 110, and in this case, the potentials of the left side bit line BLT0 and the sense amplifier section bit line BLT are slightly lowered.

Next, the sense amplifier 101 is driven to amplify the potential difference between the bit lines 104 and 105 (more accurately, between the sense amplifier section bit lines BLT and BLN). At that time, the transfer gate 108 is controlled. The signal is once made equal to the ground potential GND. That is, after making the control signal of the transfer gate 108 equal to the ground potential GND, the first control signal SEP1 of the drive potential supply circuit 107 is obtained.
Are made equal to the ground potential GND, and at the same time, the control signal SEN of the ground potential supply circuit 106 is made equal to the peripheral operation potential VCL. As a result, the sense amplifier 101 is electrically disconnected from the left bit lines BLT0 and BLN0 (and the memory cell 110 and the precharge circuit 109), and the potential of the sense amplifier section bit line BLN is changed to the high voltage operating potential VO in a short time.
D and the potential of the sense amplifier section bit line BLT can be made equal to the ground potential GND, respectively.

Thereafter, the first of the drive potential supply circuit 107
The control signal SEP1 is returned to the high voltage operating potential VOD, and the second control signal SEP2 is made equal to the ground potential GND. Further, the control signal TGL of the transfer gate 108 is returned to the boosted potential VPP. As a result, the potential of the sense amplifier section bit line BLN once falls so as to become equal to the potential of the left side bit line BLN0, and then rises together with the potential of the left side bit line BLN0 until it becomes equal to the array section potential VDL. In addition, the sense amplifier section bit line BL
The potential of T rises so as to be equal to the potential of the left bit line BLT0, and then falls together with the potential of the left bit line BLT0 until it becomes equal to the ground potential GND. As a result, the memory cell 110 is supplied with the potential amplified by the sense amplifier 101, and the rewrite operation is performed. Then, during this period, if the control signal YSW of the column gate 112 is made equal to the boosted potential VPP, the potential amplified by the sense amplifier 101 can be output (that is, read) to the data bus 111.

After that, the potential of the word line WL is set to the ground potential G.
It is made equal to ND and the selection of the memory cell 110 is completed.
Then, the second control signal SE of the drive potential supply circuit 107
P2 is returned to the high voltage operating potential VOD, and the control signal SEN of the ground potential supply circuit 106 is returned to the ground potential GND. After that, the control signal PDLL of the precharge circuit 109 is made equal to the boosted potential VPP, and the transfer gate 113
By making the control signal TGR of (1) equal to the boosted potential VPP, the potentials of the bit lines 104 and 105 are set to ½ × VDL over all the lines, and the potential (intermediate level) is maintained.

Next, another conventional sense amplifier driving method will be described with reference to FIG.

The method according to the time chart of FIG. 13 is basically the same as the method according to the time chart of FIG. 12 described above. However, when the sense amplifier 101 is driven, the control signal TGL of the transfer gate 108 is not set to the ground potential GND but is set to be equal to the array portion potential VDL.

Control signal T of transfer gate 108
When GL is made equal to the array portion potential VDL, the transfer gate 1 provided on the high potential side bit line 105
The N-channel transistor of No. 08 becomes substantially non-conductive, and the potential of the sense amplifier section bit line BLN is amplified as in the case shown in FIG. On the other hand, N of the transfer gate 108 provided in the bit line 104 on the low potential side
The channel transistor becomes slightly conductive,
The potential of the sense amplifier section bit line BLT is slightly delayed in amplification as compared with the case of FIG. Instead,
Compared to the case of 2, the potential increase in the sense amplifier section bit line BLT on the low potential side when the control signal TGL of the transfer gate 108 is returned to the boosted potential VPP is small,
No big noise is generated.

As described above, in the method according to the time chart of FIG. 13, compared with the method according to the time chart of FIG. 12, the amplification operation of the sense amplifier is slightly delayed, but noise can be reduced.

[0024]

In the conventional method in which the control signal to the transfer gate is set to the ground potential GND, when the control signal is returned to the boosted potential VPP,
There is a problem in that a large amount of noise is generated in the sense amplifier node and a read malfunction may occur.

Further, in the conventional method in which the control signal to the transfer gate is set to the array portion potential VDL, there is a problem that the amplification on the low level side is delayed because the initial sense operation current is large.

Therefore, the present invention can realize an amplification speed almost the same as when the transfer gate is made non-conductive,
Moreover, it is an object of the present invention to provide a driving method of a sense amplifier that can significantly suppress the generation of noise.

[0027]

According to the present invention, a memory cell, a pair of bit lines for writing / reading information to / from the memory cell, and the bit connected between the pair of bit lines are provided. A sense amplifier for amplifying a potential difference between the lines; and a transfer gate formed of a transistor provided on each of the pair of bit lines for electrically separating the sense amplifier from a part of the bit line. In a method of driving a sense amplifier applied to a provided memory circuit, a voltage between a logic high level (VPP) and a logic low level (GND) as a control signal of the transfer gate at the start of driving the sense amplifier, , Turn off the transistor provided on the high potential side bit line of the transistors forming the transfer gate And a predetermined voltage VTG that is set to slightly turn on the transistor provided on the bit line on the low potential side is supplied, and after a predetermined time elapses, the control signal is changed from the predetermined voltage VTG to the logical high level. A method for driving a sense amplifier, which is characterized in that the level (VPP) is changed, can be obtained.

Specifically, the amplification factor on the low potential side of the sense amplifier after the control signal is changed from the predetermined voltage VTG to the logic high level (VPP) is maintained at 60% or more. The predetermined voltage VTG is determined.

More specifically, when the transfer gate applies the voltage VT as the control signal, the transfer gate is 1 μm.
The sense amplifier has an input / output characteristic of allowing a current of A to flow, and the sense amplifier detects the potential difference between the pair of bit lines as the array voltage VDL.
When amplifying to be equal to (<“logical high level”), the predetermined voltage VTG is ⅕ × VDL +
It is within the range of VT ≦ VTG ≦ ½ × VDL + VT.

Further, in the above method of driving the sense amplifier, at the start of driving the sense amplifier, a voltage higher than the ground potential GND and lower than the predetermined voltage VTG is once supplied as a control signal for the transfer gate. Alternatively, the predetermined voltage VTG may be supplied.

Further, according to the present invention, the predetermined voltage V
A sense amplifier used in the method for driving the sense amplifier, comprising: a VTG voltage generation circuit for generating TG; and a selection circuit for selecting the output of the VTG voltage generation circuit and the logic high level (VPP). A drive circuit is obtained.

Further, according to the present invention, a first transistor for determining whether to supply the logic high level (VPP) to the transfer gate, and the first transistor.
A second transistor for setting the voltage supplied to the transfer gate to the predetermined voltage VTG when the transistor of FIG. 2 changes from on to off, and the logic low level (GND) to the transfer gate. A drive circuit for a sense amplifier used in the above method for driving a sense amplifier, characterized in that the drive circuit includes a third transistor for determining whether or not it is present.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following explanation,
It is assumed that the DRAM has the same configuration as that of the conventional one shown in FIG.

FIG. 1 shows a time chart of the driving method of the sense amplifier according to the first embodiment of the present invention.

As shown in FIG. 1, in the initial state,
Control signals PDLL for the precharge circuits 109 and 114,
The control signals TGL and TGR of the PDLR and transfer gates 108 and 113 are all equal to the boosted potential VPP. At this time, the potential (= 1/2 × VDL) supplied to the precharge circuits 109 and 114 is the bit line 10.
4 and 105, the bit line 104,
The potential of 105 is equal to the potential ½ × VDL over the entire line.

In this state, the control signal PDLL of the precharge circuit 109 and the control signal TGR of the transfer gate 113 are made equal to the ground potential GND, and the word line WL connected to the memory cell 110 is selected (equal to the boosted potential VPP. ) Then, the transfer gate 113
On the left side, a potential difference occurs between the left side bit line pair BLT0 and BLN0 and between the sense amplifier section bit lines BLT and BLN. That is, when a high potential (= array part potential VDL) is written in the memory cell 110, the potentials of the left side bit line BLT0 and the sense amplifier part bit line BLT are slightly increased, and the low potential of the memory cell 110 ( = (Ground potential GND) is written, the potentials of the left side bit line BLT0 and the sense amplifier section bit line BLT drop slightly. FIG. 1 shows a case where a low potential is written in the memory cell 110, and the potential of the sense amplifier section bit line (sense amplifier node) BLN is unchanged, but the sense amplifier section bit line (sense amplifier node) is changed. ) The potential of BLT is slightly reduced.

After that, the sense amplifier 101 is driven,
The potential difference between the bit lines 104 and 105 is amplified, but at that time, the control signal TGL of the transfer gate 108 is lower than the boosted potential VPP which is a logic high level and higher than the ground potential GND which is a logic low level. V
Make it equal to TG.

The predetermined potential VTG will be described in detail. The lower limit value of the transfer gate 108 is when the sense amplifier 101 amplifies about 60% on the low level side (the sense amplifier section bit line BLT side in this embodiment). The value is set to such a value that the N-channel transistor is conductive. That is, VTG ≧ 1/5 × VDL + VT, where VGS = V, where VGS is the gate-source voltage of the N-channel transistor of the transfer gate 108.
TG-1 / 5 × VDL ≧ VT). Here, VT is 1 in the N-channel transistor of the transfer gate 108.
It is a gate voltage that allows a current of about μA to flow. Further, the upper limit value of the predetermined potential VTG is set to be equal to or lower than the level at which the N channel transistor of the transfer gate 108 operates in the saturation region. That is, VTG ≦ 1/2 × VDL + VT (the drain-source voltage of the N-channel transistor of the transfer gate 108 is VDS, the sense amplifier 1
If the low-level voltage (also referred to as floating) inside 01 is VSA, then VDS = 1/2 × VDL−VSA ≧ VGS−V
T = VTG-VSA-VT). The actual value of the predetermined potential VTG is, for example, VDL = 1.4 [V] and VT = 0.
Assuming 5 [V], 0.78 ≦ VTG ≦ 1.2.

As described above, the transfer gate 108
After the control signal TGL of is made equal to the predetermined potential VTG,
The control signal SEN of the ground potential supply circuit 106 is set to the peripheral operation potential VCL, and the first control signal SEP1 of the drive potential supply circuit 107 is set to be equal to the ground potential GND.
As a result, the sense amplifier 101 amplifies the potential difference between the sense amplifier section bit lines BLT and BLN. At this time,
Little or no current flows through the N-channel transistor on the bit line 104 side of the transfer gate 108. Therefore, the sense amplifier 101 is connected to the low level side (sense amplifier section bit line B
Until the potential of (LT) is amplified by 50 to 60%, the amplification operation can be performed at almost the same speed as when the transfer gate 108 is non-conductive. On the other hand, the potential of the left bit line BLT0 located on the left side of the transfer gate 108 is N
Since a small amount of current flows through the channel transistor, it is slowly pulled out. Sense amplifier 1
The operation of the high level side of 01 (sense amplifier bit line BLN) is hardly affected by the difference in the potential of the control signal TGL of the transfer gate 108, and can be raised to the VOD level as in the conventional case.

Then, the first of the drive potential supply circuit 107
The control signal SEP1 is returned to the high voltage operating potential VOD, and the second control signal SEP2 is made equal to the ground potential GND. Further, the control signal TGL of the transfer gate 108 is returned to the boosted potential VPP. As a result, the potential of the sense amplifier section bit line BLN drops to become equal to the potential of the left bit line BLN0, and then the left bit line BN.
It rises together with the potential of LN0 until it becomes equal to the array potential VDL. On the other hand, on the bit line 105 side, the potential of the left side bit line BLT0 continues to decrease slowly, becomes equal to the sense amplifier section bit line BLT, and then becomes equal to the ground potential GND. On the bit line 105 side,
Before and after returning the control signal TGL of the transfer gate 108 to the boosted potential VPP, no large change in the potential is seen. That is, noise is hardly generated in the low potential side node of the sense amplifier 101.

As a result, the potential amplified by the sense amplifier 101 is supplied to the memory cell 110, and the restore operation is performed. Then, during this time, if the control signal YSW of the column gate 112 is made equal to the boosted potential VPP, the potential amplified by the sense amplifier 101, that is, data can be output (read) to the data bus 111.

When the restore operation (and read operation) is completed as described above, the potential of the word line WL is then made equal to the ground potential GND and the selection of the memory cell 110 is completed. Then, the control signal SEN of the ground potential supply circuit 106 is returned to the ground potential GND, and the drive potential supply circuit 1
07 second control signal SEP2 to the high voltage operating potential VOD
Return to. Thereafter, the control signal PDLL of the precharge circuit 109 is made equal to the boosted potential VPP, and the control signal TGR of the transfer gate 113 is made equal to the boosted potential VPP, so that the bit lines 104 and 105 are in the initial state, that is, the bit line 104. , 105 can be in a state (intermediate level) equal to ½ × VDL over the entire line.

As described above, according to the sense amplifier driving method of this embodiment, the amplification by the sense amplifier 101 can be performed at high speed, and the generation of noise at the connection point of the sense amplifier on the low level side can be suppressed. can do.

Next, the transfer gate 10 described above.
A circuit for generating the control signals TGL and TGR of 8 and 113 will be described.

A circuit for generating the control signals TGL and TGR is, for example, as shown in FIG.
It is composed of a generation circuit and a pair of selection circuits (TGL side and TGR side selection circuits) for selectively outputting any one of the output voltage VTG, the boosted potential VPP and the ground potential GND. Here, one terminal of the VDL stabilizing capacitor may be connected to the VTG voltage generating circuit as shown in FIG. By doing so, it is possible to obtain the output voltage VTG that follows changes in the array portion potential VDL.

The pair of selection circuits in FIG. 2A operate according to the time chart shown in FIG. That is, the TGL-side selection circuit controls the control signal PDLR of the precharge circuit 114.
And PDL controlled by the selection circuit control signal TGS.
When both R and TGS are equal to the boosted potential VPP, T
When VPP is output as GL, PDLR is equal to the boosted potential, and TGS is equal to GND, VGL is output as TGL.
Output TG. On the other hand, the TGR-side selection circuit is controlled by the control signal PDLL of the precharge circuit 109 and the selection circuit control signal TGS, and PDLL has the boosted potential VPP.
, VPP is output as TGR and PDLL
Is equal to the ground potential GND, GND is output as TGR. The selection signal of the word line WL and other signals not shown in FIG. 3 change at the same timing as shown in FIG.

The circuit for generating the control signal TGL (TGR) may be constructed as shown in FIG. 4 or 5. The circuit shown in FIG. 4 uses the VT floating of the P-channel transistor to generate the potential VTG, and the circuit shown in FIG. 5 has the VT of the N-channel transistor.
The floating is used to generate the potential VTG. These circuits have an advantage that the potential VTG can be generated from the existing power supply voltage.

By preparing two sets of the circuits shown in FIG. 4 or 5, one can be operated as a circuit for generating the control signal TGL and the other as a circuit for generating the control signal TGR. That is, when the control signal TGL, TGR generating circuit is configured by using two sets of the circuit of FIG. 4, the control signal TGL, TGR generating circuit is configured by using two sets of the circuit of FIG. 5 as shown in FIG. In this case, as shown in FIG. 7, the control signals TGE1R, TGE1L, TG, respectively.
E2, TGE3R and TGE3L are controlled by their control signals TG
The control signals TGL and TGR of the transfer gates 108 and 103 are supplied to the L and TGR generation circuits.
Can be obtained. Here, the control signals TGL and TGR
Control signals TGE1R, TGE for controlling the generation circuit
1L, TGE3R, and TGE3L constitute a control driver using a NAND circuit and a NOT circuit, for example, as shown in FIG. 8 and FIG.
14 control signals PDLL and PDLR and the selection circuit control signal TGS. The selection signal and other signals of the word line WL which are not shown in FIGS. 6 and 7 change at the same timing as that shown in FIG.

Next, a method of driving the sense memory according to the second embodiment of the present invention will be described.

As shown in FIG. 10, the driving method of the sense memory according to the present embodiment is such that, when driving the sense amplifier 101, the control signal TGL of the transfer gate 108 is used.
Is not immediately changed from the boosted potential VPP to the potential VTG, but is once lowered to near the ground potential GND, and then set to the potential VTG. At this time, if the control signal TGL is set to the ground potential GND, noise is generated when the potential VTG is set. Therefore, when the potential VTG is set, the potential is set to a value that does not generate noise.

In this way, the transfer gate 108
By bringing the control signal TGL of 1) closer to the ground potential GND, the amplification speed of the sense amplifier can be improved as compared with the case of the method of driving the sense memory according to the first embodiment.

[0052]

As described above, according to the present invention, the predetermined voltage VTG is supplied as the control signal of the transfer gate before driving the sense amplifier, thereby enabling the subsequent amplification. At the same time, noise generated when a logical high level is supplied as a control signal for the transfer gate can be suppressed thereafter. As a result, it is possible to provide a method for driving a sense memory which can perform high-speed amplification and has less noise.

[Brief description of drawings]

FIG. 1 is a time chart for explaining a driving method of a sense amplifier according to a first embodiment of the present invention.

2A is a diagram showing an example of a circuit for generating control signals TGL and TGR used in the method for driving the sense amplifier of FIG. 1, and FIG. 2B is a circuit of FIG. It is a figure which shows the state which connected the VTG voltage generation circuit used for the VDL stabilizing capacitor.

FIG. 3 is a time chart for explaining the operation of the circuit of FIG.

FIG. 4 is a diagram showing another example of a circuit for generating a control signal TGL used in the method of driving the sense amplifier of FIG. 1, which is a circuit utilizing floating of VT of a P-channel transistor.

5 is a diagram showing another example of a circuit for generating a control signal TGL used in the driving method of the sense amplifier of FIG. 1, which is a circuit using floating of VT of an N-channel transistor.

FIG. 6 is a time chart for explaining the operation of the circuit of FIG.

FIG. 7 is a time chart for explaining the operation of the circuit of FIG.

8 is a control signal TGL, TGR using the circuit of FIG.
It is a figure which shows an example of the control driver of a generation circuit.

9 is a control signal TGL, TGR using the circuit of FIG.
It is a figure which shows an example of the control driver of a generation circuit.

FIG. 10 is a time chart for explaining a driving method of the sense amplifier according to the second embodiment of the invention.

FIG. 11 is a circuit diagram showing a configuration of a conventional DRAM to which the present invention can be applied.

FIG. 12 is a time chart for explaining a conventional method of driving a sense amplifier.

FIG. 13 is a time chart for explaining another conventional method for driving a sense amplifier.

[Explanation of symbols]

101 sense amplifier 102 N-channel flip-flop 103 P-channel flip-flop 104, 105 bit line 106 Ground potential supply circuit 107 drive potential supply circuit 108 Transfer Gate 109 Precharge circuit 110 memory cells 111 data bus 112 column gate 113 Transfer Gate 114 precharge circuit

Claims (8)

[Claims] 1. A memory cell, and a pair of bit lines for writing / reading information to / from the memory cell,
A sense amplifier connected between the pair of bit lines for amplifying a potential difference between the bit lines; and a pair of bit lines for electrically separating the sense amplifier from a part of the bit lines. In a driving method of a sense amplifier applied to a memory circuit including a transfer gate formed of a transistor provided respectively, a logic high level and a logic low level are provided as a control signal of the transfer gate at the start of driving the sense amplifier. A voltage between them, and turns off the transistor provided on the high potential side bit line among the transistors forming the transfer gate, and slightly turns on the transistor provided on the low potential side bit line. Is supplied with a predetermined voltage VTG, and after a predetermined time has passed, the control signal A predetermined voltage VT
A method of driving a sense amplifier, wherein G is changed to the logic high level. 2. The predetermined voltage VTG is maintained so that the amplification factor on the low potential side of the sense amplifier after the control signal is changed from the predetermined voltage VTG to the logic high level is maintained at 60% or more. The method for driving a sense amplifier according to claim 1, wherein the method is determined. 3. The ground potential GN is used as a control signal for the transfer gate at the start of driving the sense amplifier.
3. The method of driving a sense amplifier according to claim 1, wherein a voltage higher than D and lower than the predetermined voltage VTG is once supplied, and then the predetermined voltage VTG is supplied. 4. The driving of the sense amplifier is started by supplying a first driving voltage, and then the first driving voltage is applied.
Changing the control signal from the predetermined voltage VTG to the logic high level is continued by supplying a second drive voltage lower than the second drive voltage from the first drive voltage to the second drive voltage. 4. The method for driving a sense amplifier according to claim 1, wherein the driving voltage is changed after the driving voltage for the sense amplifier is changed to the driving voltage according to claim 1. 5. Each of the transistors forming the transfer gate receives a voltage VT as the control signal.
When the sense amplifier amplifies the potential difference between the pair of bit lines so as to be equal to the array voltage VDL, the predetermined voltage VTG is 1/5 × VDL + VT ≦ VT
The method of driving a sense amplifier according to claim 1, wherein G ≦ 1/2 × VDL + VT. 6. A VTG for generating the predetermined voltage VTG
The method of driving a sense amplifier according to claim 1, comprising a voltage generation circuit and a selection circuit for selecting the output of the VTG voltage generation circuit and the logic high level. Sense amplifier drive circuit. 7. The array section voltage V is applied to the sense amplifier.
A driving voltage supply circuit for supplying DL includes a VDL stabilizing capacitor for stabilizing the array voltage VDL, and an output of the VGT voltage generating circuit is connected to the VDL stabilizing capacitor. 7. The drive circuit for the sense amplifier according to claim 6, wherein 8. A first transistor for determining whether to supply the logic high level to the transfer gate, and a supply to the transfer gate when the first transistor changes from on to off. A second transistor for setting the applied voltage to the predetermined voltage VTG and a third transistor for determining whether to supply the logic low level to the transfer gate. Claims 1, 2, 3,
A sense amplifier drive circuit used in the method 4 or 5 of driving a sense amplifier.