JP2003016783A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which such situation is relaxed that temporal margin until the amplitude of a bit line is recovered is made severe and in which operation speed can be increased. SOLUTION: This device is provided with a memory cell array 100 in which a plurality of pairs of bit lines BLt/BLc are arranged, sense amplifiers 3 provided for respective pairs of bit lines BLt/BLc, column gates 5 provided for respective pairs of bit lines BLt/BLc for selecting a column of the memory cell array 100, and a write buffer circuit 7 holding a write data to be written into a memory cell. Selection of a write column is performed in the non- activation state of the sense amplifier 3, write data are written in the pair of bit lines BLt/BLc belonging to a selected column when the sense amplifier 3 is in a non-activation state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to speeding up data write operation.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing voltage waveforms of a word line, a bit line and a column selection line during a general data write operation and a data read operation.

As shown in FIG. 7, the data write operation of a semiconductor memory device having a bit line pair, for example, a DRAM,
Bit line pair BLt / BLc is precharged, row address is selected, word line WL is raised, and bit line pair BLt / BLc
After the data in the memory cell is sufficiently transmitted, the sense amplifier is activated. Then, the column selection signal CSL is raised to select a column, and the write data transmitted to the data line pair DQt / DQc is transmitted to the bit line pair BLt / BLc. The transmitted write data is amplified and latched by the activated sense amplifier and written in the memory cell. After that, the word line WL is lowered to complete the writing to the memory cell.

[0004]

In such a general data write method, as shown in FIG. 8, in the write cycle when the speed is increased, the column selection signal CS
Due to L, the inversion of the bit lines BLt / BLc is started, and the time margin until the amplitude of the bit lines is sufficiently recovered becomes particularly strict as compared with the read cycle, which is an obstacle to speeding up the operation.

The present invention has been made in view of the above circumstances, and an object thereof is to alleviate a situation in which a time margin until the amplitude of a bit line is recovered during a data write operation becomes strict, and further. It is an object of the present invention to provide a semiconductor memory device capable of operating at high speed.

[0006]

In order to achieve the above object, according to the present invention, first and second memory cells are connected.
Memory cell array in which a plurality of bit line pairs each including a plurality of bit lines are arranged, a sense amplifier provided in each of the plurality of bit line pairs, and a column of the memory cell array provided in each of the plurality of bit line pairs. A write gate circuit for holding write data to be written in the memory cell, the write column is selected when the sense amplifier is inactive, and the write data is selected. Writing is performed to the bit line pair belonging to a column when the sense amplifier is inactive.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In this description, common reference numerals are given to common portions throughout the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
According to the data writing method according to the embodiment, the word line,
It is a figure which shows the voltage waveform of a bit line and a column selection line. In FIG. 1, a DRAM is used as a semiconductor memory device.
Assume

As shown in FIG. 1, in the present invention, column selection is performed before the rise of the word line WL or the activation time of the sense amplifier, and the data writing to the bit line is completed. After that, the operation after the word line WL is raised is the same as the read operation.

By the way, when data is written to the bit line belonging to the selected column, the written data interferes with the bit line belonging to the non-selected column adjacent to the selected column, and the bit belonging to the non-selected column. The potential of the line may fluctuate from the precharge level VPRC.

More specifically, in the present invention, as shown in FIG. 2, the precharge / equalize circuit 1 (1 [0] to
1 [2], ...) And the sense amplifiers 3 (3 [0] -3 [2], ...) Are inactive, respectively, and data are transferred to the bit lines BLt [1] / BLc belonging to the selected column. Write in [1]. And
Bit lines belonging to non-selected columns BLt [0] / BLc [0], BLt [2] /
BLc [2], ... Is in an electrically floating state because the column gates 5 [0], 5 [2] ,.

In this state, the data is transferred to the bit line BLt.
When written to [1] / BLc [1], the electrically floating bit lines BLt [0] / BLc [0] and BLt [2] / BLc [2] are coupled via the bit line capacitance C. However, the potentials of these bit lines change from the precharge level VPRC. When the potential of the bit line changes from the precharge level VPRC, for example, during data reading, it becomes difficult for the data stored in the memory cell to be correctly transmitted to the bit line, which may cause a malfunction.

In consideration of such circumstances, in the first embodiment, the data write potential to the bit line is set to a level that does not cause interference with the bit line belonging to the non-selected column. As a specific example of this level, as shown in FIG. 1, a bit line potential difference (hereinafter referred to as a write level) Vbl2 at the time of writing data becomes substantially equal to a minute potential difference Vbl1 appearing between the bit lines when data is read from a memory cell. To do so. When “Vbl1 <Vbl2” is set, the upper limit of the write level Vbl2 is set to a level that does not interfere with the bit lines belonging to the non-selected column.

To give a concrete example of the upper limit of the write level Vbl2, it is about 0.5V.

The upper limit of the write level Vbl2 varies depending on, for example, the value of the capacitance C between the bit lines and the interference level with respect to the adjacent bit lines, and is not limited to the above-mentioned about 0.5V. Absent.

According to the data writing method of the first embodiment, column selection is performed before the rise of the word line or the activation time of the sense amplifier, so that, for example, as in the conventional case, By selecting the column, it is possible to solve the time problem when the bit lines BLt / BLc are inverted. Therefore, the time margin until the amplitude of the bit line is recovered during the data writing operation can be relaxed, and the operation speed can be further increased.

Specifically, for example, the write cycle can be shortened to the read cycle.
By shortening the write cycle to the same as the read cycle, the operation of the semiconductor memory device, for example, DRAM,
Can speed up.

(Second Embodiment) Next, a specific circuit example of a DRAM adopting the data writing method according to the first embodiment of the present invention will be described as a second embodiment of the present invention.

FIG. 3 shows a D according to the second embodiment of the present invention.
It is a circuit diagram which shows RAM.

As shown in FIG. 3, a plurality of memory cells a0,
, a0, b0, b1, ... Are arranged in a matrix in the memory cell array 100. These memory cells a0, a1,
, B0, b1, ... are the same memory cell array 10
Bit lines BLt [0] / BLc [0], BLt [1] / BLc arranged at 0
Of [1], ..., Connected to the corresponding bit line.

Bit lines BLt [0] / BLc [0], BLt [1] / BLc [1],
... are precharge / equalize circuits 1 (1 [0],
1), a sense amplifier 3 (3 [0], 3 [1], ...) And a column gate 5 (5 [0], 5 [1], ...).

The precharge / equalize circuit 1 responds to the precharge control signal PRC to precharge and equalize the potential of the bit line to the precharge level VPRC.

The sense amplifier 3 amplifies the potential between the bit lines in response to the sense amplifier enable signal SAE.

The column gate 5 has a column selection signal CSL (CS
In response to L [0], CSL [1], ...), a column of the memory cell array is selected, and the bit lines belonging to the selected column are connected to the data lines DQt [0] / DQc [0], DQt [1]. Connect to / DQc [1], ...

Data lines DQt [0] / DQc [0], DQt [1] / DQc [1],
.. each include, for example, a write buffer circuit 7 for amplifying write data transmitted to the data line from outside the chip.
(7 [0], 7 [1], ...) And the DQ buffer circuit 11 (11 [0], 11 [1], which amplifies the read data transmitted from the bit line to the data line through the column gate 5). …) Are provided.

Further, in the second embodiment, the data line DQ
A write level control circuit 9 (9 [0], 9 [1], ...) Is provided for each of t [0] / DQc [0], DQt [1] / DQc [1] ,. The write level control circuit 9 sets the write level Vw to the bit line.
Control r to a level that does not interfere with bit lines belonging to unselected columns.

Specifically, the write level control circuit 9
Sets the lower limit of the write level Vwr to “Vbl2 = Vbl1”,
The upper limit is controlled to a level that does not cause interference with the bit lines belonging to the non-selected columns.

4 (A) to 4 (D) are circuit diagrams showing some specific circuit examples of the write level control circuit 9, respectively.

First, the first circuit example shown in FIG.
A constant current or constant voltage circuit 21 is provided between the high power supply potential VDD and the high power supply terminal of the write buffer circuit 7 to provide a low power supply potential.
A constant current or constant voltage circuit 22 is provided between the VSS and the low power supply terminal of the write buffer circuit 7.

The constant current or constant voltage circuit 21 lowers the high power supply potential VDD to the write level high potential VwrH by current control or voltage control and supplies it to the high power supply terminal of the write buffer circuit 7.

The constant current or constant voltage circuit 22 raises the low power supply potential VSS to the write level low potential VwrL by current control or voltage control and supplies it to the low power supply terminal of the write buffer circuit 7.

As a result, the power supply voltage supplied to the write buffer circuit 7 is controlled to the potential difference between the high potential VwrH and the low potential VwrL, that is, the write level Vwr. The power supply voltage supplied to the write buffer circuit 7 is set to the write level Vw.
By controlling to r, the write buffer circuit 7 can output the level of write data as the write level Vwr.

In the second circuit example shown in FIG. 4B, the PMOS 23 is provided between the high power supply potential VDD and the high power supply terminal of the write buffer circuit 7, and the low power supply potential VSS and the low power supply of the write buffer circuit 7 are provided. An NMOS 24 is provided between the terminal and the terminal.

The high power supply potential VD is applied to the gate of the PMOS 23.
A potential of D or less, for example, a potential of VDD or less and VDD / 2 or more is supplied. Then, the current supplied to the high power supply terminal of the write buffer circuit 7 is controlled by adjusting the gate potential of the PMOS 23 and its threshold value, respectively.
As a result, the high power supply potential VDD is set to the write level high potential Vwr.
Lower to H.

Further, the gate of the NMOS 24 is supplied with a potential equal to or higher than the low power source potential VSS, for example, a potential in the range of VSS or more and VDD / 2 or less, and the gate potential of the NMOS 24 and its threshold value are adjusted respectively. As a result, the current supplied to the low power supply terminal of the write buffer circuit 7 is controlled.
As a result, the low power supply potential VSS is set to the write level low potential Vwr.
Raise to L.

In the second circuit example, the power supply voltage supplied to the write buffer circuit 7 is set to the PMOS 23,
The write level Vwr is controlled by adjusting the gate potential and the threshold value of each NMOS 24.
Therefore, the write buffer circuit 7 can output the level of the write data as the write level Vwr.

In the third circuit example shown in FIG. 4C, the NMOS 25 is provided between the high power supply potential VDD and the high power supply terminal of the write buffer circuit 7, and the low power supply potential VSS and the low power supply of the write buffer circuit 7 are provided. A PMOS 26 is provided between the terminal and the terminal.

The gate potential of the NMOS 25 is a high power supply potential.
Fix to VDD. Then, by utilizing the threshold drop of the NMOS 25, the voltage supplied to the high power supply terminal of the write buffer circuit 7 is controlled to the write level high potential VwrH.
In this example, the write level high potential VwrH is VDD−Vthn (V
thn becomes the threshold value of the NMOS 25).

The gate potential of the PMOS 26 is fixed to the low power supply potential VSS. Then, the threshold floating of the PMOS 26 is used to control the voltage supplied to the low power supply terminal of the write buffer circuit 7 to the write level low potential VwrL. In this example, the write level low potential VwrL is VSS + V
thp (Vthp is the threshold value of the PMOS 26).

In the third circuit example as described above, the power supply voltage supplied to the write buffer circuit 7 is set to the threshold value Vthn,
Write level Vw by adjusting Vthp respectively
control to r. Therefore, the write buffer circuit 7 can output the level of the write data as the write level Vwr.

In the fourth circuit example shown in FIG. 4D, the capacitors 27 and 2 are used as the power supply source of the write buffer circuit 7.
8 is used. The capacitors 27 and 28 are charged / discharged by the charge / discharge circuit 30 each time data is written.

For example, when writing data, the charge / discharge circuit 30 first discharges the capacitor 27 having one electrode connected to the high power supply potential VDD and charges the capacitor 28 having one electrode connected to the low power supply potential VSS. . After that, the electric charge charged in the capacitor 28 is discharged and supplied to the high power supply potential terminal of the write buffer circuit 7. As a result, the high power supply potential terminal of the write buffer circuit 7 becomes the write level high potential VwrH. In addition, the capacitor 27 is charged with the electric charge accumulated in the low power supply potential terminal of the write buffer circuit 7. As a result, the low power supply potential terminal of the write buffer circuit 7 becomes the write level low potential Vw.
It becomes rL.

In the fourth circuit example as described above, the power supply voltage supplied to the write buffer circuit 7 is changed to the capacitor 2
Write level by adjusting the capacity of 7, 28
Control to Vwr. Therefore, the write buffer circuit 7
The level of write data can be output as the write level Vwr.

In the fourth circuit example, in order to set the write level Vwr to the bit line potential difference Vbl1 at the time of reading, the capacitances of the capacitors 27 and 28 are equal to or more than the capacitors of the memory cells. It is necessary.

Further, in the first to fourth circuit examples, the circuit for controlling the write level, the transistor and the capacitor are provided on both the high potential side and the low potential side, but the circuit for controlling the write level is provided. The transistors and capacitors may be provided only on one of the high potential side and the low potential side.

(Third Embodiment) In the first and second embodiments, in order to prevent the potential of the bit line in which the data is written from interfering with the bit lines belonging to the adjacent non-selected columns, An example has been shown in which the write level Vwr to the line is controlled to a level that does not interfere with the bit line belonging to the non-selected column.

The third embodiment relates to another method capable of suppressing the interference with the bit lines belonging to the adjacent non-selected columns without controlling the write level Vwr to the bit lines.

FIG. 5 shows a D according to the third embodiment of the present invention.
It is a circuit diagram which shows RAM.

As shown in FIG. 5, in the third embodiment, the precharge control signal PRC is assigned in the same manner as the column selection signal CSL, and the bit lines are precharged selectively.

The operation is such that, while writing data to the bit line belonging to the selected column, the bit line belonging to the non-selected column is in the precharged state. For example, the bit line BLt [0] / BLc selected by the column selection signal CSL [0]
Bit line BLt [1] / BLc when writing data to [0]
In [1], precharge is executed by the precharge signal PRC [1]. Further, the precharge of the bit lines BLt [0] / BLc [0] is canceled by the precharge signal PRC [0].

According to the third embodiment as described above, since the bit lines belonging to the non-selected columns are precharged during the data writing, as shown in FIG. 6, they are not electrically floated. . Therefore, it is possible to suppress the interference with the bit lines belonging to the non-selected column adjacent to the selected column.

As described above, the DRAM according to the first to third embodiments
According to the method, column selection is performed before the rise of the word line or the activation time of the sense amplifier, so that the bit line BLt / BLt / BLt /
The situation that BLc is reversed can be solved. Therefore, the time margin until the amplitude of the bit line is recovered during the data writing operation can be relaxed, and the operation speed can be further increased.

The present invention is not limited to each of the first to third embodiments, and in carrying out the invention, various modifications can be made without departing from the gist of the invention.

For example, although the DRAM is assumed as the semiconductor memory device in the first to third embodiments, the present invention is a DRAM.
However, the present invention is not limited to this, and any semiconductor memory device having a bit line pair can be implemented.

Further, each of the above-mentioned embodiments can be carried out independently, but it is of course possible to carry out in appropriate combination.

Furthermore, each of the above embodiments includes inventions at various stages, and inventions at various stages can be extracted by appropriately combining a plurality of constituent elements disclosed in each embodiment. Is.

[0057]

As described above, according to the present invention, it is possible to alleviate the situation in which the time margin until the amplitude of the bit line is recovered during the data write operation becomes strict, and the operation speed can be further increased. A possible semiconductor memory device can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing voltage waveforms of a word line, a bit line, and a column selection line according to a data write method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a selected column and a non-selected column in the first embodiment.

FIG. 3 is a DRAM according to a second embodiment of the present invention.
FIG.

FIG. 4A to FIG. 4D are circuit diagrams each showing a circuit example of a write level control circuit.

FIG. 5 is a DRAM according to a third embodiment of the present invention.
FIG.

FIG. 6 is a diagram showing a relationship between a selected column and a non-selected column in the third embodiment.

FIG. 7 is a diagram showing voltage waveforms of a word line, a bit line, and a column selection line according to a conventional data writing method.

FIG. 8 is a diagram showing voltage waveforms of a word line, a bit line, and a column selection line when a write cycle is accelerated.

[Explanation of symbols]

1 ... Precharge / equalize circuit, 3 ... sense amplifier, 5 ... Column gate, 7 ... write buffer circuit, 9 ... Write level control circuit, 11 ... DQ buffer circuit, 21, 22 ... Constant current or constant voltage circuit, 23 ... PMOS, 24 ... NMOS, 25 ... NMOS, 26 ... PMOS, 27, 28 ... Capacitor, 30 ... Charge / discharge circuit.

Claims (8)

[Claims] 1. A memory cell array in which a plurality of bit line pairs including first and second bit lines connected to memory cells are arranged, and a sense amplifier provided in each of the plurality of bit line pairs. The sense amplifier includes a column gate that is provided for each of the plurality of bit line pairs and that selects a column of the memory cell array, and a write buffer circuit that holds write data to be written in the memory cell. A semiconductor memory device, characterized in that the write data is written in an inactive state and the write data is written to the bit line pair belonging to the selected column when the sense amplifier is in an inactive state. 2. A write level control circuit for controlling a data write level to the bit line pair belonging to the selected column to a level for suppressing interference with the bit line pair belonging to a non-selected column. The semiconductor memory device according to claim 1, wherein: 3. The write level control circuit includes a constant current or constant voltage circuit for controlling a potential difference between a high power supply potential and a low power supply potential to the data write level. The semiconductor memory device described. 4. The semiconductor memory according to claim 2, wherein the write level control circuit includes a MOS transistor that controls a potential difference between a high power supply potential and a low power supply potential to the data write level. apparatus. 5. The semiconductor memory device according to claim 2, wherein the write level control circuit includes a capacitor that controls a potential difference between a high power supply potential and a low power supply potential to the data write level. . 6. A precharge / equalize circuit provided to each of the plurality of bit line pairs, wherein the precharge / equalize circuit belonging to the selected column performs precharge / equalize during data writing. 2. The semiconductor memory device according to claim 1, wherein the precharge / equalize circuit that is released and belongs to a non-selected column adjacent to the selected column performs precharge / equalize when writing data. 7. The write column selection is performed before a word line selecting a row of the memory cell array is activated.
The semiconductor memory device according to any one of claims. 8. The semiconductor memory device according to claim 1, wherein a data read cycle period and a data write cycle period are equal to each other.