JPH05250875A - Semiconductor storage device - Google Patents
Semiconductor storage deviceInfo
- Publication number
- JPH05250875A JPH05250875A JP4040009A JP4000992A JPH05250875A JP H05250875 A JPH05250875 A JP H05250875A JP 4040009 A JP4040009 A JP 4040009A JP 4000992 A JP4000992 A JP 4000992A JP H05250875 A JPH05250875 A JP H05250875A
- Authority
- JP
- Japan
- Prior art keywords
- sub
- signal
- level
- sense amplifier
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 230000004913 activation Effects 0.000 claims description 41
- 230000003213 activating effect Effects 0.000 claims 2
- 230000002779 inactivation Effects 0.000 claims 2
- 230000009849 deactivation Effects 0.000 claims 1
- 101001134276 Homo sapiens S-methyl-5'-thioadenosine phosphorylase Proteins 0.000 description 6
- 102100022050 Protein canopy homolog 2 Human genes 0.000 description 6
- 230000003321 amplification Effects 0.000 description 6
- 238000003199 nucleic acid amplification method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体記憶装置に関し、
特に１トランジスタ１キャパシタ型のメモリセルを有す
る半導体記憶装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a one-transistor / one-capacitor memory cell.
【０００２】[0002]
【従来の技術】近年、半導体記憶装置においては内部降
圧回路等を用いて低電圧動作を行なう記憶装置が主流と
なってきている。2. Description of the Related Art In recent years, in semiconductor memory devices, memory devices that operate at a low voltage using an internal voltage down converter have become mainstream.
【０００３】しかし、低電圧動作を行なうことにより、
例えば１トランジスタ１キャパシタ型のメモリセルを有
するダイナミックＲＡＭにおいては、メモリセルの蓄積
電荷量も小さくなり、センス増幅動作マージンも減少し
てしまう。However, by performing a low voltage operation,
For example, in a dynamic RAM having a 1-transistor 1-capacitor type memory cell, the amount of charge stored in the memory cell is also small, and the sense amplification operation margin is also reduced.
【０００４】この問題を解決する為に従来においては、
メモリセルのキャパシタの容量値を大きくすること、ビ
ット線の容量値を小さくすることのいずれかによりセン
ス増幅器の入力信号量を確保することが行われている。In order to solve this problem, conventionally,
The amount of input signal of the sense amplifier is secured by either increasing the capacitance value of the capacitor of the memory cell or decreasing the capacitance value of the bit line.
【０００５】[0005]
【発明が解決しようとする課題】しかし、従来の半導体
記憶装置におけるメモリセルのキャパシタの容量値を大
きくする方法においては、高集積化が進む程小面積内に
所定の容量値を確保する必要が生じ、キャパシタの絶縁
膜の薄膜化などにより物理的限界へ近づくことが予想さ
れる。However, in the conventional method of increasing the capacitance value of the capacitor of the memory cell in the semiconductor memory device, it is necessary to secure a predetermined capacitance value in a small area as the degree of integration increases. It is expected that the physical limit will be reached due to the thinning of the capacitor insulating film.
【０００６】又、ビット線の容量値を小さくするには、
ビット線上に存在するメモリセル数を減少させビット線
長を短かくする方法があるが、この方法はセンス増幅器
数を増加させる必要を生ずる為、高集積化に適さない。To reduce the capacitance value of the bit line,
Although there is a method of reducing the number of memory cells existing on the bit line to shorten the bit line length, this method is not suitable for high integration because it requires the increase of the number of sense amplifiers.
【０００７】従って従来の半導体記憶装置においては、
低電圧動作化にともなうセンス増幅動作マージンの悪化
を防ぐのが困難であるという問題点がある。Therefore, in the conventional semiconductor memory device,
There is a problem in that it is difficult to prevent the sense amplification operation margin from deteriorating due to the low voltage operation.
【０００８】本発明の目的は、低電圧動作におけるセン
ス増幅動作マージンを向上させることができる半導体記
憶装置を提供することにある。An object of the present invention is to provide a semiconductor memory device capable of improving a sense amplification operation margin in low voltage operation.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体記憶装置
は、対をなす第１及び第２の副ビット線と、対をなす第
１及び第２の主ビット線と、第１及び第２のワード線
と、ソース，ドレインの一方を前記第２の副ビット線と
接続し前記第１のワード線が選択レベルのときオンとな
るトランジスタ、及び一端をこのトランジスタのソー
ス，ドレインの他方と接続し他端を前記第１の主ビット
線と接続するキャパシタを備えた第１のメモリセルと、
ソース，ドレインの一方を前記第１の副ビット線と接続
し前記第２のワード線が選択レベルのときオンとなるト
ランジスタ、及び他端をこのトランジスタのソース，ド
レインの他方と接続し他端を前記第２の主ビット線と接
続するキャパシタを備えた第２のメモリセルと、副セン
ス増幅器活性化信号に従って活性化し前記第１及び第２
の副ビット線間の信号を増幅すると共に転送制御信号に
従って前記第１の副ビット線及び主ビット線間並びに第
２の副ビット線及び主ビット線間の接続を制御する副セ
ンス増幅器と、主センス増幅器活性信号に従って活性化
し前記第１及び第２の主ビット線間の信号を増幅する主
センス増幅器と、プリチャージ信号に従って前記第１及
び第２の主ビット線を所定のレベルにプリチャージする
プリチャージ回路と、前記副センス増幅器活性化信号，
転送制御信号，主センス増幅器活性化信号，プリチャー
ジ信号，及びワード線の信号を発生して各部動作を制御
する制御部とを有している。In a semiconductor memory device of the present invention, a pair of first and second sub-bit lines, a pair of first and second main bit lines, and a pair of first and second main bit lines are provided. And a transistor that is turned on when the first word line is at a selected level and one of the source and drain is connected to the second sub-bit line, and one end is connected to the other of the source and drain of the transistor. A first memory cell having a capacitor whose other end is connected to the first main bit line,
A transistor that is connected to the first sub-bit line with one of the source and drain and turned on when the second word line is at the selection level, and the other end is connected with the other of the source and drain of the transistor and the other end is connected. A second memory cell having a capacitor connected to the second main bit line; and the first and second memory cells activated according to a sub-sense amplifier activation signal.
A sub-sense amplifier for amplifying a signal between the sub-bit lines and controlling a connection between the first sub-bit line and the main bit line and between a second sub-bit line and the main bit line according to a transfer control signal. A main sense amplifier which is activated in accordance with a sense amplifier activation signal and amplifies a signal between the first and second main bit lines, and a precharge signal which precharges the first and second main bit lines to a predetermined level. A precharge circuit, the sub-sense amplifier activation signal,
It has a transfer control signal, a main sense amplifier activation signal, a precharge signal, and a signal of a word line to control the operation of each part.
【００１０】また、副センス増幅器が、副センス増幅器
活性化信号に従って活性化して１及び第２の副ビット線
間の信号を増幅して第１の転送制御信号に従って第１及
び第２の主ビット線にそれぞれ対応して伝達する回路で
あり、第２の転送制御信号に従って前記第１の副ビット
線及び主ビット線間並びに前記第２の副ビット線及び主
ビット線間の接続を制御する転送制御回路を設けた構成
を有している。The sub-sense amplifier is activated according to the sub-sense amplifier activation signal to amplify the signal between the first and second sub-bit lines, and according to the first transfer control signal, the first and second main bits. A circuit for transmitting the signal corresponding to each line, and controlling the connection between the first sub-bit line and the main bit line and between the second sub-bit line and the main bit line according to a second transfer control signal. It has a configuration provided with a control circuit.
【００１１】[0011]
【実施例】次に本発明の実施例について図面を参照して
説明する。Embodiments of the present invention will now be described with reference to the drawings.
【００１２】図１は本発明の第１の実施例を示す回路図
である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【００１３】この実施例は、対をなす第１及び第２の副
ビット線ＳＢ１１，ＳＢ１２と、対をなす第１及び第２
の主ビット線ＭＢ１，ＭＢ２と、第１及び第２のワード
線ＷＬ１１，ＷＬ１２と、ソース，ドレインの一方を第
２の副ビット線ＳＢ１２と接続し第１のワード線ＷＬ１
１が選択レベルのときオンとなるトランジスタＱ１、及
び一端をこのトランジスタＱ１のソース，ドレインの他
方と接続し他端を第１の主ビット線ＭＢ１と接続するキ
ャパシタＣ１を備えた第１のメモリセルＭＣ１１と、ソ
ース，ドレインの一方を第１の副ビット線ＳＢ１１と接
続し第２のワード線ＷＬ１２が選択レベルのときオンと
なるトランジスタＱ２、及び一端をこのトランジスタＱ
２のソース，ドレインの他方と接続し他端を第２の主ビ
ット線ＭＢ２と接続するキャパシタＣ２を備えた第２の
メモリセルＭＣ１２と、トランジスタＱ１１〜Ｑ１４を
備え副センス増幅器活性化信号ＳＳＡに従って活性化し
第１及び第２の副ビット線ＳＢ１１，ＳＢ１２間の信号
を増幅すると共に転送制御信号ＴＧ１に従って第１の副
ビット線ＳＢ１１及び主ビット線ＭＢ１間並びに第２の
副ビット線ＳＢ１２及び主ビット線ＭＢ２間の接続を制
御する副センス増幅器ＳＳ１と、トランジスタＱ２１〜
Ｑ２４を備え主センス増幅器活性信号ＭＳＡＰ，ＭＳＡ
Ｎに従って活性化し第１及び第２の主ビット線ＭＢ１，
ＭＢ２間の信号を増幅する主センス増幅器ＭＳと、トラ
ンジスタＱ３１，Ｑ３２を備えプリチャージ信号ＰＣに
従って第１及び第２の主ビット線ＭＢ１，ＭＢ２を所定
のレベルにプリチャージするプリチャージ回路２と、副
センス増幅器活性化信号ＳＳＡ，転送制御信号ＴＧ１，
主センス増幅器活性化信号ＭＳＡＰ，ＭＳＡＮ，プリチ
ャージ信号ＰＣ，及びワード線ＷＬ１１の信号を発生し
て各部動作を制御する制御部１とを有し、かつ、第１及
び第２の副ビット線ＳＢ１１，ＳＢ１２に対して第１及
び第２のメモリセルＭＣ１１，ＭＣ１２がそれぞれ複数
設けられ、第１及び第２の主ビット線ＭＢ１，ＭＢ２に
対してこれらと同一構成の第１及び第２の副ビット線並
びに副センス増幅器が複数設けられた構成となってい
る。In this embodiment, a pair of first and second sub-bit lines SB11 and SB12 and a pair of first and second sub-bit lines SB11 and SB12 are formed.
Main bit lines MB1 and MB2, first and second word lines WL11 and WL12, and one of a source and a drain thereof is connected to the second sub bit line SB12 to connect the first word line WL1.
A first memory cell having a transistor Q1 which is turned on when 1 is at a selection level, and a capacitor C1 having one end connected to the other of the source and drain of the transistor Q1 and the other end connected to the first main bit line MB1. MC11, a transistor Q2 that connects one of the source and drain to the first sub-bit line SB11 and is turned on when the second word line WL12 is at the selection level, and one end of this transistor Q2.
A second memory cell MC12 having a capacitor C2 connected to the other of the source and drain of No. 2 and the other end of which is connected to the second main bit line MB2, and transistors Q11 to Q14 according to the sub-sense amplifier activation signal SSA. The signal is activated to amplify the signal between the first and second sub-bit lines SB11 and SB12, and according to the transfer control signal TG1, between the first sub-bit line SB11 and the main bit line MB1 and the second sub-bit line SB12 and the main bit. The sub-sense amplifier SS1 for controlling the connection between the lines MB2 and the transistors Q21 to
Main sense amplifier activation signal MSAP, MSA with Q24
The first and second main bit lines MB1, which are activated according to N
A main sense amplifier MS for amplifying a signal between MB2, a precharge circuit 2 having transistors Q31, Q32 for precharging the first and second main bit lines MB1, MB2 to a predetermined level in accordance with a precharge signal PC, Sub sense amplifier activation signal SSA, transfer control signal TG1,
A main sense amplifier activation signal MSAP, MSAN, a precharge signal PC, and a control unit 1 for controlling the operation of each unit by generating a signal of the word line WL11, and the first and second sub bit lines SB11. , SB12 are provided with a plurality of first and second memory cells MC11 and MC12, respectively, and the first and second main bit lines MB1 and MB2 have the same configuration as the first and second sub-bits. A plurality of lines and sub sense amplifiers are provided.
【００１４】図２にこの実施例の制御部１内のセンス制
御部１１の具体的な回路例を、また図３に各部信号のタ
イミング図を示す。FIG. 2 shows a concrete circuit example of the sense control section 11 in the control section 1 of this embodiment, and FIG. 3 shows a timing chart of signals at respective sections.
【００１５】次にこの実施例の動作について説明する。Next, the operation of this embodiment will be described.
【００１６】まず初期状態においては制御信号Ｅ１，Ｅ
２が低電位となっているので、主センス増幅器活性化信
号ＭＳＡＰ，ＭＳＡＮ及び副センス増幅器活性化信号Ｓ
ＳＡはすべてプリチャージ電位ＶＲと等しくなってい
る。またプリチャージ信号ＰＣ，転送制御信号ＴＧ１，
ＴＧ２が高電位のアクティブレベルとなっているので、
主ビット線ＭＢ１，ＭＢ２、及びこの主ビット線ＭＢ
１，ＭＢ２にトランジスタＱ１３，Ｑ１４を介して接続
される副ビット線ＳＢ１１，ＳＢ１２（ＳＢ２１，ＳＢ
２２）はすべてプリチャージ電位ＶＲと等しくなってい
る。First, in the initial state, the control signals E1, E
2 has a low potential, the main sense amplifier activation signals MSAP and MSAN and the sub sense amplifier activation signal S
SA is all equal to the precharge potential VR. In addition, the precharge signal PC, the transfer control signal TG1,
Since TG2 is at high potential active level,
Main bit lines MB1 and MB2 and this main bit line MB
1 and MB2 via sub-bit lines SB11 and SB12 (SB21 and SB) connected via transistors Q13 and Q14.
22) are all equal to the precharge potential VR.
【００１７】次に動作状態となり転送制御信号ＴＧ１，
ＴＧ２が低電位のインアクティブレベルになると、主ビ
ットＭＢ１，ＭＢ２と副ビット線ＳＢ１１，ＳＢ１２
（ＳＢ２１，ＳＢ２２）とは分離される。この時プリチ
ャージ信号ＰＣは高電位であり、メモリセルＭＣ１１，
ＭＣ１２のキャパシタＣ１，Ｃ２の対極（主ビット線
側）はプリチャージ電位ＶＲに保たれている。Next, the operation state is set, and the transfer control signals TG1,
When TG2 goes to a low potential inactive level, the main bits MB1 and MB2 and the sub bit lines SB11 and SB12 are
It is separated from (SB21, SB22). At this time, the precharge signal PC is at a high potential, and the memory cells MC11,
The counter electrodes (main bit line side) of the capacitors C1 and C2 of MC12 are kept at the precharge potential VR.
【００１８】次にワード線ＷＬ１１が高電位の選択レベ
ルになると、メモリセルＭＣ１１と副ビット線ＳＢ１２
とが接続され、副ビット線ＳＢ１１，ＳＢ１２間に信号
差△Ｖ１が発生する。この後に制御信号Ｅ２を高電位に
して副センス増幅器活性化信号ＳＳＡを低電位の活性化
レベルとし、副ビット線ＳＢ１１，ＳＢ１２間の差電位
△Ｖ１を副センス増幅器ＳＳ１により増幅する。副ビッ
ト線ＳＢ１１，ＳＢ１２間に充分差電位が発生した後に
転送制御信号ＴＧ１を高電位へと戻すことで主ビット線
ＭＢ１，ＭＢ２にこの差信号を伝達するが、この時まで
にはプリチャージ信号ＰＣは低電位となっている必要が
ある。Next, when the word line WL11 reaches the high potential selection level, the memory cell MC11 and the sub bit line SB12 are selected.
Are connected to each other, and a signal difference ΔV1 is generated between the sub bit lines SB11 and SB12. After that, the control signal E2 is set to a high potential and the sub-sense amplifier activation signal SSA is set to a low-potential activation level, and the sub-sense amplifier SS1 amplifies the potential difference ΔV1 between the sub-bit lines SB11 and SB12. This difference signal is transmitted to the main bit lines MB1 and MB2 by returning the transfer control signal TG1 to a high potential after a sufficient difference potential has been generated between the sub bit lines SB11 and SB12. PC needs to be at a low potential.
【００１９】一方、主ビット線ＭＢ１，ＭＢ２と副ビッ
ト線ＳＢ１１，ＳＢ１２とがそれぞれ対応して接続され
ることで主ビット線ＭＢ１，ＭＢ２間には△Ｖ２の差電
位が発生する。この後制御信号Ｅ１を高電位とすること
により主センス増幅器活性化信号ＭＳＡＰ，ＭＳＡＮが
活性化レベルとなり主センス増幅器ＭＳが活性化され、
主ビット線ＭＢ１，ＭＢ２間及び副ビット線ＳＢ１１，
ＳＢ１２間の差電位△Ｖ２を増幅し始め、メモリセルＭ
Ｃ１１の記憶節点Ｎ１のリフレッシュが行われる。図３
においては、メモリセルＭＣ１１の記憶節点Ｎ１の初期
値が高電位である場合を表わしている。そしてこの記憶
節点Ｎ１はワード線ＷＬ１１が低電位となる時点におい
て、主センス増幅器活性化信号ＭＳＡＰと同電位の高電
位迄リフレッシュされている。On the other hand, since the main bit lines MB1 and MB2 and the sub bit lines SB11 and SB12 are connected to each other, a difference potential of ΔV2 is generated between the main bit lines MB1 and MB2. After that, the control signal E1 is set to a high potential to set the main sense amplifier activation signals MSAP and MSAN to the activation level, and the main sense amplifier MS is activated.
Between the main bit lines MB1 and MB2 and the sub bit line SB11,
Amplification of the potential difference ΔV2 between SB12 and the memory cell M
The storage node N1 of C11 is refreshed. Figure 3
In the figure, the case where the initial value of the storage node N1 of the memory cell MC11 is a high potential is shown. The storage node N1 is refreshed to a high potential that is the same potential as the main sense amplifier activation signal MSAP when the word line WL11 has a low potential.
【００２０】この後、制御信号Ｅ１，Ｅ２を低電位とす
ることで主センス増幅器活性化信号ＭＳＡＰ，ＭＳＡ
Ｎ、副センス増幅器活性化信号ＳＳＡ、主ビット線ＭＢ
１，ＭＢ２、副ビット線ＳＢ１１，ＳＢ１２（ＳＢ２
１，ＳＢ２２）のすべての電位がプリチャージ電位ＶＲ
へとプリチャージされる。この時主ビット線ＭＢ１は低
電位からプリチャージ電位ＶＲへと上昇するので、メモ
リセルＭＣ１１の記憶節点Ｎ１の電位は高電位（電源電
位）から更に昇圧される。従ってセンス増幅動作マージ
ンが大きくなる。After that, the control signals E1 and E2 are set to a low potential so that the main sense amplifier activation signals MSAP and MSA are activated.
N, sub sense amplifier activation signal SSA, main bit line MB
1, MB2, sub-bit lines SB11, SB12 (SB2
1, SB22) are all precharge potentials VR
Is precharged to. At this time, since the main bit line MB1 rises from the low potential to the precharge potential VR, the potential of the storage node N1 of the memory cell MC11 is further boosted from the high potential (power supply potential). Therefore, the sense amplification operation margin is increased.
【００２１】上述の例はメモリセルＭＣ１１に高電位の
電荷が蓄えられている場合を示したが、メモリセルＭＣ
１１に低電位の電荷が蓄えられている場合においては、
リセット時において主ビット線ＭＢ１が高電位からプリ
チャージ電位ＶＲへと下降する為、メモリセルＭＣ１１
の記憶節点Ｎ１の電位は低電位（接地電位）より更に降
圧される。Although the above-mentioned example shows the case where the high potential electric charge is stored in the memory cell MC11,
In the case where low-potential electric charge is stored in 11,
At the time of reset, the main bit line MB1 falls from the high potential to the precharge potential VR, so that the memory cell MC11
The potential of the storage node N1 is further lowered than the low potential (ground potential).
【００２２】図４は本発明の第２の実施例を示す回路
図、図５はそのタイミング図である。FIG. 4 is a circuit diagram showing a second embodiment of the present invention, and FIG. 5 is its timing chart.
【００２３】この実施例は、副センス増幅器ＳＳａ１
が、副センス増幅器活性化信号ＳＳＡに従って活性化し
て第１及び第２の副ビット線ＳＢ１１，ＳＢ１２間の信
号を増幅して第１の転送制御信号ＴＧ１１に従って第１
及び第２の主ビット線ＭＢ１，ＭＢ２にそれぞれ対応し
て伝達する回路となっており、第２の転送制御信号ＴＧ
１２に従って第１の副ビット線ＳＢ１１及び主ビット線
ＭＢ１間並びに第２の副ビット線ＳＢ１２及び主ビット
線ＭＢ２間の接続を制御する転送制御回路３を設けたも
のである。In this embodiment, the sub sense amplifier SSa1 is used.
Is activated according to the sub-sense amplifier activation signal SSA to amplify the signal between the first and second sub-bit lines SB11 and SB12, and according to the first transfer control signal TG11.
And the second main bit lines MB1 and MB2, respectively.
12, the transfer control circuit 3 for controlling the connection between the first sub bit line SB11 and the main bit line MB1 and the connection between the second sub bit line SB12 and the main bit line MB2 is provided.
【００２４】この実施例においては、第１の転送制御信
号ＴＧ１１によりオン，オフするトランジスタＱ１３，
Ｑ１４は副センス増幅器ＳＳ１が活性化する時のみ導通
し、副ビット線ＳＢ１１，ＳＢ１２間の差電位△Ｖによ
り主ビット線ＭＢ１，ＭＢ２を駆動する構成となってい
る。その他の基本的な動作及び効果は第１の実施例と同
様であるのでその説明は省略する。In this embodiment, the transistor Q13 which is turned on / off by the first transfer control signal TG11,
Q14 conducts only when the sub sense amplifier SS1 is activated, and drives the main bit lines MB1 and MB2 by the difference potential ΔV between the sub bit lines SB11 and SB12. The other basic operations and effects are the same as those in the first embodiment, and therefore their explanations are omitted.
【００２５】これら実施例においては、メモリセルＭＣ
１１等のキャパシタ（Ｃ１等）の対極の導体層と接続す
る主ビット線（例えばＭＢ１）と対をなす主ビット線
（ＭＢ２）が、トランジスタ（Ｑ１３，Ｑ１４）により
そのメモリセルの信号が読み出される副ビット線（ＳＢ
１２）へと接続される構成となっている為、メモリセル
の対極である導体層を主ビット線と共有でき、従って配
線層の低減が図れる。In these embodiments, the memory cell MC
A main bit line (MB2) paired with a main bit line (for example, MB1) connected to a counter electrode conductor layer of a capacitor (C1 or the like) such as 11 reads the signal of the memory cell by the transistors (Q13, Q14). Sub bit line (SB
12), the conductor layer, which is the counter electrode of the memory cell, can be shared with the main bit line, so that the wiring layer can be reduced.
【００２６】[0026]
【発明の効果】以上説明したように本発明は、メモリセ
ルの記憶節点及びキャパシタの対極を高電位及び低電位
にした後キャパシタの対極をプリチャージ電位にする構
成となっているので、メモリセルの記憶節点の電位を高
電位（電源電位）より高く、低電位（接地電位）より低
く増大させてリフレッシュでき、低電圧動作におけるセ
ンス増幅動作マージンを向上させることができる効果が
ある。As described above, according to the present invention, the storage node of the memory cell and the counter electrode of the capacitor are set to the high potential and the low potential, and then the counter electrode of the capacitor is set to the precharge potential. There is an effect that the potential of the storage node can be refreshed by increasing the potential higher than the high potential (power supply potential) and lower than the low potential (ground potential), and the sense amplification operation margin in the low voltage operation can be improved.
【図１】本発明の第１の実施例を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
【図２】図１に示された実施例の制御部内のセンス制御
部の具体例を示す回路である。FIG. 2 is a circuit showing a specific example of a sense control unit in the control unit of the embodiment shown in FIG.
【図３】図１に示された実施例の動作を説明するための
各部信号のタイミング図である。FIG. 3 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.
【図４】本発明の第２の実施例を示す回路図である。FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
【図５】図４に示された実施例の動作を説明するための
各部信号のタイミング図である。5 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.
１ 制御部 ２ プリチャージ回路 ３ 転送制御回路 １１ センス制御部 Ｃ１，Ｃ２ キャパシタ ＭＢ１，ＭＢ２ 主ビット線 ＭＣ１１，ＭＣ１２，ＭＣ２１，ＭＣ２２ メモリセ
ル ＭＳ 主センス増幅器 Ｑ１〜Ｑ９，Ｑ１１〜Ｑ１４，Ｑ２１〜Ｑ２４，Ｑ３
１，Ｑ３２，Ｑ４１，Ｑ４２ トランジスタ ＳＢ１１，ＳＢ１２，ＳＢ２１，ＳＢ２２ 副ビット
線 ＳＳ１，ＳＳ２ 副センス増幅器 ＷＬ１１，ＷＬ１２，ＷＬ２１，ＷＬ２２ ワード線1 Control Unit 2 Precharge Circuit 3 Transfer Control Circuit 11 Sense Control Unit C1, C2 Capacitor MB1, MB2 Main Bit Line MC11, MC12, MC21, MC22 Memory Cell MS Main Sense Amplifier Q1 to Q9, Q11 to Q14, Q21 to Q24, Q3
1, Q32, Q41, Q42 Transistor SB11, SB12, SB21, SB22 Sub bit line SS1, SS2 Sub sense amplifier WL11, WL12, WL21, WL22 Word line
Claims (5)
対をなす第１及び第２の主ビット線と、第１及び第２の
ワード線と、ソース，ドレインの一方を前記第２の副ビ
ット線と接続し前記第１のワード線が選択レベルのとき
オンとなるトランジスタ、及び一端をこのトランジスタ
のソース，ドレインの他方と接続し他端を前記第１の主
ビット線と接続するキャパシタを備えた第１のメモリセ
ルと、ソース，ドレインの一方を前記第１の副ビット線
と接続し前記第２のワード線が選択レベルのときオンと
なるトランジスタ、及び一端をこのトランジスタのソー
ス，ドレインの他方と接続し他端を前記第２の主ビット
線と接続するキャパシタを備えた第２のメモリセルと、
副センス増幅器活性化信号に従って活性化し前記第１及
び第２の副ビット線間の信号を増幅すると共に転送制御
信号に従って前記第１の副ビット線及び主ビット線間並
びに第２の副ビット線及び主ビット線間の接続を制御す
る副センス増幅器と、主センス増幅器活性信号に従って
活性化し前記第１及び第２の主ビット線間の信号を増幅
する主センス増幅器と、プリチャージ信号に従って前記
第１及び第２の主ビット線を所定のレベルにプリチャー
ジするプリチャージ回路と、前記副センス増幅器活性化
信号，転送制御信号，主センス増幅器活性化信号，プリ
チャージ信号，及びワード線の信号を発生して各部動作
を制御する制御部とを有することを特徴とする半導体記
憶装置。1. A pair of first and second sub-bit lines,
A pair of first and second main bit lines, first and second word lines, and one of a source and a drain are connected to the second sub bit line, and the first word line is at a selected level. One of the source and the drain, and a first memory cell having a transistor that is turned on when one end is connected to the other of the source and drain of the transistor and the other end is connected to the first main bit line. A transistor connected to the first sub-bit line and turned on when the second word line is at a selection level, and one end connected to the other of the source and drain of the transistor and the other end connected to the second main bit line A second memory cell having a capacitor connected to
It is activated according to a sub-sense amplifier activation signal to amplify a signal between the first and second sub-bit lines, and between the first sub-bit line and the main bit line and a second sub-bit line according to a transfer control signal. A sub sense amplifier for controlling connection between main bit lines, a main sense amplifier for activating a signal between the first and second main bit lines by activating it according to a main sense amplifier activation signal, and a first sense amplifier for precharge signal. And a precharge circuit for precharging the second main bit line to a predetermined level, and the sub sense amplifier activation signal, transfer control signal, main sense amplifier activation signal, precharge signal, and word line signal. And a control unit that controls the operation of each unit.
号及び転送制御信号をアクティブレベル、副センス増幅
器活性化信号及び主センス増幅器活性化信号を非活性化
レベル、ワード線のレベルを非選択レベルとし、動作状
態ではまず前記転送制御信号をインアクティブレベルに
した後前記ワード線を選択レベルとし、続いて前記プリ
チャージ信号をインアクティブレベルにして前記副セン
ス増幅器活性化信号を活性化レベルとし、続いて前記転
送制御信号をアクティブレベルとした後前記主センス増
幅器活性化信号を活性化レベルとし、続いて前記ワード
線を非選択レベルにした後前記プリチャージ信号をアク
ティブレベル、前記副センス増幅器活性化信号及び主セ
ンス増幅器活性化信号を非活性化レベルとする回路で構
成された請求項１記載の半導体記憶装置。2. The control unit, in an initial state, a precharge signal and a transfer control signal at an active level, a sub-sense amplifier activation signal and a main sense amplifier activation signal at a deactivation level, and a word line level at a non-selection level. In the operating state, first, the transfer control signal is set to the inactive level, then the word line is set to the selection level, then the precharge signal is set to the inactive level, and the sub-sense amplifier activation signal is set to the activation level. Subsequently, the transfer control signal is set to an active level, the main sense amplifier activation signal is set to an activation level, the word line is set to a non-selection level, the precharge signal is set to an active level, and the sub sense amplifier activation is set. 2. The circuit according to claim 1, wherein the activation signal and the main sense amplifier activation signal are set to an inactivation level. On-board semiconductor memory device.
及び第２のメモリセルがそれぞれ複数設けられ、第１及
び第２の主ビット線に対して前記第１及び第２の副ビッ
ト線並びに副センス増幅器が複数設けらた請求項１記載
の半導体記憶装置。3. A first for the first and second sub-bit lines.
2. The semiconductor memory according to claim 1, wherein a plurality of memory cells and a plurality of second memory cells are provided respectively, and a plurality of the first and second sub bit lines and a plurality of sub sense amplifiers are provided for the first and second main bit lines. apparatus.
化信号に従って活性化して１及び第２の副ビット線間の
信号を増幅して第１の転送制御信号に従って第１及び第
２の主ビット線にそれぞれ対応して伝達する回路であ
り、第２の転送制御信号に従って前記第１の副ビット線
及び主ビット線間並びに前記第２の副ビット線及び主ビ
ット線間の接続を制御する転送制御回路を設けた請求項
１記載の半導体記憶装置。4. A sub-sense amplifier is activated according to a sub-sense amplifier activation signal to amplify a signal between the first and second sub-bit lines, and according to a first transfer control signal, a first and second main bit. A circuit for transmitting the signal corresponding to each line, and controlling the connection between the first sub-bit line and the main bit line and between the second sub-bit line and the main bit line according to a second transfer control signal. The semiconductor memory device according to claim 1, further comprising a control circuit.
号及び第２の転送制御信号をアクティブレベル、第１の
転送制御信号をインアクティブレベル、副センス増幅器
活性化信号及び主センス増幅器活性化信号を非活性化レ
ベル、ワード線のレベルを非選択レベルとし、動作状態
ではまず前記第２の転送制御信号をインアクティブレベ
ルにした後前記ワード線を選択レベルとし、続いて前記
プリチャージ信号をインアクティブレベル前記第１の転
送制御信号をアクティブレベルにして前記副センス増幅
器活性化信号を活性化レベルとし、続いて前記主センス
増幅器活性化信号を活性化レベルとした後前記第２の転
送制御信号をアクティブレベルとし、続いて前記ワード
線を非選択レベルにして前記第１の転送制御信号をイン
アクティブレベルにした後前記プリチャージ信号をアク
ティブレベル、前記副センス増幅器活性化信号及び主セ
ンス増幅器活性化信号を非活性化レベルとする回路で構
成された請求項４記載の半導体記憶装置。5. The control unit, in an initial state, a precharge signal and a second transfer control signal at an active level, a first transfer control signal at an inactive level, a sub sense amplifier activation signal and a main sense amplifier activation signal. Is set to an inactive level, the level of the word line is set to a non-selection level, and in the operating state, the second transfer control signal is first set to the inactive level, then the word line is set to the selection level, and then the precharge signal is set to Active level The first transfer control signal is set to the active level, the sub-sense amplifier activation signal is set to the activation level, and then the main sense amplifier activation signal is set to the activation level, and then the second transfer control signal is set. Is set to an active level, then the word line is set to a non-selection level, and the first transfer control signal is set to an inactive level. 5. The semiconductor memory device according to claim 4, further comprising a circuit for setting the precharge signal to an active level and the sub sense amplifier activation signal and the main sense amplifier activation signal to an inactivation level.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4040009A JPH05250875A (en) | 1992-02-27 | 1992-02-27 | Semiconductor storage device |
| US08/011,776 US5353255A (en) | 1992-02-27 | 1993-02-01 | Semiconductor dynamic random-access memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4040009A JPH05250875A (en) | 1992-02-27 | 1992-02-27 | Semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05250875A true JPH05250875A (en) | 1993-09-28 |
Family
ID=12568911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4040009A Withdrawn JPH05250875A (en) | 1992-02-27 | 1992-02-27 | Semiconductor storage device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5353255A (en) |
| JP (1) | JPH05250875A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5652726A (en) * | 1994-12-15 | 1997-07-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system |
| US6094392A (en) * | 1998-09-10 | 2000-07-25 | Nec Corporation | Semiconductor memory device |
| JP2013122809A (en) * | 2011-11-09 | 2013-06-20 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device and driving method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2814862B2 (en) * | 1992-12-07 | 1998-10-27 | 日本電気株式会社 | Semiconductor storage device |
| JPH07114792A (en) * | 1993-10-19 | 1995-05-02 | Mitsubishi Electric Corp | Semiconductor memory |
| US5986914A (en) * | 1993-03-31 | 1999-11-16 | Stmicroelectronics, Inc. | Active hierarchical bitline memory architecture |
| JPH06338191A (en) * | 1993-05-28 | 1994-12-06 | Oki Electric Ind Co Ltd | Sense amplifier circuit and its driving method |
| US5742544A (en) | 1994-04-11 | 1998-04-21 | Mosaid Technologies Incorporated | Wide databus architecture |
| JP3270294B2 (en) * | 1995-01-05 | 2002-04-02 | 株式会社東芝 | Semiconductor storage device |
| US5734620A (en) * | 1995-04-05 | 1998-03-31 | Micron Technology, Inc. | Hierarchical memory array structure with redundant components having electrically isolated bit lines |
| US5600602A (en) * | 1995-04-05 | 1997-02-04 | Micron Technology, Inc. | Hierarchical memory array structure having electrically isolated bit lines for temporary data storage |
| US5675529A (en) * | 1995-07-07 | 1997-10-07 | Sun Microsystems, Inc. | Fast access memory array |
| JP2900854B2 (en) * | 1995-09-14 | 1999-06-02 | 日本電気株式会社 | Semiconductor storage device |
| US5995403A (en) * | 1996-03-29 | 1999-11-30 | Nec Corporation | DRAM having memory cells each using one transfer gate and one capacitor to store plural bit data |
| EP0834881A1 (en) * | 1996-10-01 | 1998-04-08 | STMicroelectronics S.r.l. | A multi-block memory |
| US5991217A (en) * | 1996-12-26 | 1999-11-23 | Micro Magic, Inc. | Fast SRAM design using embedded sense amps |
| FR2765026B1 (en) * | 1997-06-19 | 1999-08-13 | Sgs Thomson Microelectronics | READING METHOD AND CIRCUIT FOR DYNAMIC MEMORY |
| JP3360717B2 (en) * | 1997-09-29 | 2002-12-24 | 日本電気株式会社 | Dynamic semiconductor memory device |
| JPH11306762A (en) * | 1998-04-20 | 1999-11-05 | Mitsubishi Electric Corp | Semiconductor memory |
| US6201730B1 (en) * | 1999-06-01 | 2001-03-13 | Infineon Technologies North America Corp. | Sensing of memory cell via a plateline |
| JP2001291389A (en) * | 2000-03-31 | 2001-10-19 | Hitachi Ltd | Semiconductor integrated circuit |
| US6469941B2 (en) * | 2000-12-29 | 2002-10-22 | Stmicroelectronics, Inc. | Apparatus and method for pumping memory cells in a memory |
| JP2003151267A (en) * | 2001-11-09 | 2003-05-23 | Fujitsu Ltd | Semiconductor memory device |
| US7289369B2 (en) * | 2005-04-18 | 2007-10-30 | International Business Machines Corporation | DRAM hierarchical data path |
| US8743591B2 (en) | 2011-04-26 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device and method for driving the same |
| US8982607B2 (en) | 2011-09-30 | 2015-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Memory element and signal processing circuit |
| US9230615B2 (en) | 2011-10-24 | 2016-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device and method for driving the same |
| TWI607434B (en) | 2011-10-24 | 2017-12-01 | 半導體能源研究所股份有限公司 | Semiconductor memory device and driving method thereof |
| CN106796918A (en) | 2014-10-10 | 2017-05-31 | 株式会社半导体能源研究所 | Semiconductor device, circuit board and electronic equipment |
| US10424671B2 (en) | 2015-07-29 | 2019-09-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, circuit board, and electronic device |
| US12068020B2 (en) | 2018-12-10 | 2024-08-20 | Etron Technology, Inc. | Dynamic memory with sustainable storage architecture and clean up circuit |
| US11302383B2 (en) | 2018-12-10 | 2022-04-12 | Etron Technology, Inc. | Dynamic memory with sustainable storage architecture |
| US11798613B2 (en) | 2018-12-10 | 2023-10-24 | Etron Technology, Inc. | Dynamic memory with long retention time |
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|---|---|---|---|---|
| US4920517A (en) * | 1986-04-24 | 1990-04-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device having sub bit lines |
| JP2618938B2 (en) * | 1987-11-25 | 1997-06-11 | 株式会社東芝 | Semiconductor storage device |
-
1992
- 1992-02-27 JP JP4040009A patent/JPH05250875A/en not_active Withdrawn
-
1993
- 1993-02-01 US US08/011,776 patent/US5353255A/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5652726A (en) * | 1994-12-15 | 1997-07-29 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system |
| US5848012A (en) * | 1994-12-15 | 1998-12-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical bit line structure employing improved bit line precharging system |
| US6094392A (en) * | 1998-09-10 | 2000-07-25 | Nec Corporation | Semiconductor memory device |
| JP2013122809A (en) * | 2011-11-09 | 2013-06-20 | Semiconductor Energy Lab Co Ltd | Semiconductor memory device and driving method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US5353255A (en) | 1994-10-04 |
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Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990518 |