JPH0554122B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a process control device including a PID controller. In general, a first-order delay system process with dead time L is equivalent to 1/1+Ls as shown in Figure 1, where R is the proportional gain of the process, T is the time constant, and s is the differential operator. Dead time element 2 and
It is composed of a first-order lag element 3 expressed as 1/1+Ts. In order to properly control such a process 1, a PID controller 4 is connected in series to the process 1, and this PID controller 4 controls the target value r and the control amount x.
The parameters of the PID controller 4 are set so that ultimately m=v. That is, PID controller 4
Letting G be the characteristic of , the following equation holds true in FIG. -(m1/1+Ls-v)R/1+TsG=m...(1) Here, if we set m=v and rearrange and find G, G=1/R(1+Ts)(1+1/Ls) =T/RL( 1+Ls) (1+1/Ts) ...(2). Further, the control amount x is x=(v1/1+Ls-v)R/1+Ts=-vLs/1+Ls·R/1+Ts (3). When this equation (3) is converted into a time function, it is expressed as x(t)=-vL/LT(e ^-t/L -e ^-t/T )...(4). When this equation (4) is integrated over time 0 to ∞, A=∫ ^∞ ₀ x(t)dt=-vRL (5) and the control area A=-vRL is obtained. The smaller the control area, the better, but until now it has been thought that A=-vRL shown in the above equation (5) is the minimum, and that the control area cannot be made any smaller. An object of the present invention is to provide a process control device that can obtain a desired control area that is even smaller than the control area that would be optimally adjusted in process control using the above-mentioned conventional PID controller. In order to achieve the above object, the process control device of the present invention provides a parallel circuit of a first-order delay element (1/1+nLs) and a first-order advance element (Ka・nLs/1+nLs) between the PID controller and the process. . However, Ka is a constant related to n and has a different value depending on whether the process is a first-order delay system or an integral system. The present invention will be explained in more detail below with reference to embodiments shown in the drawings. FIG. 2 is a block diagram of a process control device to which the present invention is applied to a first-order lag type process. In the same figure, C is equivalent dead time element 11, adder 1
The process A includes a proportional element 14, a differential element 15, an integral element 16, and an adder 18, and the difference between the target value r and the control amount x obtained by the adder 17. received PID
This is a PID controller that performs calculations. These process C and PID controller A are no different from those of conventional process control devices. B is the primary advance element 19 and 1 connected between PID regulator A and process C.
This is a parallel circuit of next delay elements 20. Corresponding to the fact that process C is a first-order lag system including dead time, the first-order advance element 19 is expressed as (2n-1)nLs/n ² (1+nLs), and the first-order lag element 20 is expressed as 1/1+nLs. The outputs of the first-order lead element 19 and the first-order lag element 20 are added by an adder 21 and derived as the manipulated variable m. In this embodiment, by arbitrarily selecting n, the control area can be made smaller than -vRL in the above equation (5); for example, if n=2, the control area becomes -vRL/2. This situation will be explained below using equations. In the embodiment shown in FIG. 2, the following equation holds. −(m1/1+Ls−v)R/1+Ts・[n(T+L)/
RL {1+TLs/T+L+1/(T+L)s}] {(2n-1)nLs/n ² (1+nLs)+1/1+
nLs}=m...(6) Rearrange this equation (6) to find m. (v-m1/1+Ls)1/1+Tsn{(T+L)/L+
Ts+1/Ls}・(2n-1)nLs+n ² /n ² (1+nLs=m (v-m1/1+Ls)1/1+Ts(1+Ts)(1+Ls
/Ls)・(2n-1)Ls+n/(1+nLs)=m v-m1/1+Ls=mLs(1+nLs)/(1+Ls) {
(2n−1)Ls+n}∴v=mLs(1+nLs)+{(2n−
1) Ls+n}/(1+Ls) {n+(2n-1)Ls} =mLs+n(Ls) ² +2nLs-Ls+n/(1+Ls){n+
(2n−1)Ls}=mn(1+Ls) ² /(1+Ls){n+
(2n-1)Ls} =mn(1+Ls)/n+(2n-1)Ls∴m=vn+(2n
-1) Ls/n(1+La)...(7) On the other hand, the controlled amount x is x=(m・1/1+Ls-v)・R/1+Ts...(8) x={vn+(2n-1)Ls/ n(1+Ls) ² −v}R/
1+Ts=-v(1+nLs)/n(1+Ls) ²・R/1+Ts
=-vR{1/n・Ls/(1+Ls) ²・1/1+Ts+(L
s) ² / (1 + Ls) ²・1/1 + Ts}...(9). Converting this equation (9) into a time function, x(t)=-vR [1/n{1/L-Tte ^-t/L -LT/(LT) ²
(e ^-t/L -e ^-t/T )}+L ² -t(LT)/(LT) ² e ^-t/L -L ² /
(L-T) ² e ^-t/T ] ...(10) Next, integrate equation (10) over time 0 to ∞ to calculate the control area An
When calculating, An=∫ ^∞ ₀ x(t)dt=-vR[1/n{L ² /L-T-LT/(
L-T) ² (L-T)}+L ³ /(L-T) ² -L ² /(L-
T)-L ² T/(L-T) ² ] =-vR[1/n{L ² /L-T-LT/L-T+L ³ -L ³ +
L ² T−L ² T/(L−T) ² ]=−vR[1/n{L(L−T
)/L-T}+0]=-vRL/n
...(11) becomes. If n=1 in equation (11), A1=-
vRL, which is the same as the control area of the conventional device shown in equation (5), but if n=2, the control area A2 becomes -vRL/2, which is half of the control area obtained with the conventional device. Furthermore, when n is further increased to 3, 4, etc., the control area becomes smaller successively. Therefore, by setting n to an appropriate value, a desired control area smaller than -vRL can be obtained. FIG. 3 is a block diagram of a process control device to which the present invention is applied to an integral system process. In the figure, C is equivalent dead time element 31, adder 3
2, and a process consisting of an integral element 33,
A is a PID controller that includes a proportional element 34, a differential element 35, an integral element 36, and an adder 38, and performs PID calculation in response to the difference between the target value r obtained by the adder 37 and the control amount x. . B is PID controller A
This is a parallel circuit of a first-order advance element 39 and a first-order lag element 40 connected between the process C and the process C. Process C
Corresponding to the fact that is an integral system process that includes dead time, the first-order advance element 39 is expressed as 1/n・nLs/1+nLs, and the first-order lag element 40 is expressed as 1/1+nLs. The outputs of the lead element 39 and the first-order lag element 40 are added by an adder 41 and derived as the manipulated variable m. It will be explained using equations that in this embodiment device as well, by arbitrarily selecting n, the control area can be made smaller than the value conventionally considered to be the minimum. Now, in this example device, if n=1, it is the case where a PID controller is applied to a conventional integral system process. At this time, the following equation holds true. -(m1/1+Ls-v)1/Ts・3T/L(1+2/3Ls
+ 1/3Ls)=m...(12) Rearrange this equation (12) to find m. (v-m1/1+Ls) 3/Ls・3Ls+2(Ls) ² +1/3L
s=mv=m(Ls) ² /(1+Ls)(1+2Ls)+m1/
1+Ls = m(Ls) ² +2La+1/(1+Ls)(1+2Ls)=m(
1+Ls) ² /(1+Ls) (1+2Ls)=m1+Ls/1+2L
s∴m=v1+2Ls/1+Ls...(13) On the other hand, the controlled variable x is expressed as Substituting m in the equation, x={v1+2Ls/(1+Ls) ² −v}1/Ts = −vL/T・Ls/1+Ls・1/1+Ls ……(15) Convert this following equation into a time function. x(t)=-vt/Te ^-t/L ...(16) Next, calculate the control area by integrating equation (16) over time 0 to ∞. A1=∫ ^{∞ 0} x(T)dt=-v1 /T{[-tLs ^-t/L ]
^∞ ₀ −∫ ^∞ ₀ −Ls ^-t/L dt} =−vL/T∫ ^∞ ₀ e ^-t/L dt=−vL/T(−
L) [e ^-t/L ] ^∞ ₀ = -vL ² /T...(17). This value is the control area considered to be the minimum for PID control of an integral process. In the device of this embodiment, the following equation generally holds true. −(m1/1+Ls−v)1/Ts・3nT/L(
1+3n-1/3n+1/3Ls) {nLs/n(1+nLs)+1
/1+nLs}=m
...(18) Rearranging this equation (18), (v-m1/1+Ls)3n/Ls・3nLs+(3n-1)(Ls
) ² +n/3nLs・1+Ls/1+nLs=m (v−m1/1+Ls)・(3n−1)(Ls) ² +3nLs+
n/(Ls) ²・1+Ls/1+nLs=m v=m(Ls) ² (1+nLs)+{n+3nLs+(3n-1)
(Ls) ² }/(1+Ls) {n+3nLs+(3n-1)(Ls) ²
} =m(Ls) ² +n(Ls) ³ +n+3nLs+3n(Ls) ² −(L
s) ² / (1 + Ls) n {1 + 3Ls + 3n - 1 / n (Ls) ² } = mn {1 + 3Ls + 3 (Ls) ² + (Ls) ³ } / n (1 + L
s) {1+3Ls+3n-1/n(Ls) ² }=m(1+Ls) ² /
1+3Ls+3n-1/n(Ls) ² ∴m=v1+3Ls+3n-1/n(Ls) ² /(1+Ls) ²
...(19) Substituting m from equation (19) into equation (14), the control amount x is x={v1+3Ls+3n-1/n(Ls) ² /(1+Ls) ³
−v}1/Ts
...(20) Rearranging this equation (20), x = -v (3-3n-1/n) (Ls) ² + (Ls) ³ / (1+
Ls) ³・1/Ts =-v1/n(Ls) ² +(Ls) ³ /(1+Ls) ³・1/T
s =-vL/T・1/nLs+(Ls) ² /(1+Ls) ³ =-vL/T{1/n・Ls/(1+Ls) ³ +(Ls) ² /
(1+Ls) ³ } ...(21) Converting the controlled variable x in equation (21) into a time function, x(t)=-vL/T {1/n・1/2(t/
L) ² e ^-t/L + (1-t/2L)t/Le ^-t/L }...(22) Integrating equation (22) over time 0 to ∞ to find the control area An, An= ∫ ^∞ ₀ x(t)dt=-vL/T{1/n・1/2L ² ∫ ^∞ ₀
t ² e ^-t/L dt+1/L∫ ^∞ ₀ te ^-t/L dt−1/2L ² ∫ ^∞ ₀ t ² e ^-t/
L dt} =-vL/T{1/n・1/2L ²・2L ³ +1/LL ² −1
/2L ²・2L ³ }=-vL/T{1/n・L+L-L}=-
vL ² /nT
(23) As is clear from a comparison of the above equations (17) and (23), it can be seen that in this example device as well, the larger the value of n, the smaller the control area. Note that in the above embodiment, instead of the general e ^-LS as the equivalent dead time element, 1/(1+
The reason for using LS) is explained below. For example, the formula (1) shown in Japanese Patent Application Laid-Open No. 57-5105, G
(S)=Ke ^-LS /(1+Ts) shows the characteristics of a first-order lag (gain K, time constant T) process including dead time L. In a process control system, the dead time is the manipulated variable m
The above equation can be illustrated as shown in FIG. 5 since it can be seen as the transfer delay time until the process is reached. From FIG. 5, x becomes the following equation. x=me ^-LS K/1+Ts ... (a) On the other hand, in this application, instead of the dead time e ^-LS , 1/(1+Ls) (first-order delay with L as the time constant) is used as the equivalent dead time, so It will be drawn as shown in Figure 6. From FIG. 6, x becomes the following equation. x=m1/1+Ls・K/1+Ts...(b) Here, the primary delayed process K/(1+Ts)
to go into. Let's examine the properties of a in Fig. 5 and b in Fig. 6.
Since a enters the process after step m by 1, it can be expressed in the time domain as follows. a=0 t≦L m t>L (c) The above equation (c) is illustrated as shown in a of FIG. 7. Since step m enters the process in the form of a first-order delay with time constant L, b is expressed as a time expression in the time domain. b=m(1-e ^-t/L ...(d) When (d) is illustrated, it becomes as shown in b in Figure 7. Here, the amount that enters the process is the amount a = in the case of equation (c).
m(t-L). In the case of equation (d), b can be integrated over time 0 to ∞, so it is as follows. Although the process is different in this way,
At the time when b reaches m, the amount entering the process becomes the same m(t-L). Therefore, when the same amount enters the same process, the response x should have the same value after a certain time. m is first-order delayed after the dead time e ^-LS K/(1+
Ts), the response x and m are linearly delayed K/(1+Ls) through the equivalent dead time 1/(1+Ls).
To see how much of a difference there is in the response x when Ts) is reached, equations (a) and (b) can be converted to the time domain and plotted. Converting equation (a) to the time domain results in the following equation. Converting equation (b) into the time domain results in the following equation. x(t)=mK {1-1/T-L (Te ^-t/T -Le ^-t/T )} ...(F) Given m=1, K=1, T=5, L=2 (E)
Figure 8 is obtained by plotting equations (F) and (F). As shown in this figure, the shape of the response up to t = 5 is different, but there is almost no difference in the shape after that, and t
= 20 and later are consistent. Since the actual process is characterized by high-order delay including dead time, the shape of the response is almost S-shaped as shown in FIG. From this S-shaped response curve,
To find the characteristics of the process, find the point where the tangent drawn to the steepest point (curvature point) of this curve intersects the time axis, and calculate the time L from the beginning of the response to this point (effective). It is considered dead time. Also, the value mK that the response curve reaches is set to 1, and this curve is calculated by approximating it to a linear lag as shown by the dotted line, where the time constant is the time T obtained by subtracting the dead time L from the time it takes for this curve to reach 0.632. (This method best characterizes the S-shaped process). The actual process can also be expressed by approximating the dead time L, the gain K, and the first-order delay of the time constant T as described above. In this way, the primary lag including dead time is
After a certain period of time, the characteristics become the same whether e ^-LS K/1+Ts or 1/1+Ls・K/1+Ts.
If either e ^-LS or 1/1+Ls can be used as the dead time, it is better to use 1/1+Ls because it is easier to calculate. In addition, the response curve of the actual process (Figure 9)
is also similar to the response curve shown in FIG. 8 using 1/1+Ls. Next, taking a first-order lag process (gain: R, time constant: T) including an equivalent dead time L as an example, the effect of adopting the process control device of the present invention will be explained in the step of the controlled variable x shown in FIG. This will be explained using a response curve. In addition, in Fig. 4, R=1, T=5, L=2
This shows the case where the load v increases in steps of 0.1 in the process. In the figure, 4 is a plot of equation (4) and shows the case using conventional PID control. In addition, CHR is based on CHR (chien, HRones, Reswick), which has been considered optimal.
A case using PID control [the characteristic equation is 1.2T/RL (1+1/2Ls+0.42Ls)] is shown. Also 10,-
2, 10, -5, 10-10 indicate the case using the embodiment device of FIG. 2, and in the formula, n=
2, corresponding to the case of n=5 and n=10. The control area corresponding to these response curves is as shown in the table below, and compared to conventional devices such as 4 and CHR, the device according to the embodiment of this invention is

[Table] shows that the control area can be made much smaller. As described above, according to the process control device of the present invention, by adding the parallel connection of the first-order lag element and the first-order lead element between the conventional PID controller and the process, it was previously thought that it could not be further reduced. The control area can be made even smaller than the limit value, and the control area can be made to a desired small value by arbitrarily selecting and setting the constant n of the first-order lag element and the first-order advance element.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of a conventional process control device, FIGS. 2 and 3 are block diagrams showing a process control device in which the present invention is implemented, and FIG. 4 shows a conventional device and a process control device of the present invention. Fig. 5 is a block diagram showing a first-order delay process including dead time, and Fig. 6 is a first-order delay process including equivalent dead time. A block diagram showing a delayed process, FIG. 7 is a diagram explaining the response characteristics of the process, FIG. 8 is a diagram explaining other response characteristics of the process, and FIG. 9 is a higher-order delayed process including dead time. FIG. A: PID controller, B: additional parallel circuit, C: process, 11, 31; equivalent dead time element, 12, 1
7, 18, 21, 32, 37, 38, 41; Adder, 13; First-order lag element, 14, 34; Proportional element, 15, 35; Differential element, 16, 36; Integral element, 19, 39; 1 Next element, 20, 40; 1
Next lag element, 33; integral element.

Claims (1)

[Claims] 1. A process control device that controls a process including a dead time L, which includes a proportional element, an integral element, and a differential element, and performs PID calculation in response to a target value and a control amount from the process.
A PID controller, connected between this PID controller and the process,
A first-order lag element with a characteristic of 1/(1+nLs)
A linear advance element having a characteristic of KanLs/(1+nLs) and a parallel circuit (where n is an arbitrary constant, s is a differential operator, and Ka is an expression related to n determined depending on the type of process); Process control equipment.