JPH055374B2 - - Google Patents
Info
- Publication number
- JPH055374B2 JPH055374B2 JP62049107A JP4910787A JPH055374B2 JP H055374 B2 JPH055374 B2 JP H055374B2 JP 62049107 A JP62049107 A JP 62049107A JP 4910787 A JP4910787 A JP 4910787A JP H055374 B2 JPH055374 B2 JP H055374B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semi
- chip
- cured
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 42
- 239000011347 resin Substances 0.000 claims description 26
- 229920005989 resin Polymers 0.000 claims description 26
- 238000007789 sealing Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000010408 film Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F5/00—Systems for regulating electric variables by detecting deviations in the electric input to the system and thereby controlling a device within the system to obtain a regulated output
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor device.
従来、この種の接続方法は、半導体チツプとリ
ードフレームをボンデイングワイヤを用いたり、
半導体チツプとリードフレームとの間に導電体を
狭んだり、半導体チツプやリードフレームに突起
部を設けたりして半導体チツプとリードフレーム
を接続した後に、樹脂を滴下したりトランスフア
成形等により封止を行つていた。
Traditionally, this type of connection method involves connecting the semiconductor chip and lead frame using bonding wires,
After connecting the semiconductor chip and lead frame by placing a conductor between the semiconductor chip and the lead frame, or by providing a protrusion on the semiconductor chip or lead frame, sealing is performed by dripping resin or transfer molding. I was making a stop.
第２図は従来の半導体装置の一例を示す断面図
である。 FIG. 2 is a sectional view showing an example of a conventional semiconductor device.
絶縁基板１０上のアイランド１１に半導体チツ
プ１が設けられ、半導体チツプ１上の電極パツド
２とリードフレーム１３とにボンデイングワイヤ
１２をボンデイングし接続した後に、半導体チツ
プ１とボンデイングワイヤ１２とリードフレーム
１３の一部を樹脂にて被覆するようにトランスフ
ア成形等により封止されていた。 A semiconductor chip 1 is provided on an island 11 on an insulating substrate 10, and after bonding and connecting a bonding wire 12 to an electrode pad 2 on the semiconductor chip 1 and a lead frame 13, the semiconductor chip 1, the bonding wire 12, and the lead frame 13 are connected. It was sealed by transfer molding or the like so that a part of it was covered with resin.
上述したように、従来の接続封止方法は、接続
と封止を分けて行うので、工程が複雑になり、か
つ半導体チツプ１や電極パツド２やボンデイング
ワイヤ１２やリードフレーム１３に熱や応力が数
回加わるため、半導体チツプ１や電極パツド２や
ボンデイングワイヤ１２やリードフレーム１３に
ひずみが蓄積し、特性の変化や信頼性の低下を起
すという問題点があつた。
As mentioned above, in the conventional connection and sealing method, connection and sealing are performed separately, which complicates the process and causes heat and stress to the semiconductor chip 1, electrode pads 2, bonding wires 12, and lead frame 13. Since the stress is applied several times, strain accumulates in the semiconductor chip 1, the electrode pad 2, the bonding wire 12, and the lead frame 13, causing a problem in that characteristics change and reliability decreases.
本発明の目的は、半導体チツプ１の電極パツド
２とリードフレーム１３との接続と封止用樹脂に
よる封止を同時に行うことにより、作業工程が少
く、かつ半導体チツプ１や電極パツド２やボンデ
イングワイヤ１２やリードフレーム１３に加えら
れる熱や応力の影響を少くし、特性の変化のない
信頼性の高い半導体装置の製造方法を提供するこ
とにある。 An object of the present invention is to simultaneously connect the electrode pads 2 of the semiconductor chip 1 and the lead frame 13 and seal them with a sealing resin, thereby reducing the number of work steps and making it possible to connect the electrode pads 2 of the semiconductor chip 1, the electrode pads 2, and the bonding wires. It is an object of the present invention to provide a method for manufacturing a highly reliable semiconductor device in which the effects of heat and stress applied to the lead frame 12 and the lead frame 13 are reduced and the characteristics do not change.
本発明の半導体装置の製造方法は、半硬化封止
用樹脂板の一主面上でかつ半導体チツプ上の電極
パツドに対応する位置に接続用金属層を被着する
工程と、該接続用金属層を被着した前記半硬化封
止用樹脂板を前記半導体チツプの大きさよりも小
さくから前記電極パツドを含む大きさに切断して
半硬化樹脂チツプを形成する工程と、前記半硬化
樹脂チツプの前記接続用金属層とインナーリード
とを前記半導体チツプの前記電極パツドに位置合
わせしプレス機に装着する工程と、前記半硬化樹
脂チツプを加熱しながら加圧し前記半硬化樹脂チ
ツプと前記接続用金属層とを同時に溶融した後冷
却することにより前記半導体チツプ上の前記電極
パツドと前記インナーリードとを接続しかつ同時
に前記半導体チツプ上面を封止する工程とを含ん
で構成されている。
The method for manufacturing a semiconductor device of the present invention includes the steps of: depositing a connecting metal layer on one main surface of a semi-cured encapsulating resin plate at a position corresponding to an electrode pad on a semiconductor chip; forming a semi-cured resin chip by cutting the semi-cured encapsulating resin plate having the layer applied thereto into a size smaller than the size of the semiconductor chip to a size that includes the electrode pads; A step of aligning the connection metal layer and the inner lead with the electrode pad of the semiconductor chip and mounting it on a press machine, and heating and pressing the semi-hardened resin chip to separate the semi-hardened resin chip and the connection metal. The method includes the steps of connecting the electrode pads on the semiconductor chip and the inner leads by simultaneously melting and cooling the layers, and simultaneously sealing the top surface of the semiconductor chip.
次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第１図ａ〜ｃは本発明の一実施例を説明するた
めの工程順に示した断面図である。 FIGS. 1a to 1c are cross-sectional views showing the steps in order to explain an embodiment of the present invention.
半導体チツプ１上にはアルミニウムの表面には
んだ付性を良くするために白金薄膜が被覆された
電極パツド２が設けられており、半導体チツプ１
の表面には電極パツド２の部分を除くパターン形
成面上一面に半導体チツプ１を保護するためのパ
ツシベーシヨン被膜３が形成されている。インナ
ーリード４は、それぞれ外部パターンに接続して
おり、半導体チツプ１上の電極パツド２に対応す
るインナーリード４の幅は、電極パツド２よりも
狭い幅で形成されている。半硬化封止用樹脂板５
は、エポキシ系の封止樹脂を150℃の温度で150分
間加熱して半硬化したものであり、半硬化封止用
樹脂板５の表面の電極パツド２に対応する位置を
除く全面にホトレジストを塗布し、共晶はんだ６
を蒸着させた後、ホトレジストを剥離し、半硬化
封止用樹脂板５を半導体チツプ１よりも小さく、
かつ電極パツドを含む大きさに切断し半硬化樹脂
チツプ７を形成する。 On the semiconductor chip 1, there is provided an electrode pad 2 whose aluminum surface is coated with a platinum thin film to improve solderability.
A passivation film 3 for protecting the semiconductor chip 1 is formed on the entire surface of the pattern forming surface excluding the electrode pad 2 portion. Each inner lead 4 is connected to an external pattern, and the width of the inner lead 4 corresponding to the electrode pad 2 on the semiconductor chip 1 is narrower than that of the electrode pad 2. Semi-cured sealing resin plate 5
is a semi-cured epoxy sealing resin heated at a temperature of 150°C for 150 minutes, and photoresist is applied to the entire surface of the semi-cured sealing resin plate 5 except for the position corresponding to the electrode pad 2. Apply and eutectic solder 6
After vapor-depositing, the photoresist is peeled off, and the semi-cured sealing resin plate 5 is made smaller than the semiconductor chip 1.
Then, it is cut into a size that includes the electrode pad to form a semi-cured resin chip 7.
次に、半導体チツプ１上の電極パツド２に合わ
せてインナーリード４と半硬化樹脂チツプ７を位
置合わせしプレス機８に装着し、圧力を加えなが
ら185℃の温度で10分間加熱する。これによつて
共晶はんだ６が溶けて電極パツド２とインナーリ
ード４が接続され、これらの接続部を含む半導体
チツプ１上の全面が硬化した硬化樹脂体９で完全
に封止された半導体装置が得られる。 Next, the inner leads 4 and the semi-cured resin chip 7 are aligned with the electrode pads 2 on the semiconductor chip 1, mounted on a press machine 8, and heated at a temperature of 185° C. for 10 minutes while applying pressure. As a result, the eutectic solder 6 is melted, the electrode pad 2 and the inner lead 4 are connected, and the entire surface of the semiconductor chip 1 including these connection parts is completely sealed with the hardened resin body 9, resulting in a semiconductor device. is obtained.
なお、圧力を加えながら加熱する工程で圧力と
半硬化封止用樹脂板５の量を変化させることによ
り、半導体装置の仕上り時の厚さを制御出来るこ
とが確認された。 It has been confirmed that the finished thickness of the semiconductor device can be controlled by changing the pressure and the amount of the semi-cured sealing resin plate 5 in the step of heating while applying pressure.
以上説明したように、本発明は、半導体チツプ
の電極パツドとインナーリードとの接続と封止用
樹脂による封止を同時に行うことにより、作業工
程が少く、かつ半導体チツプや電極パツドやボン
デイングワイヤやインナーリードに加えられる熱
や応力の影響を少くし、特性の変化のない信頼性
の高い半導体装置が得られる。
As explained above, the present invention simultaneously connects the electrode pads and inner leads of a semiconductor chip and seals them with a sealing resin, thereby reducing the number of work steps and making it possible to connect the semiconductor chip, electrode pads, bonding wires, etc. The influence of heat and stress applied to the inner leads is reduced, and a highly reliable semiconductor device with no change in characteristics can be obtained.
更に、半硬化した封止用樹脂の量と接続封止時
に加える圧力を変化することにより、半導体装置
の厚さを自由に制御出来るので、薄い板厚が要求
されるICカード用等の半導体装置も得られると
いう効果がある。 Furthermore, by changing the amount of semi-cured sealing resin and the pressure applied during connection sealing, the thickness of the semiconductor device can be freely controlled, making it possible to control semiconductor devices such as those for IC cards that require a thin plate thickness. It has the effect that you can also obtain
第１図ａ〜ｃは本発明の一実施例を説明するた
めの工程順に示した断面図、第２図は従来の半導
体装置の一例を示す断面図である。
１……半導体チツプ、２……電極パツド、３…
…パツシベーシヨン被膜、４……インナーリー
ド、５……半硬化封止用樹脂板、６……共晶はん
だ、７……半硬化樹脂チツプ、８……プレス機、
９……硬化樹脂体、１０……絶縁基板、１１……
アイランド、１２……ボンデイングワイヤ、１３
……リードフレーム。
1A to 1C are cross-sectional views showing an example of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing an example of a conventional semiconductor device. 1... Semiconductor chip, 2... Electrode pad, 3...
... Passivation film, 4 ... Inner lead, 5 ... Semi-hardened sealing resin plate, 6 ... Eutectic solder, 7 ... Semi-hardened resin chip, 8 ... Press machine,
9... Cured resin body, 10... Insulating substrate, 11...
Island, 12... Bonding wire, 13
……Lead frame.
Claims (1)
チツプ上の電極パツドに対応する位置に接続用金
属層を被着する工程と、該接続用金属層を被着し
た前記半硬化封止用樹脂板を前記半導体チツプの
大きさよりも小さくかつ前記電極パツドを含む大
きさに切断して半硬化樹脂チツプを形成する工程
と、前記半硬化樹脂チツプの前記接続用金属層と
インナーリードとを前記半導体チツプの前記電極
パツドに位置合わせしプレス機に装着する工程
と、前記半硬化樹脂チツプを加熱しながら加圧し
前記半硬化樹脂チツプと前記接続用金属層とを同
時に溶融した後冷却することにより前記半導体チ
ツプ上の前記電極パツドと前記インナーリードと
を接続しかつ同時に前記半導体チツプ上面を封止
する工程とを含むことを特徴とする半導体装置の
製造方法。1. A step of depositing a connecting metal layer on one main surface of a semi-cured sealing resin plate at a position corresponding to an electrode pad on a semiconductor chip, and a step of depositing the semi-cured sealing layer on which the connecting metal layer is attached. forming a semi-hardened resin chip by cutting a stopping resin plate into a size smaller than the size of the semiconductor chip and including the electrode pads; a step of aligning the semiconductor chip with the electrode pad of the semiconductor chip and mounting it on a press machine; heating and pressurizing the semi-cured resin chip to simultaneously melt the semi-cured resin chip and the connection metal layer, and then cooling. A method of manufacturing a semiconductor device, comprising the steps of connecting the electrode pads on the semiconductor chip and the inner leads and sealing the top surface of the semiconductor chip at the same time.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62049107A JPS63213935A (en) | 1987-03-03 | 1987-03-03 | Manufacture of semiconductor device |
| KR1019880003476A KR880011636A (en) | 1987-03-03 | 1988-03-30 | controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62049107A JPS63213935A (en) | 1987-03-03 | 1987-03-03 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63213935A JPS63213935A (en) | 1988-09-06 |
| JPH055374B2 true JPH055374B2 (en) | 1993-01-22 |
Family
ID=12821853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62049107A Granted JPS63213935A (en) | 1987-03-03 | 1987-03-03 | Manufacture of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS63213935A (en) |
| KR (1) | KR880011636A (en) |
-
1987
- 1987-03-03 JP JP62049107A patent/JPS63213935A/en active Granted
-
1988
- 1988-03-30 KR KR1019880003476A patent/KR880011636A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| KR880011636A (en) | 1988-10-29 |
| JPS63213935A (en) | 1988-09-06 |
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