JPH0552705B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a timing signal extraction circuit for a receiver.

[Prior art]

An example of a timing signal extraction circuit that extracts only a timing signal from an input timing signal that includes noise and is easily degraded is a timing signal extraction circuit shown in FIG.

In FIG. 1, 1 is a timing signal input terminal, 2 is a gate circuit that controls the passage of the input timing signal and has input terminals for control signal B and control signal C, and 3 is a gate circuit through which the input timing signal passes through gate circuit 2. 4 is a fixed oscillator that oscillates at a frequency that is an integral multiple of the frequency of the input timing signal. 5 is a fixed oscillator that divides the output signal of the fixed oscillator 4 and outputs the same frequency as the input timing signal. A resettable frequency divider circuit outputs a frequency signal and a control signal B, and 6 is a signal output terminal of the frequency divider circuit 5. Further, a waveform diagram of each part of the circuit shown in FIG. 1 is shown in FIG. 2. Figure 2-A is an input timing signal, where 7 represents the true timing signal, 8 represents the noise mixed in between the timing signals, 9 represents the dropout of the timing signal, and 10 represents the noise mixed in after the timing signal was dropped. There is.

The timing signal inputted from the timing signal input terminal 1 can pass through the gate circuit 2 if the gate circuit 2 is in the pass permission state. On the other hand, if the gate circuit 2 is in a state where passage is prohibited, it is not possible to pass through the gate circuit 2. The timing signal extraction circuit shown in FIG. 1 extracts mixed noise from the gate circuit 2.
This circuit attempts to remove the timing signal when the gate circuit 2 is in a state where the passage is prohibited, and to obtain a timing signal when the gate circuit 2 is in a state where the gate circuit 2 is allowed to pass. The passage permission state of this gate circuit 2 is as follows.
The control signal B output from the frequency dividing circuit 5 is transferred to the gate circuit 2.
This is the period from the input of C to the gate circuit 2 inputting the control signal C output from the detection circuit 3.
Further, the passage prohibited state is a period from when the gate circuit 2 receives the control signal C output from the detection circuit 3 until the gate circuit 2 inputs the control signal B output from the frequency dividing circuit 5.

First, the frequency dividing circuit 5 divides the frequency of the output signal of the fixed oscillator 4 and outputs the control signal B shown in FIG. 2-B. The gate circuit 2 receives this control signal B and enters a passage permission state. Next, when the timing signal is input, the timing signal passes through the gate circuit 2 and resets the frequency divider circuit 5.
It is possible to synchronize the output signal with the timing signal. On the other hand, the detection circuit 3 detects that the timing signal has passed through the gate circuit 2, and the second
Outputs control signal C shown in Figure-C. When the gate circuit 2 receives this control signal C, it becomes in a state where passage is prohibited until the control signal B is input. Here, since the output signal of the frequency dividing circuit 5 and the timing signal are synchronized, the output timing of the control signal B is set to the expected input timing of the next timing signal. Therefore, since the noise 8 shown in FIG. 2-A cannot pass through the gate circuit 2 as shown in FIG. 2-D, it is possible to prevent the reset malfunction of the frequency dividing circuit 5 due to the noise 8 . Furthermore, since the timing signal 7 passes through the gate circuit 2 and resets the frequency divider circuit 5, an output signal 11 of the frequency divider circuit 5 synchronized with the timing signal can be obtained as shown in FIG. 2-E. Furthermore, in the circuit shown in FIG. 1, the frequency dividing circuit 5 divides the output signal of the fixed oscillator 4 and outputs a signal with the same frequency as the timing signal. It is possible to output the internal timing signal 12 whose state is maintained.

However, such a circuit has the drawback that noise mixed in after the timing signal drops passes through the gate circuit 2, causing the frequency divider circuit 5 to reset and malfunction. This is because if the timing signal is dropped, the detection circuit 3 does not output the control signal C, so the gate circuit 2 maintains the pass permission state.
Noise 10 shown in FIG. 2A is noise mixed in after the timing signal is dropped, and as shown in FIG. 2D, it passes through the gate circuit 2 and resets the frequency dividing circuit 5. Therefore, as shown in FIG. 3-E, a signal 13 synchronized with the noise appears in the output signal of the frequency dividing circuit 5. Furthermore, since the output timing of the control signals B and C is synchronized with the noise 10, not only the timing signal input after the noise 10 is removed, but also the frequency dividing circuit 5 outputs the internal timing signal 14 at the wrong timing. It is.

The circuit shown in Figure 1 cannot remove the noise mixed in after the timing signal is dropped, so it has sufficient timing signal extraction performance for equipment used under conditions where noise mixes or timing signals are frequently dropped. It cannot be given.

An example of a device used under such conditions is a portable television receiver. Portable television receivers are often used in moving objects such as trains and cars rather than in a stationary state, and are less prone to sudden changes in electric field strength and radio noise than stationary television receivers. Contamination frequently occurs. Therefore, the horizontal synchronization signal input to the horizontal synchronization circuit of a portable television receiver often contains noise or is dropped. However, as a horizontal synchronization circuit for a conventional portable television receiver, the horizontal synchronization circuit shown in FIGS.
The circuit shown in the figure is used. The circuit shown in FIG. 3 is the most widely used circuit, and the circuit shown in FIG. 4 is a circuit to which the timing signal extraction circuit shown in FIG. 1 is applied.

In FIGS. 3 and 4, 15 is a composite video signal input terminal, 16 is a sync separation circuit that separates a composite sync signal from a decoded video signal, and 17 is a horizontal sync signal separator that separates a horizontal sync signal from a composite sync signal. 19 is a horizontal AFC circuit; 20 is a signal output terminal of the horizontal AFC circuit 19; Further, in FIG. 3, reference numeral 18 denotes a noise removal circuit that includes a low-pass filter, a comparator, etc., and removes noise with a narrow time width. Note that the low-pass filter can be easily constructed using resistors, capacitors, etc., and can also be easily constructed using a comparator differential amplifier, a C-MOS threshold level, or the like. Further, in FIG. 4, 2 is a gate circuit that controls the passage of the horizontal synchronizing signal, 3 is a detection circuit that detects that the horizontal synchronizing signal has passed through the gate circuit 2, and 4 is a detection circuit that is an integer multiple of the frequency of the horizontal synchronizing signal. A fixed oscillator that oscillates at a frequency, and 5 a frequency divider circuit that divides the output signal of the fixed oscillator 4 and outputs a signal with the same frequency as the horizontal synchronization signal.The operation of these circuits is the same as the circuit in Figure 1. It is.

First, a composite video signal input from the composite video signal input terminal 15 is input to the synchronization separation circuit 16, and a composite synchronization signal is extracted. Next, this composite synchronization signal is input to a horizontal synchronization signal separation circuit 17, and a horizontal synchronization signal is extracted. The horizontal synchronization signal extracted by the horizontal synchronization signal separation circuit 17 may be contaminated with noise or
It's falling off. Here, in the circuit shown in FIG. 3, noise with a narrow time width is removed by the noise removal circuit 18, so the horizontal AFC circuit 19 operates stably against the inclusion of noise with a narrow time width, resulting in a stable screen. is obtained. However, since the noise cannot be removed by the noise removal circuit 18, which has a time width comparable to or more than the time width of the horizontal synchronization signal, the horizontal AFC circuit 19 cannot stably operate against such noise. , the screen becomes distorted. Furthermore, since nothing is input to the horizontal AFC circuit 19 when the horizontal synchronization signal is dropped, the horizontal AFC circuit 19 cannot operate stably, and the screen becomes distorted. On the other hand, in the circuit shown in FIG. 4, the noise mixed between the horizontal synchronizing signals cannot pass through the gate circuit 2 as described above, regardless of its time width, so the reset of the frequency dividing circuit 5 due to such noise is Malfunctions can be prevented. Therefore, since no signal synchronized with such noise appears in the output signal of the frequency dividing circuit 5, the horizontal AFC circuit 19 operates stably and a stable screen can be obtained. Furthermore, when the horizontal synchronization signal is dropped, the frequency divider circuit 5 divides the output signal of the fixed oscillator 4,
Since the horizontal AFC circuit 19 outputs an internal horizontal synchronizing signal, by inputting this internal horizontal synchronizing signal, the horizontal AFC circuit 19 operates stably and a stable screen can be obtained. However, if noise gets mixed in after the horizontal synchronization signal is dropped,
As mentioned above, the frequency divider circuit 5 is reset due to noise. Therefore, a signal synchronized with the noise appears in the output signal of the frequency divider circuit 5, and furthermore, an internal horizontal synchronization signal is output at the wrong timing, so the horizontal AFC circuit 19 inputs these signals and operates stably. The screen will be distorted.

As described above, the circuit shown in FIG. 4 can provide a more stable screen than the circuit shown in FIG. 3 with respect to the incorporation of noise and dropout of the horizontal synchronizing signal. However, the circuit shown in Figure 4 has the disadvantage that the screen is distorted by noise introduced after the timing signal is dropped, and it cannot provide sufficient synchronization performance as a horizontal synchronization circuit for a portable television receiver. .

[Purpose of the invention]

The present invention aims to eliminate such drawbacks, and its purpose is to extract timing signals stably and reliably even under conditions where noise contamination and timing signal dropout occur frequently in the timing signal extraction circuit of a receiver. The purpose of this invention is to provide a timing signal extraction circuit that can perform the following steps, and in particular, to provide a circuit that is optimal for a horizontal synchronization circuit of a portable television receiver.

[Summary of the invention]

The timing signal extraction circuit of the present invention includes a fixed oscillator that oscillates at a frequency that is an integral multiple of the frequency of the input timing signal, and an internal clock that has the same frequency as the input timing signal by dividing the output clock signal of this fixed oscillator. outputs a timing signal and has the same frequency as the input timing signal (in the embodiment, first and second
A frequency divider circuit that outputs a control signal (a signal consisting of a control signal) at a predetermined timing and can be reset by supplying a signal to a reset terminal, a gate circuit that controls passage of an input timing signal, and a gate circuit that controls passage of an input timing signal. It consists of a monitoring circuit that monitors the status. Further, the frequency divider circuit is reset by the input timing signal that has passed through the gate circuit, and the output signal of the frequency divider circuit and the input timing signal are synchronized.

The input timing signal passes through the gate circuit if the gate circuit is in a pass-permitting state and resets the frequency divider circuit. Furthermore, if the gate circuit is in a state where passage is prohibited, the signal cannot pass through the gate circuit. There are two states for controlling the passage of this gate circuit: an operating mode and a standby mode. In the operating mode, the period from when the gate circuit inputs the first control signal to when it inputs the second control signal is The passage is permitted, and the period from when the second control signal is input until when the first control signal is input is the passage prohibited status. On the other hand, the monitoring circuit inputs the input timing signal that has passed through the gate circuit and a signal indicating whether the gate circuit is allowed to pass through the gate circuit, monitors the gate circuit passing state of the input timing signal, and monitors the input timing of the input timing signal and the gate circuit. It is determined whether or not the timing matches the timing of the passage permission state, and if it is determined that they match, the output of the operation control signal indicating the operation mode is maintained. Conversely, if it is determined that they do not match, a third control signal is output, and the operation mode is switched to output of a standby control signal indicating standby mode. In the standby mode, the gate circuit is allowed to pass until the input timing signal passes, and when the input timing signal passes through the gate circuit, the standby mode is switched to the operating mode. At this time, the frequency divider circuit is reset by the input timing signal, and the output signal of the frequency divider circuit and the input timing signal passed through the gate circuit are again synchronized.

〔Example〕

The present invention will be described in detail below based on Examples.

FIG. 5 shows a first embodiment of the timing signal extraction circuit of the present invention, in which 1 is a timing signal input terminal, 21 is a terminal for controlling passage of an input timing signal,
A gate circuit having a first input terminal, a second input terminal, and a third input terminal; 22, a monitoring circuit that monitors the passing state of the input timing signal through the gate circuit 21; and 4, a monitoring circuit that outputs a third control signal; A fixed oscillator 50 oscillates at a frequency that is an integral multiple of the frequency of the input timing signal, and 50 divides the signal of the fixed oscillator 4 and outputs a signal having the same frequency as the input timing signal, a first control signal, and a second control signal. A resettable frequency dividing circuit 60 is a signal output terminal of the frequency dividing circuit 50.

Further, waveform diagrams of each signal line of the circuit shown in FIG. 5 are shown in FIGS. 6 and 7. Figure 6 shows the operating mode,
That is, it represents a mode in which the passage of the input timing signal through the gate circuit 21 is controlled by the first control signal and the second control signal, and FIG. This represents a mode in which the gate circuit 21 is in a passing permission state. Here, in both FIGS. 6 and 7, A is the timing signal input from the timing signal input terminal 1, F is the first control signal, G is the second control signal, and M is the input timing that has passed through the gate circuit 21. The signal E represents the output signal of the frequency dividing circuit 50, and H represents the third control signal.

First, the operation mode will be explained with reference to FIGS. 5 and 6.

As shown in FIG. 6-A, the timing signal inputted from the timing signal input terminal 1 includes not only the true timing signal 7 but also noise 8 mixed between the timing signals, timing signal dropout 9, and mixing after the timing signal dropout. It also includes noise 10. This input timing signal is input to the gate circuit 21, and the gate circuit 21 only during the passage permission state.
1 and resets the frequency divider circuit 50. Here, the passing permission state of the gate circuit 21 means that the first input terminal of the gate circuit 21 is in the first state shown in FIG. 6-F.
This is the period from when the control signal is input to when the second input terminal inputs the second control signal shown in FIG. 6-G, and during other periods, passage is prohibited. Therefore, as shown in FIG. 6-M, only the true timing signal 7 passes through the gate circuit 21, and the noises 8 and 10 mixed between the timing signals can be removed. In this way, since only the true timing signal 7 passes through the gate circuit 21 and resets the frequency divider circuit 50, the frequency divider circuit 50 is reset as shown in FIG.
0 can output a signal 11 synchronized with the true timing signal. Note that the first control signal and the second control signal are set to be output at the timing when the next true timing signal is expected to be input. Furthermore, since the frequency dividing circuit 50 divides the output signal of the fixed oscillator 4 and outputs a signal having the same frequency as the timing signal, even if the timing signal drop 9 occurs, the internal timing signal 12 maintains the state before dropping. can be output.

Next, the standby mode will be explained with reference to FIGS. 5 and 7.

The input timing of the input timing signal and the timing of the passage permission state of the gate circuit 21 may not match, such as when the power of the device is turned on or the input timing of the input timing signal changes. FIG. 7 is a waveform diagram showing this state. Since the true timing signal 23 shown in FIG. 7-A is input during the period in which the passage of the gate circuit 21 is prohibited, the signal shown in FIG. 7-M is Like, gate circuit 2
1 cannot be passed. At this time, the monitoring circuit 22 determines that the input timing of the input timing signal and the timing of the passage permission state of the gate circuit 21 do not match, and outputs the third control signal shown in FIG. 7-H. When the third input terminal of the gate circuit 21 receives the third control signal, the gate circuit 21 switches to a standby mode in which the gate circuit 21 is allowed to pass until the input timing signal passes through the gate circuit 21. The Ta period in the figure is the operating mode, and the Tb period is the standby mode. Then, when the true timing signal 24 passes through the gate circuit 21, the frequency divider circuit 50 is reset and the operation mode is switched again.
The same operation as in FIG. 6 is performed. Note that the internal timing signal 26 is a signal outputted by the frequency dividing circuit 50 at a constant cycle, and is a signal that is not synchronized with the input timing signal.

Next, the second timing signal extraction circuit of the present invention
An example of this is shown in FIG. 1 is a timing signal input terminal, 21 is a gate circuit, 22 is a monitoring circuit, 4
50 is a fixed oscillator, 50 is a frequency dividing circuit, 60 is a signal output terminal of the frequency dividing circuit 50, 27 is a resettable first counter that counts the number of input timing signals that have passed through the gate circuit 21, and 28 is a gate circuit 21. A resettable second counter 29 counts the number of times the passage is permitted, and 29 is the first counter 27.
and a logic circuit that detects the passing state of the input timing signal through the gate circuit 21 from the count value of the second counter 28; 30 is an AND gate; 31 to 34 are
NOR gate, 35, 36 are inverters, 37 is
It is an OR gate. Further, signal lines FGH in the figure represent each first control signal, second control signal, and third control signal.

When the third control signal H is "L", it is the operating mode, and when it is "H", it is the standby mode. When the third control signal is “L”, the first control signal F is “H”
The inverter 35 outputs "H" during the period from when it outputs "H" until the second control signal G outputs "H". In other words, the gate circuit 21 enters a passing permission state. Further, the inverter 35 outputs "L" during the period from when the second control signal G outputs "H" until when the first control signal F outputs "H". That is, the gate circuit 21 becomes in a state where passage is prohibited. When the timing signal input from the timing signal input terminal 1 passes through the gate circuit 21, the frequency divider circuit 50 is reset, and the output signal of the frequency divider circuit 50 can be synchronized with the input timing signal that has passed through the gate circuit 21. . On the other hand, the input timing signal that has passed through the gate circuit 21 is input to the first counter 27 , and the output signal of the inverter 35 is input to the second counter 28 . Then, the count value of the first counter and the count value of the second counter are input to the logic circuit 29, and based on the number of input timing signals that have passed through the gate circuit 21 with respect to the number of times that the gate circuit 21 has entered the pass permission state, It is determined whether or not the third control signal H is set to "H". That is, the input timing of the input timing signal and the gate circuit 2
It is determined whether or not the timing of the passage permission state of No. 1 coincides with the timing of the passing permission state. If it is determined that they match, the third control signal H maintains "L". If it is determined that they do not match, the logic circuit 29
In order to output “H” to the NOR gate 34, the third
The control signal H outputs "H" and enters the standby mode. In the standby mode, the inverter 35 becomes "H" and the gate circuit 21 enters a pass-through state. Then, when the input timing signal passes through the gate circuit 21 and inputs "H" to the NOR gate 33, the output of the inverter 36 becomes "L", that is, the third control signal H becomes "L", and the operation mode is switched. It is. Here, the reset signals for the first counter 27 and the second counter 28 are outputted by the logic circuit 29, for example, in a standby mode, or when the count value of the inverter 35 reaches a predetermined value.
This can be set arbitrarily in conjunction with the configuration of .

Next, FIG. 9 shows an embodiment of the monitoring circuit 22 constituting the timing signal extraction circuit of the present invention. The monitoring circuit 22 shown in FIG. 8 is configured such that the second counter 28 counts the number of times the gate circuit 21 is allowed to pass, but the monitoring circuit 22 shown in FIG. The second counter 28 is configured to count the number of times the input timing signal does not pass through the gate circuit 21 during the period of the permission state. 38 is an input terminal for the input timing signal that has passed through the gate circuit 21; 39 is an input terminal for a signal indicating whether the gate circuit 21 is allowed to pass through; 41 is an AND gate; and 42 is a data input flip-flop (hereinafter referred to as DF/F/F). F),
43 and 44 are NOR gates, 45 and 46 are inverters, and 47 is an arbitrary clock input terminal, and these elements allow the input timing signal to be input to the gate circuit 21 while the gate circuit 21 is in the pass permission state.
A circuit is constructed that generates a signal only when the signal does not pass through. Further, 27 is a first circuit that counts the number of input timing signals that have passed through the gate circuit 21.
38 is a second counter, 29 is a logic circuit, 33 and 34 are NOR gates, 36 is an inverter, and 40 is a third control signal output terminal. Further, a waveform diagram of each part of the circuit shown in FIG. 9 is shown in FIG. 10. 10-I is a signal indicating the passing permission/prohibition state of the gate circuit 21. When it is "H", it indicates the passing permission state, and when it is "L", it indicates the passing prohibition state. The input timing signal passed through the circuit 21, FIG. 10-J is the output signal of the NOR gate 44, and FIG. 10-K is the D-F/F 42.
The output signal of FIG. 10-L represents the output signal of AND gate 41.

When the input timing signal passes through the gate circuit 21 while the gate circuit 21 is in the pass permission state,
The signals shown in FIG. 10-I and FIG. 10-M both output "H". At this time, as shown in FIG. 10-J, the NOR gate 44 outputs "H" and D-
F/F 42 is reset. This D-F/F4
2 is maintained until the gate circuit 21 is prohibited from passing, that is, until the signal shown in FIG. 10-I outputs "L", so the output of the AND gate 41 is "L" as shown in
maintain. Therefore, when the input timing signal passes through the gate circuit 21 while the gate circuit 21 is in the pass permission state, the AND gate 41 maintains "L", so the second counter 28 does not count. On the other hand, while the gate circuit 21 is in the pass permission state, the input timing signal is not applied to the gate circuit 21.
1, the signal shown in FIG. 10-I outputs "H" and the signal shown in FIG. 10-M outputs "L". At this time, as shown in Figure 10-J
NOR gate 44 outputs “L” and D-F/F
Since the AND gate 42 is not reset, the AND gate 41 outputs "H" as shown in FIG. 10-L. Therefore, during the period when the gate circuit 21 is in the pass permission state,
When the input timing signal does not pass through the gate circuit 21, the AND gate 41 outputs "H", so the second counter 28 counts.

In this way, the monitoring circuit 22 shown in FIG. , the configuration is such that it is determined whether or not to output the third control signal.

Next, FIG. 11 shows an example in which the circuit of the present invention is applied to a horizontal synchronization circuit of a portable television receiver. 15 is a composite video signal input terminal, 16 is a sync separation circuit, 17 is a horizontal sync signal separation circuit, 21 is a gate circuit, 22 is a monitoring circuit, 4 is a fixed oscillator, 5
0 is a frequency dividing circuit, 19 is a horizontal AFC circuit, and 20 is an output terminal of the horizontal AFC circuit 19.

As already explained, the horizontal synchronizing signal obtained by the horizontal synchronizing signal separation circuit 17 of the portable television receiver is very susceptible to noise being mixed in or being dropped. When this horizontal synchronizing signal is input to the gate circuit 21, the noise mixed between the horizontal synchronizing signals can be reliably removed, and malfunction of the reset of the frequency dividing circuit 50 due to the noise can be prevented. Therefore, it is possible to obtain the output signal of the frequency dividing circuit 50 that is synchronized only with the horizontal synchronizing signal, and the horizontal AFC circuit 19 operates stably against noise, and a stable screen can be obtained. Furthermore, when the horizontal synchronization signal drops, the internal horizontal synchronization signal obtained by frequency-dividing the output signal of the fixed oscillator 4 can be sent to the horizontal AFC circuit 19, so the horizontal AFC circuit 19 operates stably. You can get a screen like this. Furthermore, when selecting a channel on a television receiver, the input timing of the horizontal synchronizing signal and the timing of the passage permission state of the gate circuit 21 may not match, but as already mentioned, the standby mode allows the gate circuit to easily The timing of the passage permission state of 21 can be changed.

〔Effect of the invention〕

As described above, according to the present invention, the gate circuit allows or prohibits passage of the timing signal at accurate timing based on the output signal of the fixed oscillator, allows only the timing signal to pass, and prevents the passage of the timing signal between the timing signals. noise can be prohibited from passing. Therefore, the timing signal passed through the gate circuit,
By resetting the frequency divider circuit that divides the output signal of the fixed oscillator, the output signal of the frequency divider circuit will be synchronized with the timing signal, and malfunction of the frequency divider circuit reset due to noise mixed between the timing signals can be prevented. . Furthermore, when the timing signal is dropped, the frequency divider circuit can divide the output signal of the fixed oscillator to generate an internal timing signal having the same frequency as the timing signal. In addition, the monitoring circuit monitors whether the timing of the gate circuit passage permission/prohibition state matches the input timing of the timing signal, and if they do not match, the timing of the gate circuit passage permission/prohibition state is easily changed. It is also possible to change the input timing of the timing signal to coincide with the timing of the passage permission state of the gate circuit.

Furthermore, in the circuit of the present invention, if the oscillation frequency of the fixed oscillator changes due to temperature drift or the like, the frequency of the internal timing signal generated when the timing signal drops does not match the frequency of the timing signal. However, between the case where no internal timing signal is generated and the case where a timing signal is generated using a fixed oscillator and a frequency dividing circuit, the device operates more stably when an internal timing signal is generated.

If we compare the horizontal synchronization circuit of a television receiver as an example, we can see that when the horizontal synchronization signal is dropped, generating an internal horizontal synchronization signal and inputting it to the horizontal AFC circuit is much more efficient than when the internal horizontal synchronization signal is not generated and nothing is input to the horizontal AFC circuit. Even if the frequency deviates from the frequency of the horizontal synchronization signal, the drift of the internal oscillation frequency within the horizontal AFC circuit is smaller when input to the horizontal AFC circuit, and the response when the horizontal synchronization signal is input again after dropping out is smaller. The properties are also improved. Therefore, even if the oscillation frequency of the fixed oscillator changes due to temperature drift or the like, it is effective to generate an internal timing signal, and the circuit of the present invention is of great significance.

As described above, the timing signal extraction circuit of the present invention is an optimal circuit for use under conditions where noise frequently enters or timing signals are dropped, and is particularly suitable for use in portable television receivers. It is possible to provide an optimal circuit for the machine's horizontal synchronization circuit.

Furthermore, a first counter counts the number of times the input timing signal passes through the gate means, and a first counter counts the number of times the gate means is allowed to pass or the number of times the input timing signal does not pass during the pass permission period of the gate means. Since a second counter is separately provided to allow passage of the gate, and the gate is set to a pass-through state based on the relationship between the counts of the two counters, it is possible to determine a more comprehensive trend of out-of-synchronization.

[Brief explanation of the drawing]

Figure 1 is a conventional example of a timing signal extraction circuit, Figure 2 is a waveform diagram of each part of the circuit in Figure 1, Figure 3 is a first conventional example of a horizontal synchronous circuit, and Figure 4 is a second example of a horizontal synchronous circuit. FIG. 5 is a timing signal extraction circuit according to the first embodiment of the present invention, FIG. 6 is a waveform diagram of each part of the circuit of FIG. 5 in an operating mode, and FIG. 7 is a diagram of the circuit of FIG. 5 in a standby mode. Waveform diagrams of various parts of the circuit, FIG. 8 shows a second embodiment of the timing signal extraction circuit of the present invention, FIG. 9 shows an embodiment of the monitoring circuit constituting the timing signal extraction circuit of the present invention, and FIG.
The waveform diagram of each part of the circuit shown in FIG. 11 is a third embodiment of the circuit of the present invention, and is a horizontal synchronous circuit to which the circuit of the present invention is applied. DESCRIPTION OF SYMBOLS 1... Timing signal input terminal, 2... Gate circuit of conventional timing signal extraction circuit, 3... Detection circuit, 4... Fixed oscillator, 5... Frequency dividing circuit of conventional timing signal extraction circuit, 6... Frequency dividing circuit 5
15...Composite video signal input terminal, 16...Sync separation circuit, 17...Horizontal synchronization signal separation circuit, 18...Noise removal circuit, 19...Horizontal AFC circuit, 20...Horizontal AFC circuit 19 signal output terminals, 21... gate circuit of the timing signal extraction circuit of the present invention, 22... monitoring circuit, 27...
First counter, 28...Second counter, 29
... logic circuit, 50 ... frequency divider circuit of the timing signal extraction circuit of the present invention, 60 ... signal output terminal of frequency divider circuit 50.

Claims (1)

[Claims] 1. By dividing the clock signal, an internal timing signal having the same frequency as the input timing signal is output, and a gate control signal having the same frequency as the input timing signal is output at a predetermined timing. a frequency dividing means that can be reset by supplying a signal to a reset terminal;
Transition to a state in which passage of the input timing signal to be controlled is permitted, and after the predetermined period, transition to a state in which passage of the input timing signal is prohibited, and also in response to input of a standby control signal, a state in which passage of the input timing signal is permitted. a first counting means for counting the number of times the input timing signal has passed through the gate means; and a first counting means for counting the number of times the input timing signal has passed through the gate means; a second counting means for counting the number of times the input timing signal has not passed; and outputting the standby control signal based on the relationship between the counted value of the first counting means and the counted value of the second counting means. A timing signal extraction circuit comprising: monitoring means, and supplying the input timing signal that has passed through the gate means to a reset terminal of the frequency dividing means.