JPH055216B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data communication device between microcomputers and the like.

[Prior art]

Conventionally, this type of communication control system has often used synchronous or asynchronous serial signals in order to reduce the number of signal lines. Such circuits for serial communication are increasingly being built into single-chip microcomputers in recent years, and have the advantage of being able to keep costs low.

However, since this type of communication control method was originally intended for long-distance communication, it requires complicated software control for error checking, etc., and also has the disadvantage that high-speed data transmission is difficult due to serial communication. There is.

Furthermore, when a microcomputer with a multi-chip configuration is used, a dedicated LSI must be added for serial communication, which has the disadvantage of increasing costs.

〔the purpose〕

In view of the above points, an object of the present invention is to provide a data communication device between microcomputers, etc., which is capable of high-speed processing with a simple hardware configuration.

〔Example〕

FIG. 1 is an example of a specific circuit configuration for communication control according to the present invention. microcomputer 23,
24 is a digital computer that requires data communication, and each includes a central processing circuit, a program memory for storing a control program, and
It has built-in random access memory (RAM) for temporary data storage, an interrupt control circuit, etc.

A rectangular wave oscillation output (clock 26) from an oscillation circuit 25 is connected to an interrupt input terminal of the microcomputers 23 and 24, respectively. In this embodiment, it is assumed that the interrupt function operates at the rising edge of the clock 26 in the microcomputer 23, and at the falling edge of the clock 26 in the microcomputer 24.

Further, the microcomputers 23 and 24 are connected to the input/output ports 21 and 21 via the microcomputer buses 27 and 28, respectively.
22 and performs parallel data input/output operations. For example, Intel's 8255A, microcomputer 23, 2 can be used as the input/output ports 21, 22.
4 also Intel's CPU8085A, RAM
8155 with built-in + timer + I/O port,
A combination of 8755A with built-in EPROM and I/O port can be used. The RST7.5 terminal of the 8085A can be used as an interrupt terminal, and an inverter circuit can be inserted into the clock 26 to generate a falling edge.

The input/output ports 21 and 22 are connected by signal lines 11 to 18, and protective resistors 1 to 8 are inserted between them, if necessary, in order to prevent circuit damage even if they are in an output state.

FIG. 2 is a timing chart showing the circuit operation of FIG. 1.

Microcomputers 23 and 24 are clock 2
It is shown that data communication is performed by performing interrupt processing operations alternately at the rising edge and falling edge of 6. In interrupt processing, the input/output port is first switched to input mode and data output by the other party is input, and then the data to be sent is output and data is exchanged.

As can be seen from the figure, each interrupt processing must be completed within half a cycle of the clock 26, and by guaranteeing this processing time, the maximum data transfer rate is determined, and the operation of each other is There is no need to confirm that the process has been completed, which has the advantage of making it easier to control the software.

3-a and 3-b are examples of control flowcharts of the microcomputers 23 and 24,
FIG. 3-a is an example of a flowchart of the main routine, and FIG. 3-b is an example of a flowchart of the interrupt processing routine.

In Figure 3-a, the microcomputer 2
After 3 or 24 is powered on and the microcomputer is hard reset, the steps
Initialize input/output ports 21 and 22 with SP1, internal
Perform initialization such as clearing RAM. step
At SP2, interrupts by the clock 26 are enabled, and the program proceeds to step SP3, where an interrupt-enabled program is executed. During the execution of step SP3, an interrupt request is issued by the clock 26, and the interrupt processing routine shown in FIG. 3-b is executed.

In Fig. 3-b, first, in step SP11, the input/output ports 21, 22 are changed to the input mode, and then the process proceeds to step SP12, where the data output by the other microcomputer is transferred to the input/output ports 21, 22.
Import from 2. Subsequently, in step SP13, the input/output port is set to output mode again, and in step SP14, data to be output to the partner microcomputer is output to the input/output ports 21 and 22. Subsequently, if necessary, the clock 26 is used as a timer clock, and the timer processing program is executed in step SP15.

FIG. 4 is an example of a wiring diagram when one side uses the output port 51 and the input port 52, and the other side uses the input/output port 53. 41～
48 is a signal line, and 31 to 38 are protective resistors similar to 1 to 8 in FIG.

FIG. 5 is an example of a wiring diagram when configured using output ports 91, 93 and input ports 92, 94. Similarly, 81 to 88 are signal lines, 61
~68, 71~78 are protective resistors.

Furthermore, although it has been described that the interrupt is executed by detecting the edge of the clock 26, a low/high level sense signal may be used as long as input/output operations can be executed at the timings described above. moreover,
Clock 2 if no interrupt signal is available.
A similar operation may be performed by polling and sensing 6.

Note that, according to the present invention, data communication can be performed particularly at high speed even in relatively short-distance data communication such as on the same board.

〔effect〕

As explained above, the present invention has a very simple hardware configuration and can be realized at low cost without using any special LSI.

Furthermore, by executing timer processing and software in the same interrupt processing, there is an advantage that software control is simplified.

Furthermore, since the data transfer is parallel transfer, there is an effect that high-speed processing is also possible.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one embodiment of a circuit configuration to which the present invention is applied, FIG. 2 is a timing chart for explaining the operation timing to which the present invention is applied, and FIG.
FIG. 4 and FIG. 5 are diagrams showing other embodiments of signal line connections. 23 and 24 are microcomputers, and 26 is a clock.

Claims (1)

[Claims] 1. A first microcomputer, a second microcomputer, and a first input/output port for the first microcomputer that inputs and outputs multiple bits in parallel and is set to a normal output mode. and a second input/output port for the second microcomputer that inputs and outputs multiple bits in parallel, is connected to the first input/output port by a plurality of signal lines, and is set to normal output mode; a generating means for generating a clock signal of a predetermined cycle; inputting the clock signal generated by the generating means to interrupt ports of the first microcomputer and the second microcomputer, respectively; The computer temporarily switches the first input/output port from the output mode to the input mode by interrupt processing in response to the rising edge of the clock signal, and outputs the data via the second input/output port. input the data from the second microcomputer, and then input the data from the first microcomputer.
On the other hand, the second microcomputer returns the second input/output port from the output mode to the input mode by interrupt processing in response to the falling edge of the clock signal. , inputting data from the first microcomputer that is output through the first input/output port, and then returning the second input/output port to the output mode. Data communication equipment.