JPH0550709B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a signal delay device equipped with a monitor function for checking signal delay effects, and by inputting an original sound signal to one channel of a headphone and inputting a delayed signal to the other channel,
This allows the delay effect to be clearly confirmed even with a small delay time. Signal delay devices are used to produce acoustic effects in studios, halls, etc., but it is necessary to check whether the set delay time is being delayed during actual use. If there is a clear time difference between the original sound and the delayed signal and the spatial arrangement is close, it is possible to judge by directly listening to the sound field, but in general, it is possible to judge by listening directly to the sound field, but in general msec to several tens of msec), and the spatial arrangement is often difficult to confirm directly with the ear (the longer the distance from the sound source to the ear, the greater the effect of that distance on the delay time. Therefore, some kind of ingenuity is required. The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a signal delay device having a monitoring function that allows the delay effect to be clearly confirmed even with a small delay time. The signal delay device of the present invention supplies an original audio signal to one channel unit of a headphone via an original audio signal supply path, and supplies a signal delayed from the original audio signal by a delay circuit to the other channel unit of the headphone. This allows the delay effect to be confirmed by the difference in sound heard by the left and right ears. According to this, the distance between the sound source and the ear becomes closer, eliminating the effect of delay time due to distance.
The delay effect caused by the delay circuit can be confirmed, and even the slightest delay time difference can be clearly identified. Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows an example of the overall configuration of a signal delay device according to the present invention. A portion surrounded by a dashed line 40 is a monitor circuit that implements the monitor function of the present invention. First, the portion that performs signal delay will be explained. The signal delay device shown in FIG. 1 has flexibility in circuit configuration and can be adapted to various purposes and conditions of use by dividing the memory 15 constituting the delay circuit according to the number of input signals. This is how it was done. That is, if there are few input signals, allocate a large memory area to each input channel to obtain a long delay time, and if each input signal requires a short time, allocate less memory area to each input signal. Therefore, many types of signals can be input, and various combinations of the number of input signals and delay times can be set.
Furthermore, this signal delay device has eight output channels CH1 to CH8, and by equally allocating these output channels CH1 to CH8 according to the number of input signals, various delayed signals can be obtained for each input signal. I have to. In other words, when the number of input signals is one, eight types of delayed signals are obtained for that input signal (hereinafter this mode of use is referred to as 1-in mode), and when the number of input signals is two
In this case, four types of delayed signals can be obtained for each input signal (hereinafter, this usage pattern will be referred to as 2 types).
When the number of input signals is four, two types of delay signals are obtained for each input signal (hereinafter, this usage mode is referred to as four-way mode).
(called in mode). The signal delay device shown in FIG. 1 has four input channels 1ch to 4ch, and the original sound signals input from the respective input terminals 1 to 4 are passed through attenuators 5 to 8 to A-D converters 9 to 4. 12, each is converted into a digital signal and sent to multiplexer 1.
3 is input. The multiplexer 13 multiplexes input data of each input channel 1ch to 4ch and outputs the multiplexed data according to a predetermined clock according to a command from a control device (CPU) 14 depending on the mode of use. For example, in the 1-in mode, one sample of the input channel (for example, the first input channel 1ch) is output every one clock (corresponding to one sampling period of the A/D converters 9 to 12). In addition, in the case of 2-in mode, 1
Samples of two input channels (for example, first and second input channels 1ch and 2ch) are sequentially output one by one for each clock. Further, in the case of the 4-in mode, samples of all input channels 1ch to 4ch are sequentially output one by one every clock. Data output from the multiplexer 13 is applied to a memory (RAM) 15 forming a delay circuit. The memory area of the memory 15 is divided according to the number of input channels in the usage mode according to a command from the control device 14. That is, in the case of 1-in mode, all addresses are used only for that one input channel (for example, 1ch) without division, and in the case of 2-in mode, they are divided into two and each area is used for each input channel (for example, 1ch, In the case of 4-in mode, it is divided into four areas and each area is allocated to all input channels 1CH to 4CH. Therefore, if the memory 15 has a configuration of, for example, 64K words, the amount allocated to each input channel will be: 1-in mode: 64K words, 2-in mode: 32K words, and 4-in mode: 16K words. The data of each input channel added to the memory 15 is distributed to the allocated areas and sequentially written in accordance with a write address command from the control device 14. The write address circulates within each area, and old data is sequentially rewritten with new data. Therefore, assuming a write clock of 40kHz, the maximum delay time obtained in each mode is: 1-in mode: 64K words/40kHz = 1.6 seconds 2-in mode: 32K words/40kHz = 0.8 seconds 4-in mode: 16K Word/40kHz = 0.4 seconds. The data written in the memory 15 is stored in the control device 1.
It is read out sequentially by commands from 4. At this time,
Delayed data is obtained by shifting the read address relative to the write address. This reading is performed in synchronization with writing. FIG. 2 shows the relationship between write addresses and read addresses in one divided memory area (address 1 to address n). Writing is performed cyclically within the memory area from address 1 to address n, and old data is sequentially rewritten with new data. If the delay time is set to R1, when a write is performed at clock _t1 , the address data written at clock _t1 ' is read out, and when a write is performed at clock _t2 , the address data written is read out. , the data at the address written at clock t ₂ ' is read, and when the write is performed at clock t ₃ , the data at the address written at clock t ₃ ' is read and the data at the write address is read. The read addresses are sequentially shifted at a constant interval _T1 . When obtaining two types of delay data for one input channel signal, set another delay time R2 to obtain t ₁ , t ₂ , t ₃ ,... as shown by the dashed line in Figure 2. When data is written by the clock, the data written by the clock at t ₁ ″, t ₂ ″, t ₃ ″, etc. is read out.If more delay times are set, the signal of one input channel can be read out. Many types of delay data can be obtained. In FIG. 1, the data read from the memory 15 is input to the multiplexer 16, and according to a command from the control device 14, each delay data is sent to each output channel CH1 to CH8. The delay data distributed to each output channel CH1 to CH8 is converted into the original audio signal by D-A converters 17 to 24, and then output to each channel output 25 to 3.
2 respectively. FIG. 3 shows the divided state of the memory 15 in each mode and the allocated state of output channels CH1 to CH8 to each divided memory area. Figure 3a shows the case of 1-in mode,
At this time, one input channel has one memory
A total area of 5 is allocated. Also, all 8 output channels CH1 to CH8 are input channel 1.
channel, and up to eight types of delayed signals can be obtained for the input signal of one input channel. Figure 3b shows the case of 2-in mode, where the memory 15
is divided into two regions 15a and 15b, and assigned to input channels 1ch and 2ch, respectively.
Output channels 1CH to 8CH are also divided into two groups, with output channels 1CH to 4CH being assigned to input channel 1ch, and 5CH to 8CH being assigned to input channel 2ch. Therefore, in this case, a maximum of four types of delayed signals can be obtained for the input signals of each input channel 1ch and 2ch. Third
Figure c shows the case of 4-in mode, and the memory 15 is 4-in mode.
It is divided into three areas 15c, 15d, 15e, and 15f, and input channels 1ch to 4ch are assigned to each area. Output channels 1CH to 8CH are also 4
Divided into groups, output channels 1CH, 2CH
is input channel 1, output channel 3
CH, 4CH are input channels 2ch, output channels 5CH, 6CH are input channels 3ch,
Output channels 7CH and 8CH are respectively assigned to input channel 4ch. Therefore, in this case, a maximum of two types of delayed signals can be obtained for the input signals of each input channel 1ch to 4ch. The connection states between input and output in each mode can be equivalently represented as shown in FIGS. 4a, b, and c, respectively. In FIG. 4, a shows the 1-in mode, b shows the 2-in mode, and c shows the 4-in mode.
In other words, in the 1-in mode, it is equivalent to providing 8 delay elements for 1 input channel, and in the 2-in mode, 4 delay elements are provided for each input channel 1ch and 2ch. In the case of 4-in mode, it is equivalent to providing two delay elements for each of the four input channels 1ch to 4ch.
In this manner, in the digital delay device shown in FIG. 2, various combinations of the number of input channels and delay times can be realized. In FIG. 1, the keyboard 33 serves as a delay time setting means for selecting a mode, setting a delay time (which can be set for each output channel from 1CH to 8CH), and selecting an output channel to be monitored. Further, the memory (RAM) 34 stores a program for processing in addition to delay time setting values. In addition, the display device 35 displays the selected mode, the connection status of input channels 1ch to 4ch and output channels CH1 to CH8, and the delay time of each output channel CH1 to CH8, etc., as shown in FIG. 5, for example. Now you can see the current usage status at a glance. Also,
When monitoring, the output channel being monitored is displayed. Next, the actual signal delay operation of the delay device shown in FIG. 1 will be explained with reference to the flowchart shown in FIG. Before use, the mode is selected and the delay times R1 to R8 for each output channel CH1 to CH8 are set in advance. When a mode is selected, the control device 14 calculates the start and end addresses of each divided area in the memory 15 according to the selected mode, and divides the memory 15. The calculated value is as follows, assuming that the entire area of the memory 15 is, for example, 0000 _H to FFFF _H (hexadecimal notation).

[Table] Also, since the delay times R1 to R8 can be set within the time that writing in each memory area completes,
The maximum value that can be set varies depending on the size of the memory area, and as mentioned above, based on 1-in mode, it is half that in 2-in mode, and 1/2 of that in 4-in mode.
In the case of mode, it becomes gradually shorter to 1/4. The signal delay operation in each mode is as follows. Incidentally, the relationship between write addresses and read addresses in each mode is shown in FIG. 1-in mode (Figure 6a) If 1-in mode is selected, memory 1
Since there is no division by 5, the entire area of the memory 15 is sequentially written and read from the first address A1. The read address is obtained by calculating the address distance from the current write address AD1 according to preset delay times R1 to R8. These read data are demultiplexed and output. Each time one set of writing and reading is completed (this one loop corresponds to one sampling period of input data), the current address AD1 is advanced one by one, and the current address AD1 becomes the ending address E1. When this is completed, the process returns to the starting address A1 and repeats the operation. 2-in mode (Fig. 6b) When the 2-in mode is selected, the starting address A1,
The data of input channels 1ch and 2ch are multiplexed and stored from A2. For the output channels CH1 to CH4, reading is performed by accessing the address obtained by calculating from the current address AD1 of the first memory area 15a using the respective set delay times R1 to R4, and for the output channels CH5 to CH8. This is performed by accessing the address obtained by calculating from the current address AD2 of the second memory area 15b using the respective set delay times R5 to R8. Each area 1
Each time one set of writing and reading is completed in 5a and 15b (also in this case, one loop
current address (corresponding to the sampling period)
Advance AD1 and AD2 one by one and repeat the above operation. When the current addresses AD1 and AD2 complete the end addresses E1 and E2 of each area, the process returns to the beginning addresses A1 and A2 and repeats the operation. 4-in mode (Fig. 6c) When the 4-in mode is selected, the input channels ch1, A2, A3, and A4 are input to each of the four areas 15c to 15f of the memory 15 divided into four. The data of ch2, ch3, and ch4 are multiplexed and stored. For the output channels CH1 and CH2, reading is performed by accessing the address obtained by calculating from the current address AD1 of the first memory area 15c using the set delay times R1 and R2, respectively. is accessed by accessing the current address obtained by calculating from the current address AD2 in the second memory area 15d using the set delay times R3 and R4, and for the output channels CH5 and CH6, the third memory This is done by accessing the addresses obtained by calculating from the current address AD3 in the area 15e using the set delay times R5 and R6, respectively, and for the output channels CH7 and CH8, the addresses are accessed from the current address AD4 in the fourth memory area 15f, respectively. This is done by accessing the address obtained by calculation using the set delay times R7 and R8. Each area 15c
~15f, each time one set of writing and reading is completed (in this case, one loop corresponds to one sampling period), the current address AD
1. Advance AD2, AD3, and AD4 one by one and repeat the above operation. Current address AD1, AD2,
AD3 and AD4 are the end address E1 of each area,
After completing E2, E3, and E4, the process returns to the starting addresses A1, A2, A3, and A4, and repeats the operation. Next, the monitor circuit 40 shown in FIG. 1 will be explained. The monitor circuit 40 receives the original sound signals of each input channel 1ch to 4ch before delay and the delayed signal of each output channel CH1 to CH8 after delay. The original audio signal is input to an analog switch 41. Further, the delayed signal is input to the analog switch 42. When monitoring a signal, one of the output channels CH1 to CH8 to be monitored is selected using the keyboard 33. Then, a control signal is output from the control circuit 14, the corresponding one of the analog switches 42 is turned on, and the delayed signal of the output channel is output from the analog switch 42. This delayed signal is supplied to the right channel unit 44r of the headphone 44 via the amplifier 43 (this supply path corresponds to the delayed signal supply path). At this time, the selection of the analog switch 41 is automatically performed. That is, since the connection between input channels 1ch to 4ch and output channels CH1 to CH8 is uniquely determined by the mode of use as described above, the control circuit 14 selects the mode and the output channel to be monitored. According to the table below, specify the input channel, output the control signal,
Turn on the corresponding one of the analog switches 41 to output the signal of the corresponding input channel (original audio signal) and supply it to the left channel unit 44l of the headphone 44 (this supply path corresponds to the original audio signal signal supply path). ).

[Table] Such an input channel switching operation by the control circuit 14 can be achieved by configuring the logic shown in FIG. 7 using software. The original sound signal output from the analog switch 41 is supplied to the left channel unit 44l of the headphone 44 via the amplifier 45. Therefore,
The headphone 44 has a right channel unit 44.
The delayed signal of the selected output channel is supplied to the left channel unit 44l, and the corresponding original sound signal is supplied to the left channel unit 44l. This allows the delay effect to be confirmed by the difference in sound heard by the left and right ears. In particular, since the distance from the sound source to the ear is short, the delay time is not affected by distance, and the delay time can be set to a very small amount (several milliseconds).
It can be clearly identified even within 10 msec).
Furthermore, by changing the set value of the delay time, you can listen and compare the differences in the delay effect due to subtle differences in the delay time. Note that, in this embodiment, the control circuit 14 as a delay time control circuit controls the delay time of each delay signal itself supplied to each output channel CH1 to CH8, as is clear from the above explanation. This is performed by selecting and controlling the delay time to be output for monitoring from among these output channels CH1 to CH8 via the analog switch 42. In addition, in the embodiment shown in FIG. 1, in addition to the monitor method (in/out method) that supplies the original signal and the delayed signal to the left and right headphone units 44r and 44l, respectively, the left and right headphone units 44r and 44l also have a delayed signal. It is now possible to select a method for supplying and monitoring signals (mono method). This selection is made using the keyboard 33, and if the mono method is selected, the control circuit 1
4, the analog switch 41 selects the delayed signal supplied from the signal line 46 and outputs it to the left and right headphone units 44r, 44.
44l also supply delayed signals. As explained above, according to the present invention, the original sound signal is supplied to one channel unit of the headphone via the original sound signal supply path, and the signal obtained by delaying the original sound signal in the delay circuit is sent to the other channel unit of the headphone. Since the delay effect can be confirmed by the difference between the sound heard by the left and right ears, the distance between the sound source and the ear becomes closer, eliminating the effect of distance on the delay time, and the delay effect is purely due to the delay circuit. Delay effects can be confirmed, and even very small delay times and delay time differences can be clearly identified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between write addresses and read addresses in each divided memory area in the signal delay device of FIG. 1, and FIG. A diagram showing the divided state of the memory in FIG. 1 in each mode,
4 is a diagram showing an equivalent circuit of the input/output connection state of the signal delay device of FIG. 1 in each mode, FIG. 5 is a flowchart showing the operation of the signal delay device of FIG. 1 in each mode, and FIG. Figures a, b, and c are for 1-in mode, 2-in mode, and 4-in mode, respectively.
A diagram showing the relationship between the write address and the read address in the mode, FIG. 7 is the control circuit 1 of FIG.
4 is a flowchart showing the input channel selection operation at the time of monitoring in step 4. 1-4...Input terminal, 14...Control circuit (delay time control circuit), 15...Memory (delay circuit), 15a-
15e...Memory division area, 25-32...Output terminal, 33...Keyboard (delay time setting means), 4
0...Monitor circuit, 44...Headphone, 44r...Right channel headphone unit, 44l...Left channel headphone unit, 1ch to 4ch...Input channel, CH1 to CH8...Output channel.

Claims (1)

[Claims] 1. A delay circuit that can generate a delayed signal of an input original audio signal by changing the delay time, an output terminal that outputs the delayed signal generated by this delay circuit, and each left and right channel. an original audio signal supply path that supplies the original audio signal to one channel unit of the headphone; and a delayed signal that supplies the delayed signal generated in the delay circuit to the other channel unit of the headphone. a supply path; a delay time setting means for setting a delay time of a delayed signal generated by the delay circuit and supplied to the delayed signal supply path; and a delayed signal generated by the delay circuit and supplied to the delayed signal supply path. a delay time control circuit for controlling the delay time of the signal to the delay time set by the delay time setting means.