JPH05502545A - Electronic devices with field emission devices - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Field emission device technology using single crystal silicon layer This invention generally relates to cold cathode field emission devices. field emission devices) and more specifically The present invention relates to a cold cathode field emission device formed on a non-chamfered surface of a support substrate layer.

Background of the invention Cold field emission devices (FEDs) are known in the art.

Such cold cathode field emission devices use a geometry with a small radius of curvature for the purpose of emitting electrons. Emitter electrodes with discrete discontinuities are used.

The prior art teaches that FEDs can be formed by a number of preferred methods. Ru. One such method taught by the prior art is to use emitter electrodes or support substrates. The emitter electrode is disposed on the surface of the plate material, while another method is to directly remove the emitter electrode from the supporting substrate material. using selective semiconductor processes to form the .

Many obstacles to optimal utilization of FEDs are associated with these and other prior art methods. related to. One such obstacle is that the control or restriction of release is within the FED structure. This is something that cannot be easily implemented. Furthermore, prior art methods Transistor devices are typically formed in the substrate material within the structure in which the FED is placed. and is limited to.

Therefore, the emission current limiting mechanism can be easily introduced and can be connected in a single position other than the substrate material. There is a need for a FED formation method that allows for the formation of crystalline silicon transistors. .

Summary of the invention These needs and others are substantially addressed by the FED formation method disclosed herein. I'm satisfied. A field emission device is provided, the device comprising a substrate, a small portion of one side of the substrate. an insulating layer disposed on at least a portion of the insulating layer; a single-crystal silicon layer disposed on at least a portion of one surface of the single-crystal silicon layer; with an emitter installed.

In one embodiment, the emitter electrode(s) are as described above. ) is disposed on one surface of the single crystal silicon layer.

In other embodiments of the invention, the gate electrode(s) is made of single crystal silicon. It is formed by selectively doping the impurity layer.

In yet another embodiment, a conductive gate material is provided on one side of the single crystal silicon layer. will be placed.

In yet another embodiment of the invention, the single crystal silicon layer is selectively patterned. is used to limit FED emissions.

In yet another embodiment, the single crystal silicon layer is selectively doped with impurities. pinged.

In yet another embodiment of the invention, the transistor device(s) Formed in single crystal silicon layer(s).

Brief description of the drawing From FIG. 1A to FIG. 1L, each step of manufacturing the first embodiment of the present invention is shown. Figure 3 is a series of side views of the resulting structure;

2A to 2G show each step of manufacturing the second embodiment of the present invention. Figure 3 is a series of side views of the resulting structure;

3A to 3D illustrate each step of manufacturing the third embodiment of the present invention. Figure 3 is a series of side views of the resulting structure;

From FIG. 4A to FIG. 4B, each step of manufacturing the fourth embodiment of the present invention is shown. Figure 3 is a series of side views of the resulting structure;

5A to 5D illustrate each step of manufacturing the fifth embodiment of the present invention. Figure 3 is a series of side views of the resulting structure;

FIG. 6 is a side view of a structure forming a sixth embodiment of the invention.

Figures 7A through 7D result from the second method of forming a single crystal silicon layer. Figure 3 is a series of side views of the structure;

Figures 8A to 8B result from the third method of forming a single crystal silicon layer. Figure 3 is a series of side views of the structure;

9A to 9E illustrate each step of manufacturing the seventh embodiment of the present invention. Figure 3 is a series of side views of the resulting structure;

FIG. 10 is a side view showing an eighth embodiment of the present invention.

FIG. 11 is a side view showing a ninth embodiment of the present invention.

FIG. 12 is a side view showing a tenth embodiment of the present invention.

FIG. 13 is a side view showing an eleventh embodiment of the present invention.

FIG. 14 is a side view showing a twelfth embodiment of the present invention.

FIG. 15 shows multiple field emission devices using preferentially doped layers of single crystal silicon. FIG.

Figure 16 shows multiple electric fields using multiple selectively doped layers of single crystal silicon. FIG. 3 is a top view of the ejection device.

FIG. 17 is a side view showing a first embodiment of a plurality of field emission devices.

FIG. 18 is a side view showing a second embodiment of a plurality of field emission devices.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS FIG. 1A shows a substrate (101) forming a support base, with an electric current on the support base. A field emitting device is formed. An insulating layer (102) is thermally insulated on the surface of the substrate (101). grown or deposited (Figure 1B). This is followed by the application of a mask layer (103). (Figure 1C). The mask layer (103) is selectively exposed, developed and patterned to provide an opening exposing a surface of the underlying insulating layer (102). (Figure 1D). The insulating layer is etched and the mask layer (103) is patterned. of the insulating layer (102) in the area of the insulating layer (102) exposed by the the insulating material until a part of the surface of the underlying substrate (101) is exposed. selectively removed (Figure 1E). This is followed by removal of the mask layer (103). (Figure 1F).

The structure thus formed consists of a substrate with silicon preferentially exposed (101 ) on which silicon can be deposited easily and then preferentially deposited on single-crystal silicon. layer (IOC) (Figure 1G). Such an environment is typically Typical, in part, silane or di-s i1ane) Contains gas. A monocrystalline silicon layer is typically It is grown to a thickness on the order of micrometers (μm). Single crystal silicon layer (10 Following the growth of step 4), an insulating layer (105) is formed on the surface of the single crystal silicon layer (104). It is provided by thermal oxidation or by deposition of a suitable insulating material (FIG. 1H). Next mass A protective layer (106) is deposited on the surface of the insulating layer (105) (FIG. 1I) and subsequently exposed. exposed, developed and patterned (Figure 1J). Mask layer (106) The patterning selectively exposes surface areas of the underlying insulating layer (105). . An etching step is performed to selectively modify the planes of the underlying single crystal layer (104). The insulating layer (105) is removed to the extent that portions are exposed (FIG. 1K). after that , the emitter (107) is technically placed on the exposed surface of the monocrystalline silicon layer (104). It is formed by well known methods (Figure 1L).

This results in the formation of an FED, in which the emitter electrode is further away from the substrate (101). It is present on the single crystal silicon layer (104). The single crystal silicon layer (104) is In the region where the crystalline silicon layer (104) penetrates the intervening insulating layer (102) Selective local processing of single crystal silicon layer (104) Tsuching or selective local processing By performing oxidation, it is possible to completely electrically insulate from the substrate (101). Ru.

2A to 2G are a series of steps for realizing the second embodiment of the FED. shows the top. In Figure 2A, a substrate (201) is shown. Substrate (20 The insulating layer (202) located below the plane of 1) Implantation of ions (204) having . As a result of this implantation, an electric current is disposed on the surface of the insulating layer (202) and from the substrate (201). A gastically insulated monocrystalline silicon layer (203) results. This injection process is simple. This results in lattice defects in the crystalline silicon layer (203), which By annealing the silicon layer (203), it is similar to that of the single crystal silicon layer (203). It is repaired by producing a lower defect density (Figure 2C). after that , FED as shown in Figures 2D or 2G and see Figures 1H to 1L. and is formed as described above. However, in this example, a simple The crystalline silicon layer (203) requires selective local etching or selective local oxidation. It is effectively completely insulated from the substrate (201) without any physical properties. ``Third aspect of the present invention Examples can be obtained by repeating the steps described above with respect to Figures 1A to 1H. Realized. This realization process involves placing a gate electrode (306) on the surface of the insulating layer (105). Continued by deposition (Figure 3A). Following this, masking layer C30 7) is formed on the surface of the gate electrode (306) (Figure 3B). Mask layer (30 7) is then exposed, developed and patterned, and an etching step is performed to selectively expose a part of the surface of the underlying single crystal silicon layer (104). Gate electrode (306) material and insulating layer (105) material are removed to (Figure 3C). The emitter (308) then uses methods well known in the art to It is formed on the exposed surface of the single crystal silicon layer (104).

A fourth embodiment of the invention combines the steps described above with respect to FIGS. 2A-2D. This is achieved by repeating the process.

Following this, a gate electrode (406) is deposited on the surface of the insulating layer (205). (Figure 4A). The implementation of the device is as described above with respect to Figures 30 and 3D. and an emitter (308) disposed on the monocrystalline silicon layer (203). The result is a device as shown in FIG. 4B.

A fifth embodiment is implemented as an FED with more than one single crystal silicon layer. Ru. This realization process first proceeds as described for Figures 1A to 1K. . The structure is then formed by selecting an underlying monocrystalline silicon layer (507) in which silicon is preferentially the underlying layer. selectively placed in an environment where it deposits on exposed surfaces (FIG. 5A). Mask layer (50 8) is deposited on the surface of the monocrystalline silicon layer (507) (FIG. 5B). Subsequent ma Exposure, development, and patterning of the silicon layer (508), single crystal silicon layer (50 7) etching of the selectively exposed layers and etching of the selectively exposed insulating layers ( The etching of 105) selectively exposes the surface of the single crystal silicon layer (104). Figure 5C). Subsequently, the emitter (509) is exposed to the single crystal silicon layer (104). (FIG. 5D) using methods well known in the art. each The monocrystalline silicon layer is insulated to expose the underlying material on which the insulating layer is disposed. It can be seen that it can be formed by selectively etching the layers. to do so A subsequent structure of an insulator layer and a monocrystalline silicon layer can then be formed on the substrate.

A sixth embodiment of the invention implements the steps described above with respect to FIGS. 2A to 2C. First, it is achieved through repetition. The process of realizing this is shown in Figures 1H to 1J. and continuing the steps described above with FIGS. 5A-5D.

The second layer of monocrystalline silicon (507) (Figure 6) is the first layer of monocrystalline silicon (507) (Figure 6). 203), which can be effectively electrically insulated from a second layer of single crystal silicon. (507) extends through the insulating layer (105) selective local etching or selective local oxidation of the second layer (507). This can be achieved by

FIG. 7A shows a seventh embodiment of the invention realized by a substrate (701), which An insulating layer (702) is disposed on the substrate (701), and the insulating layer is in contact with the underlying substrate (70). 1) Select to preferentially expose a part of the surface selectively grown, selectively developed, or etched. This structure is based on the substrate (7 01) is placed in an environment where silicon is preferentially deposited on the partially exposed surfaces of the extending in the plane of the edge layer (702) and at least partially insulating layer (702) selectively Insulating layers that are not etched or selectively grown or deposited A protrusion (703) of single crystal silicon that partially occupies the same volume as (702) (Figure 7B). Subsequently, the silicon layer (704) is placed on the surface of the insulating layer (702). (FIG. 7C). this Subsequently, the silicon layer (703) is recrystallized to form a single crystal silicon layer (705). is generated (Figure 7D). Silicon for forming a single crystal silicon layer (705) Recrystallization of the con layer (703) involves techniques including thermal annealing and laser recrystallization. This can be done by any of the methods known above, and the purpose is to The underlying recrystallization pattern is increased by increasing the size and rearranging the lattice of the silicon layer (703). This is to correspond to that of the lattice of the recon layer (705).

FIG. 8A shows an eighth embodiment of the invention, in which the silicon layer (803) is insulating. deposited on the surface (802) and preferentially on the exposed portion of the surface of the substrate (801). ing. Subsequent recrystallization produces a structure with a monocrystalline silicon layer (804) ( Figure 8B).

9A to 9E are a series of steps for realizing the ninth embodiment of the present invention. Show step. FIG. 9A, formed by any of the methods described above. The structure is a bipolar transistor formed by diffusion in a single crystal silicon layer (903). It has a register (904). The insulating layer (905) is a single crystal silicon layer (903). is deposited on the surface and effectively covers the bipolar transistor (904). (Figure 9B). A mask layer (906) is then deposited on the surface of the insulating layer (905). (Figure 9C). Subsequently, selective exposure, development, and mask layer (906 ) patterning, and insulating layer (905), single crystal layer (903), and The insulating layer (902) is etched to selectively expose a portion of the substrate surface ( Figure 9B). The substrate (901,) is then exposed using methods well known in the art. An emitter (907) is formed on the surface. The device constructed in this way is Bipolar transistor device (904) formed in crystalline silicon layer (903) The monocrystalline silicon layer is not the substrate (901) and is a bipolar silicon layer. The transistor device (904) is located near the FED and is part of the same structure as the FED. It exists as.

FIG. 10 shows the electric potential present at least partially within the monocrystalline silicon layer (1002). A tenth embodiment of the present invention using a field effect transistor (1001) is shown. child The device configured as follows uses a field effect transistor formed in a single crystal silicon layer (1002). Ranjistor device! (1001) and single crystal silicon layer (1002). ) is not a substrate and the field effect transistor device (1001) is near the FED. It exists alongside and as part of the same structure as the FED.

Figure 11 shows a bipolar transistor formed in a single crystal silicon layer (1103). using a data storage device (1101) and placed on a single crystal silicon layer (1103). operably coupled to the collector of a bipolar transistor device (1101,). 11 shows an eleventh embodiment of the present invention having a FED gate electrode (1102).

Figure 12 shows a field effect transistor formed in a single crystal silicon layer (1203). using a device (1201) and disposed on a single crystal silicon layer (1203); operably coupled to the drain of the field effect transistor device (1201); A twelfth embodiment of the invention is shown having a FED gate electrode (1202).

Figure 13 shows a bipolar transistor placed in a single crystal silicon layer (1301). The single crystal silicon layer (1301) is doped with impurities. A thirteenth embodiment of the present invention is shown, in which the wafer is doped as follows. single crystal silicon layer (1301) can be formed as a bipolar transistor device by forming it in this way. (1302) functions as the collector and FED gate electrode.

Figure 1-4 shows a field effect transistor placed in a single crystal silicon layer (1402). The single-crystal silicon layer (1402) is made of impurities. A fourteenth embodiment of the present invention is shown, in which the wafer is doped with Single crystal silicon layer ( By configuring the field effect transistor device (1402) in this way, the field effect transistor device (1402) , 401) and as an FED gate electrode.

FIG. 15 shows an embodiment using multiple FEDs that are selectively electrically interconnected. FIG. 3 is a partial top view of the device (1,500). In this example, the emitter (1505) is formed, and the aperture (1503) is selectively formed into a geometrically shaped game. The individual electrodes (1504) are substantially circumferentially surrounded. The emmi The resistor (1505) is electrically connected to the selectively doped resistive region (1505). The selectively doped resistive region (1506) is formed of a single crystal silicon layer (1506). 1501) and operably selectively doped highly conductive strips (s tripe) (1502), and the selectively doped high conductivity Electrical conductivity strips are also placed in the monocrystalline silicon layer (1501). like this By configuring the device (1500) to It functions to have independently controlled electron emission.

Figure 16 shows how to obtain row and column (col, umn) addressing capabilities. selectively electrically interconnecting various electrodes of a number of FEDs of the device (1600); It is a top view which shows a means. In this example, the emitter (1603) is Connected to selectively doped high conductivity stripes (1602) in rows and thereby the emitter (1603) or the emitter (1603) that is not in the same column. They are electrically separated from each other. Selectively geometrically patterned gate electrode ( 1604) or electrically operatively connected to the high conductivity stripe (1601); The high conductivity stripes (1601) are formed by depositing a conductive or semiconducting material. Alternatively, it can be formed as a selectively doped region of a single crystal silicon layer.

With this configuration, the device (1600) can be connected to the device (1600'). provides a means for addressing individual FEDO rows and columns of multiple FEDs. make it possible.

FIG. 17 shows a selectively doped resistive region (1706) in side cross-sectional view form. ) shows a plurality of FEDs selectively operably interconnected using a . This implementation In the example, each row of emitters (1708) is an individual selectively doped individually operably connected to and disposed over the resistive region (1706); , the selectively doped resistive region (1706) is connected to a single crystal silicon layer (1706). It is located at 7). The selectively doped resistive region (1706) operably coupled to selectively doped high conductivity stripes (1705); , the selectively doped high conductivity stripes (1705) are also single crystal silicon. It is arranged in the recon layer (1707). A plurality of FED has independent column control of same column emitters (1708) and multiple emitters (1708) provides a means for independent limitation of electron emission from each.

FIG. 18 is a side sectional view of a plurality of FEDs according to one embodiment of the present invention. Emi (1806) is a substantially uniformly doped single crystal silicon layer (180). 4) It is cast above. the substantially uniformly doped single crystal silicon layer; (1804) is implanted with impurities by any known method of semiconductor doping. The substantially uniformly doped single crystal silicon layer (1804) is formed by a plurality of etching layers. to effectively limit electron emission from each of the mitters (1806) in an independent manner. function as a distributed resistance element.

For those familiar with the art and familiar with the known configurations of FEDs, each emitter should be It will be readily apparent that shapes other than the conical shape shown can be formed. some Other emitter shapes include wedges of varying length and straight or curved Including sticky items. For such emitter structures, the associated apertures are non-circular columnar and shall conform substantially symmetrically to the elongated shape of the emitter. can be done. Furthermore, the method described above can be applied to two or more monocrystalline silicon layers and / or to provide a field emission device with more than one electrode in addition to the emitter. It can be expanded.

Such field emission devices are typically commonly known and described in the literature. This may be in the form of a board or pentote device.

Fig, 14 1c+7',○ abstract Various field emission devices (308) using a non-substrate layer (203) of single crystal silicon and a field emission device structure are provided. A non-substrate layer (203) of single crystal silicon By using improved emission control is achieved and improved performance control The device (406) can be formed within the device structure.

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Claims (3)

[Claims] 1. A field emission device, substrate, an insulating layer disposed on at least a portion of one surface of the substrate; A single crystal silicon layer partially disposed on top of the an emitter disposed on at least a portion of one surface of the single crystal silicon layer; A field emission device comprising: 2. A method of forming a field emission device comprising: (A) providing a substrate; (B) forming an insulating layer on at least a portion of one surface of the substrate; (C) forming a single crystal silicon layer on at least a portion of one surface of the insulating layer; ,and (D) an emitter disposed on at least a portion of one surface of the single crystal silicon layer; 1. A method of forming a field emission device, comprising: forming a field emission device. 3. An electronic device, A field emission device having an emitter, the emitter of the field emission device being a single crystal silicone. disposed on at least a portion of one surface of the silicon layer, the single crystal silicon layer is an insulating layer; disposed on at least a portion of one side of the monocrystalline silicon eyebrow. a transistor partially disposed and operably coupled to the emitter of the field emission device; transistor device, An electronic device comprising: