JPS6226857A - Gate turn-off thyristor - Google Patents
Gate turn-off thyristorInfo
- Publication number
- JPS6226857A JPS6226857A JP16590585A JP16590585A JPS6226857A JP S6226857 A JPS6226857 A JP S6226857A JP 16590585 A JP16590585 A JP 16590585A JP 16590585 A JP16590585 A JP 16590585A JP S6226857 A JPS6226857 A JP S6226857A
- Authority
- JP
- Japan
- Prior art keywords
- region
- emitter
- regions
- base region
- ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 2
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 7
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0839—Cathode regions of thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は電力分野等に適用するゲートターンオフサイリ
スタに関し特にそのエミッタ構造を改善するものである
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a gate turn-off thyristor applied to the power field, etc., and particularly to improving the emitter structure thereof.
従来ゲートターンオフサイリスタのエミッタ構造として
はその周囲長を大きくしてその素子特性の向上を図って
いる。このＧＴＯを第３図により説明すると、この陽極
側はいわゆるアノードショート型が採用され、しかも陽
極電極とのオーミック接触を図るためにＰ導電型領域は
Ｐ′″導電型領域との２重構造が一般的である。その製
造工程としてはＰを１０”ａｔｏｍｓ／ｃｃ程度含有し
たＮ−型半導体基板（２０）を用意しその両表面から不
純物としてＢを導入して夫々の表面濃度をＩ Ｘ ＬＯ
”ａｔｏｍｓ／ｃｃ程度とする。この場合このＧＴ○素
子の陽極となる表面は前述のようにアノードショート構
造とするためにＢ導入を拡散マスクを利用して選択的に
実施し、更にこの陽極側のＰ導電型領域（２１）には電
極との良好なオーミック接触を得るためにＢを更に深さ
４〜５μ導入して７ Ｘ １０”又はＩ Ｘ １０１ｇ
ａｔｏｍｓ／ｃｃ程度の表面濃度を示すＰ＋導電型領域
（２２）を設ける。このＰ＋導電型領域間に位置するＮ
−型半導体基板（２０）と前述のＢ導入によってＧＴＯ
のベース領域（２３）として機能するＰ導電型領域にも
選択的にＰを表面濃度が１０”ａｔｏｍｓ／ｃｃ位導入
してＮ＋導電型領域（２４）及び（２５）を形成する。Conventionally, the emitter structure of a gate turn-off thyristor has been designed to increase its peripheral length in order to improve its device characteristics. To explain this GTO with reference to Fig. 3, the anode side adopts a so-called anode short type, and in order to make ohmic contact with the anode electrode, the P conductivity type region has a double structure with the P'' conductivity type region. This is a common manufacturing process. An N-type semiconductor substrate (20) containing about 10" atoms/cc of P is prepared, and B is introduced as an impurity from both surfaces of the substrate to increase the concentration of each surface to I
``atoms/cc.'' In this case, the surface of the GT○ element that will become the anode is selectively introduced using a diffusion mask to create an anode short structure as described above, and furthermore, the anode side is In order to obtain good ohmic contact with the electrode, B is further introduced into the P conductivity type region (21) to a depth of 4 to 5 μm, and the area is 7 x 10" or I x 101 g.
A P+ conductivity type region (22) having a surface concentration of about atoms/cc is provided. N located between this P+ conductivity type region
- type semiconductor substrate (20) and the above-mentioned B introduction, GTO
Also, P is selectively introduced into the P conductivity type region functioning as the base region (23) to form N+ conductivity type regions (24) and (25) at a surface concentration of about 10'' atoms/cc.
このベース領域（２３）に設置したＮ＋導電型領域（２
４）はＧＴ○素子のエミッタ領域として機能し、Ｎ−型
半導体基板（２０）の地表面に形成した深さ１０μ程度
のＮ＋導電型領域（２５）は前述のアノードショート構
造を得るためのものである。N+ conductivity type region (2) installed in this base region (23)
4) functions as the emitter region of the GT○ element, and the N+ conductivity type region (25) with a depth of about 10μ formed on the ground surface of the N− type semiconductor substrate (20) is for obtaining the above-mentioned anode short structure. It is.
この陽極として動作するこのＮ−型半導体基板（２０）
の地表面に、導電性金属であるＡＲを蒸着して陽極′北
極（２６）を完成する。This N-type semiconductor substrate (20) operates as this anode.
AR, which is a conductive metal, is deposited on the ground surface to complete the anode' north pole (26).
前記エミッタ領域の構造としてはその周囲長を大きくす
る為にいわゆるマルチエミッタもしくはリングエミッタ
構造が採用されており、第３図にはこの中の単一のリン
グエミッタ構造を示した。As the structure of the emitter region, a so-called multi-emitter or ring emitter structure is adopted in order to increase its peripheral length, and FIG. 3 shows a single ring emitter structure.
このリング状のエミッタ領域（２４）の中心部分に露出
するＰベース領域（２３）部分に導電性金属層を被着し
てゲート電極（２７）を形成する。又このエミッタ領域
（２４）にも導電性金属を堆積してエミッタ電極（２８
）を他の露出したＰベース領域（２３）には珪素酸化物
等の絶縁物層（２９）を積層してＧＴＯ素子を完成する
。A conductive metal layer is deposited on the P base region (23) exposed at the center of the ring-shaped emitter region (24) to form a gate electrode (27). A conductive metal is also deposited on this emitter region (24) to form an emitter electrode (28).
) and an insulating layer (29) such as silicon oxide is laminated on the other exposed P base region (23) to complete the GTO element.
マルチエミッタ構造をもつＧＴＯにあっては、このエミ
ッタ領域がベース領域に囲まれているためにこの素子の
ターンオフ時にエミッタ領域の中央部分に電流集中が起
る難点がある。A GTO having a multi-emitter structure has the disadvantage that current concentration occurs in the center of the emitter region when the device is turned off because the emitter region is surrounded by the base region.
一方シングルリングエミッタ構造ではその周辺長がこの
マルチエミッタ構造より長大にできず、Ｇ−に逆バイア
ス時に発生する電流集中による破壊耐量については不利
となり、更にエミッタ領域が全体として大きくなるため
に電荷を引き抜くことが容易でなく、ターンオフ時の下
降時間ｔｆも長くなる難点がある。On the other hand, the single ring emitter structure cannot have a longer peripheral length than the multi-emitter structure, and is disadvantageous in terms of breakdown resistance due to current concentration that occurs when G- is reverse biased.Furthermore, the emitter region becomes larger as a whole, which reduces the charge It is difficult to pull out, and the falling time tf at turn-off is also long.
本発明はマルチエミッタ構造をもつゲートターンオフサ
イリスタがターンオフする場合、電流集中がエミッタ領
域への魚巣中となるのを改善する。The present invention improves current concentration in the emitter region when a gate turn-off thyristor with a multi-emitter structure is turned off.
この目的を達成するため本発明に係るＧＴＯでは、中央
部にベース領域をもつリングエミッタを対称的に位置に
形成したマルチエミッタ構造を採用し、このリングエミ
ッタの中心部分に露出したＰ−ベース領域にゲート電極
を設けると共にリングエミッタ内に位置するベース領域
を浮遊ベース領域として利用する。In order to achieve this object, the GTO according to the present invention employs a multi-emitter structure in which ring emitters having a base region in the center are formed in symmetrical positions, and a P-base region exposed in the center of the ring emitter. A gate electrode is provided in the ring emitter, and a base region located within the ring emitter is used as a floating base region.
第１図〜第２図により本発明を詳述する。 The present invention will be explained in detail with reference to FIGS. 1 and 2.
Ｐを１０”ａｔｏｍｓ／ｃｃ程度含有した厚さ２００
ｐ ｍ位のＮ−型半導体基板（１）を用意し、その両表
面から不純物としてＢを導入して夫々の表面濃度を約１
×１０１０１Ｂａｔｏ／ｃｃとし、Ｘｊを２０μｍ〜３
０μｍとする。このＧＴＯにあってはその陽極をアノー
ドショート構造とするためＮ−型半導体基板（１）の−
表面には拡散マスクを所定位置に設けてＰ壁領域（３）
を選択的に形成する。更に後述する陽極電極との良好な
オーミック接触を得るためにこのＰ壁領域（３）に、更
にＢを４〜５μｍ導入してその表面濃度を７ Ｘ １０
”乃至Ｉ Ｘ １０１ｇａｔｏｍｓ／ｃｃとするピ領域
（４）を設は前述のＢ導入によってＮ−型半導体基板（
１）表面にも厚さ約２０〜３０μｍのＰ壁領域（２）が
形成され。Thickness 200 containing about 10”atoms/cc of P
An N-type semiconductor substrate (1) of about pm and m is prepared, and B is introduced as an impurity from both surfaces of the substrate to make the surface concentration of each about 1.
x10101Bato/cc, Xj is 20μm~3
It is set to 0 μm. In this GTO, since the anode has an anode short structure, the -
A diffusion mask is provided at a predetermined position on the surface to cover the P wall area (3).
selectively formed. Furthermore, in order to obtain good ohmic contact with the anode electrode, which will be described later, B is further introduced into this P wall region (3) to a thickness of 4 to 5 μm, and its surface concentration is increased to 7×10
By introducing B as described above, a pin region (4) with a conductivity of 101gatoms/cc is formed in the N-type semiconductor substrate (
1) A P wall region (2) with a thickness of about 20 to 30 μm is also formed on the surface.
ＧＴＯ素子のベース領域として機能する。It functions as a base region of the GTO element.
次に前記ピ型領域（４）間に位置するＰ壁領域（３）な
らびにベース領域として機能する他のベース領域（２）
ニ共ニｘｊ１０μ程度（７）Ｎ＋領領域５） （６）を
同時に形成する。この同時形成に当ってはＰを導入して
それぞれの表面濃度をほぼ１０”ａｔｏｍｓ／ｃｃとし
てベース領域（２）に形成したＮ＋領領域６）はＧＴＯ
素子のエミッタとして機能させる。Ｐ＋領域（４）及び
Ｎ＋領領域５）が互に隣接して配置された表面には、導
電性金属、ｌを堆積して陽極電極（７）を形成すると共
に、Ｐ＋領域（４）とＮ＋領領域５）を、アノードショ
ート構造とする。Next, a P wall region (3) located between the P-shaped regions (4) and another base region (2) functioning as a base region.
(7) N+ region 5) and (6) are formed at the same time. In this simultaneous formation, the N+ region 6) formed in the base region (2) by introducing P and setting the respective surface concentration to approximately 10"atoms/cc is GTO.
Function as an emitter of the element. A conductive metal, l, is deposited on the surface where the P+ region (4) and the N+ region 5) are arranged adjacent to each other to form an anode electrode (7), and the P+ region (4) and the N+ region 5) are arranged adjacent to each other. The region 5) has an anode short structure.
ＧＴＯ素子のエミッタとして機能するＮ＋領領域６）は
第１図及び第２図に示すようにリングエミッタ構造をも
ち、しかもＰ型ベース領域（２）の網目状位置に形成さ
れる。従ってその中央にはＰ型ベース領域（８）が点在
する形状となる。The N+ region 6), which functions as an emitter of the GTO element, has a ring emitter structure as shown in FIGS. 1 and 2, and is formed in a mesh-like position in the P-type base region (2). Therefore, the shape is such that P-type base regions (8) are scattered in the center.
このＰ型ベース領域（８）・・・及び他のＰ型ベース領
域（２）は何れも絶縁物層（９）を被覆して安定化層と
しても機能させる。These P-type base regions (8)... and other P-type base regions (2) are both covered with an insulating layer (9) to function as a stabilizing layer.
一方、Ｎ型リングエミッタ領域（６）・・・には、導電
性金属ＡＱを堆積してエミッタ電極（１０）を設けるが
、この導電性金属層を他のＰ型ベース領域を被覆する絶
縁物層（９）に積層延長してこの半導体表面端にてパッ
ド（１１）として他部品との接続可能とする。次にゲー
ト電極（１２）について説明する。On the other hand, the N-type ring emitter region (6)... is provided with an emitter electrode (10) by depositing a conductive metal AQ. The layer (9) is laminated and extended so that it can be connected to other components as a pad (11) at the end of the semiconductor surface. Next, the gate electrode (12) will be explained.
リングエミッタ領域（６）・・・内に位置するＰ型ベー
ス領域（８）以外の他のＰ型ベース領域（２）において
は互に隣接するエミッタ領域か等距離にある部分に位置
する絶縁物層（９）・・・部分を公知の写真食刻法によ
って開孔して導電性金属ＡＱを堆積してベースコンタク
ト即ちゲート電極（１２）・・・を設け、更に前記絶縁
物層（９）にＡＱを延長配線してパッド（１１）とは離
れて位置する半導体表面端に集合させてパッド（１３）
を設は他部品との接続可能としてＧＴＯを完成する。な
お、このゲート電極（１２）を形成するに当っては半導
体表面端に最も近接する位置第１図に示したＡ領域内に
も設ける方がより確実に電流集中が回避できる。In other P-type base regions (2) other than the P-type base region (8) located within the ring emitter region (6)...insulators located at the same distance from adjacent emitter regions. A hole is opened in the layer (9) by a known photolithography method and a conductive metal AQ is deposited to form a base contact, that is, a gate electrode (12), and then the insulating layer (9) is formed. AQ is extended and wired to the edge of the semiconductor surface, which is located away from the pad (11), to form the pad (13).
The GTO is completed by making it possible to connect it with other parts. Incidentally, when forming this gate electrode (12), current concentration can be more reliably avoided if it is also provided in the area A shown in FIG. 1 at a position closest to the edge of the semiconductor surface.
本発明に係るＧＴ○素子にあっては、複数のリングエミ
ッタ領域を網の目状に形成して、その周辺長を増大する
と共に、その内側にはＰ−ベース領域を配置すると共に
絶縁物層を形成する。In the GT○ element according to the present invention, a plurality of ring emitter regions are formed in a mesh shape to increase the peripheral length, and a P-base region is arranged inside the ring emitter region, and an insulating layer is formed. form.
更にゲート電極を隣接するリングエミッタ領域と等距離
の位置に設けたので、リングエミッタの外周より始まる
電荷の引抜きは中央部分に存在する絶縁したＰ−ベース
領域の存在によってほぼ完全に行われて電流集中を確実
に緩和できた。Furthermore, since the gate electrode is provided at a position equidistant from the adjacent ring emitter region, the extraction of charge starting from the outer periphery of the ring emitter is almost completely carried out due to the presence of the insulated P-base region in the central portion, and the current flow is reduced. I was able to definitely ease my concentration.
第１図は本発明に係るＧＴＯの上面図、第２図は、その
一部の断面図、第３図は従来のＧＴＯ断面図である。FIG. 1 is a top view of a GTO according to the present invention, FIG. 2 is a sectional view of a portion thereof, and FIG. 3 is a sectional view of a conventional GTO.
Claims (1)
体基板と、この頂面に位置するある導電型を示すベース
領域と、このベース領域の網目状に位置する表面部分か
ら内部に向けて異なる導電型をもつ不純物を導入して形
成するリングエミッタ領域と、この各リングエミッタ領
域に形成し電気的に互に接続するエミッタ電極と、この
各リングエミッタ領域内に位置する前記ベース領域及び
他のベース領域を被覆する絶縁物層と、前記半導体基板
底面に形成する陽極電極と、互に隣接する前記リングエ
ミッタ領域から等距離する前記他のベース領域部分に設
け、これらを互に電気的に接続するゲート電極とを具備
することを特徴とするゲートターンオフサイリスタ。A semiconductor substrate formed by alternately stacking three semiconductor layers of different conductivity types, a base region located on the top surface exhibiting a certain conductivity type, and a surface portion of the base region located in a mesh pattern that differs inward from the surface portion of the base region. a ring emitter region formed by introducing impurities having a conductivity type; emitter electrodes formed in each ring emitter region and electrically connected to each other; and the base region and other regions located in each ring emitter region. An insulator layer covering a base region, an anode electrode formed on the bottom surface of the semiconductor substrate, and an anode electrode formed on the other base region portions equidistant from the adjacent ring emitter regions, and electrically connected to each other. A gate turn-off thyristor comprising a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16590585A JPS6226857A (en) | 1985-07-29 | 1985-07-29 | Gate turn-off thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16590585A JPS6226857A (en) | 1985-07-29 | 1985-07-29 | Gate turn-off thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6226857A true JPS6226857A (en) | 1987-02-04 |
Family
ID=15821223
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16590585A Pending JPS6226857A (en) | 1985-07-29 | 1985-07-29 | Gate turn-off thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6226857A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644149A (en) * | 1994-06-10 | 1997-07-01 | Asea Brown Boveri Ag | Anode-side short structure for asymmetric thyristors |
-
1985
- 1985-07-29 JP JP16590585A patent/JPS6226857A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5644149A (en) * | 1994-06-10 | 1997-07-01 | Asea Brown Boveri Ag | Anode-side short structure for asymmetric thyristors |
| CN1040710C (en) * | 1994-06-10 | 1998-11-11 | 亚瑞亚·勃朗勃威力有限公司 | Short circuit structure on side of positive pole of unsymetric silicon brake tube |
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