JPH0550235B2 - - Google Patents

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a control device for a rotating body, particularly a control device for a rotating body when changing the motor rotation speed in a capstan motor of a magnetic recording/reproducing device (hereinafter referred to as VTR). This relates to a control device.

1. Configuration of conventional example and its problems FIG. 1 is a block diagram of a control device for a capstan motor in a conventional VTR. In FIG. 1, a signal obtained by a frequency generator 2 (hereinafter referred to as FG) provided in a capstan motor 1 is input to a digital frequency discriminator 4 via a frequency divider 3, and the digital frequency discriminator The output of the converter 4 is input to a digital-to-analog conversion circuit 5 (hereinafter referred to as a D/A conversion circuit) to obtain an error signal corresponding to the rotational speed of the capstan motor 1. The error signal thus obtained is subjected to gain compensation or phase compensation in the compensation circuit 6, and then input to a motor drive circuit 7 (hereinafter referred to as a drive circuit) to drive the capstan motor 1.

By the way, there are multiple tape speed modes for VTRs, namely, the capstan motor rotates at a speed of 1/N (N is an integer) of the standard speed, making it possible to extend the recording time. is publicly known. Hereinafter, a VTR having two recording time modes, a standard mode and an N times mode, will be explained as an example. FG signal frequency in standard mode
f _O , and the division ratio of the frequency divider 3 is the standard mode and N
Assuming that it is constant in the double mode, the sampling frequency in the digital frequency discriminator becomes f _O in the standard mode and f _O /N in the N times mode. Generally, the gain K _d of a digital frequency discriminator is inversely proportional to the square of the sampling frequency, so the gain in standard mode is K _dO and the gain in N times mode is K _dN .
Then, K _dN = N ²・K _dO (1). If this continues, the round transfer function will be ^N2 times higher in the N-fold mode than in the standard mode, so it is necessary to compensate for the round transfer function.

Furthermore, if the frequency division ratio of the frequency divider 3 is set to N:1 in the standard mode and the N times mode, the sampling frequency will be the same as f _O /N in both modes, and the gain of the digital frequency discriminator 4 will be the same. However, since the frequency is divided by N by the frequency divider 3 in the standard mode, the open loop transfer function will be N times higher in the N times mode than the standard mode, so it is still necessary to compensate the open loop transfer function.

In the above case, the compensation circuit 6 shown in FIG. 1 also performs gain compensation. Generally, the D/A converter circuit 5 in FIG. 1 has a pulse width modulation output (hereinafter referred to as
Since the PWM output (referred to as PWM output) is converted into a DC voltage by a low-pass filter, the gain is increased by the compensation circuit 6 in the standard mode, so the carrier wave component of the PWM output is also amplified, and in the drive circuit 7,
There is a phenomenon in which a portion where the motor drive current does not flow occurs, resulting in a problem that the controllability of the capstan motor 1 deteriorates. Also, generally the compensation circuit 6
There is also the problem that there are variations in gain values because they are constructed from analog circuits.

OBJECTS OF THE INVENTION The present invention is intended to alleviate and eliminate the conventional problems as described above, and is aimed at obtaining stable tape running even when the tape speeds are different between the standard mode and the N times mode.

Structure of the Invention The present invention provides a digital frequency discriminator that detects an error in the frequency of an input signal with respect to a reference frequency by counting clock pulses existing in a period of K times a half cycle (K: natural number) of the input signal. By switching the frequency of the clock pulse between the standard mode and the N-fold mode, the open-loop transfer function in both modes is compensated, and the increase in the carrier wave component of the PWM output due to gain compensation in the compensation circuit is prevented as much as possible. A control device is provided.

DESCRIPTION OF EMBODIMENTS An embodiment of the rotation control device of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a digital frequency discriminator in a control device for a rotating body according to the present invention, where 8 is a preset value generation circuit, 9 is an a-bit binary counter (a: positive integer ), 10 is a b-stage gate group (b: positive integer, b≦a), 11 is a b-bit latch circuit,
12 is a count value detection circuit, 13 is a timing pulse generation circuit, 14 is a programmable frequency divider, and 15 is a
It is an AND gate circuit.

FIG. 3 is a waveform diagram of each part of the digital frequency discriminator of FIG. 2, and the operation of the digital frequency discriminator of FIG. 2 will be explained with reference to FIG. In the embodiment of the present invention, it is assumed that the frequency division ratio of the frequency divider 3 in FIG. 1 is constant in both the standard mode and the N times mode, and the case where N=2 will be described. Therefore, when the rotational speed of the rotating body is at the set speed, the sampling frequency in the digital frequency discriminator is set to the standard mode f _O (Hz)
Then, the double mode becomes f _O /2 (Hz). In FIG. 3, g represents the counting operation of the a-bit binary counter 9, k represents the output of the b-stage gate group 10, and l represents the output of the b-bit latch 11 in analog form.

The timing pulse generation circuit 13 uses the clock pulse a to generate a signal e synchronized with an input signal d with a period corresponding to the rotational speed of the rotating body to be controlled, and a signal f having a phase difference of a certain time from the signal e. do. This signal f is a preset pulse for presetting the count value of the a-bit binary counter 9 to the output value of the preset value generation circuit 8, and the signal e is a preset pulse for presetting the count value of the a-bit binary counter 9 to the output value of the preset value generation circuit 8. This is a latch pulse for storing the count value of the lower b bits of the advance counter 9 in the b bit latch circuit 11.

In FIG. 3, the mode is switched between the standard mode and the double mode by pointing at point A, and the frequency division ratio of the programmable frequency divider 14 and the preset value generation circuit 8 are The output value of is being switched. That is, in the standard mode, the frequency division ratio of the programmable frequency divider 14 is 1, the output value of the preset value generation circuit 8 is NP1, and in the 2x mode, the frequency division ratio of the programmable frequency divider 14 is 1. The ratio is 4, and the preset value generation circuit 8
The output value of is NP2.

In the counting operation of the a-bit binary counter 9, as shown in g in FIG.
Immediately after presetting to NP2, counting is started by the frequency-divided second clock pulse c. The frequency of the second clock pulse c is f _c1 = f _ck (Hz) in the standard mode, and f _c2 = f _ck /4 in the double mode, where f _ck (Hz) is the frequency of the clock pulse a. (Hz).

And the count value g of the a-bit binary counter 9
When becomes (2 ^a −2 ^b ), the output j of the count value detection circuit 12 opens the gate group 10 of the b stage, and the a bit 2
The count value of the lower b bits of the decimal counter 9 is output. Further, when the count value g of the a-bit binary counter 9 reaches the maximum value, that is, (2 ^a -1), the output h of the count value detection circuit 12 causes the AND gate circuit 15 to
is closed, the a-bit binary counter 9 stops counting, and the output of the gate group 10 of stage b is (2 ^b -
1). Then, when the next preset pulse f arrives, the output k of the gate group 10 of the b stage immediately before the a-bit binary counter 9 is preset is set to the b-bit latch circuit 11 by the latch pulse e.
is memorized.

At this time, when the input signal d is at the center frequency, that is, when the rotational speed of the rotating body is at the set speed,
B-bit latch circuit 11 by latch pulse e
The output of the gate group of stage b at the time stored in is
2 ^(b-1) , that is, the output values NP1 and NP2 of the preset value generation circuit 8 are determined so that the count value g of the a-bit binary counter 9 becomes (2 ^a -2 ^(b-1) ). shall be taken as a thing. That is, in standard mode, NP1=2 ^a −2 ^(b-1) −f _ck /f _O , and in double mode, NP2=2 ^a −2 ^(b-1) −f _ck /4/f _O / It becomes 2.

Then, the value l stored in the b-bit latch circuit 11 is converted into an analog output by the D/A converter circuit 5 as shown in FIG.
is applied to the motor via.

By the way, the gain of a digital frequency discriminator is generally given by the following equation. That is, K _d =f _c /f _S ² [bit/Hz], where f _c is the frequency of the clock pulse and f _S is the sampling frequency. Therefore, K _d1 and K _d2 of the digital frequency discriminator in standard mode and double mode are determined as follows: K _d1 = f _ck /f _O ² K _d2 = f _ck /4/(f _O /2) ² = f _ck /f _O ² = K _d1 , and both modes have the same gain. Therefore, the open loop transfer functions of both modes have the same gain without switching the gain compensation of the compensation circuit 6 in FIG.

Furthermore, when N=3, that is, standard mode and 3
In a VTR having a double mode, the frequency division ratio of the programmable frequency divider 14 may be set to nine.
If it is difficult to divide the frequency by 9, it is also good to perform frequency division by 8, which has a simple circuit configuration, and use a compensation circuit to compensate for only the gain difference that occurs at that time.

In addition, if the set speed of the rotating body exists in multiple modes, or if the ratio of rotational speeds is large and the gain ratio cannot be brought close to 1 without significantly lowering the clock frequency, the gain ratio may be 2 ⁿ or 1/ 2(2 ⁿ +2 ⁿ⁺¹ ) (n is an integer) or close to it. In this case, the D/A conversion circuit 5 shown in FIG. 1 corrects the gain difference generated in the digital frequency discriminator. This is because it is generally relatively easy to switch the gain of a D/A conversion circuit, such as a pulse width modulation circuit, at a ratio of 2 ⁿ or 1/2 (2 ⁿ +2 ⁿ⁺¹ ).

Effects of the Invention According to the present invention, by switching the clock frequency of a digital frequency discriminator with a relatively simple configuration, the open-loop transfer function of a control device for a rotating body can be adjusted.
Compensation can be performed without amplifying the carrier wave component of the PWM output, and fluctuations in the rotational speed of the rotating body are extremely small, making it possible to achieve stable recording and playback in, for example, a VTR. It is possible to obtain a control device for a rotating body that has no variation and is suitable for digital integration.

[Brief explanation of the drawing]

Figure 1 shows a conventional rotating body (capstan motor)
FIG. 2 is a block diagram of an embodiment of a digital frequency discriminator in the rotating body control device of the present invention, and FIG. 3 is a waveform diagram of each part in FIG. 2. 1... Capstan motor, 2... Frequency generator (FG), 3... Frequency divider, 4... Digital frequency discriminator, 5... D/A conversion circuit, 6... Compensation circuit, 7 ...Drive circuit, 8...Preset value generation circuit, 9...A-bit binary counter, 10...B-stage gate group, 11...B-bit latch, 12...
...Count value detection circuit, 13...Timing pulse generation circuit, 14...Programmable frequency divider, 15...
...AND gate circuit.

Claims (1)

[Scope of Claims] 1. A control device for a rotating body having a plurality of different rotational speeds, comprising: a programmable frequency divider that divides a clock pulse according to the rotational speed; and a programmable frequency divider that divides a clock pulse according to the rotational speed; a timing pulse generation circuit that outputs a preset pulse and a latch pulse synchronized with a clock pulse; a preset value generation circuit that generates a predetermined value according to the rotational speed; and a timing pulse generation circuit that outputs a preset value according to the rotational speed; The second output of the programmable frequency divider is initialized to
a counter for counting the clock pulses of the second clock pulse, a count value detection circuit for detecting a predetermined count value of the counter, and a gate circuit for prohibiting input of the second clock pulse to the counter based on the output of the count value detection circuit; and a latch circuit that captures the counted value output of the counter using the latch pulse, and the second clock pulse existing in a period K times (K: natural number) a half period of the rotational speed signal is counted, thereby determining the clock pulse relative to the reference speed. A rotating body control device that detects errors. 2 K at all switched rotational speeds
is constant, the ratio of the error detection gain to the reference speed at each rotation speed is brought as close to 1 as possible by switching the division ratio of the programmable frequency divider according to each rotation speed. A control device for a rotating body according to claim 1. 3 K at all switched rotational speeds
is not constant, by switching the division ratio of the programmable frequency divider according to each rotation speed, the ratio of the error detection gain to the reference speed at each rotation speed can be set to 2 ⁿ or (1/
2).(2 ⁿ +Z ⁽ⁿ⁺¹⁾ ) (n: an integer). The control device for a rotating body according to claim 1.