JPH0549300A - Intermediate step generating circuit - Google Patents

Abstract

PURPOSE:To realize smooth operation of step motor by optimally setting a time point when an intermediate step takes place irrespective of the variation of input interval of step pulse. CONSTITUTION:The intermediate step generating circuit comprises a count circuit for detecting the time interval of step pulse 1 being fed externally to a step motor control circuit, a decode circuit 5 having a plurality of intermediate step generating timing being predetermined according to the constitution thereof, and a selection circuit 30 for selecting one intermediate step pulse generating timing according to the time interval of the step pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intermediate step generating circuit for smoothly moving a magnetic head in a stepping motor control circuit for moving a magnetic head of a magnetic disk device in an inner or outer direction.

[0002]

2. Description of the Related Art First, a basic operation of a conventional stepping motor control circuit and a reason why an intermediate step generation circuit is required in a magnetic disk device, for example, a flexible disk device (hereinafter referred to as FDD) will be described.

The position of the magnetic head of the FDD is controlled by step pulses supplied from the host device to the stepping motor control circuit in the FDD. One step pulse is input to the stepping motor control circuit each time the magnetic head is moved in the radial direction of one track. Therefore,
For example, when moving the magnetic head by n (n is an integer) tracks, n step pulses are input to the stepping motor control circuit. Hereinafter, every time one step pulse is input, the excitation output of the stepping motor is changed by one step (corresponding to the movement of one magnetic pole of the motor) to move the magnetic head by one track. Step feed operation ”.

In order to make this operation smoother, the excitation output of the stepping motor is changed in two steps (one-track two-step feed operation) or more steps every time a step pulse is input to It is necessary to move the head one track in multiple stages. Here, the second and subsequent steps that occur in response to the input step pulse are called intermediate steps, and the intermediate step generation circuit is adopted to generate this intermediate step.

Next, a conventional intermediate step generation circuit will be described with reference to FIG.

FIG. 9 shows a stepping motor control circuit for a one-track two-step feed operation including a conventional intermediate step generation circuit. Here, the intermediate step generation circuit is shown in FIG.
It means a combination of the circuits 4, 5, and 6. In the following description, a flip-flop (hereinafter referred to as FF)
Are all clock falling operations, and set and reset are performed at a low level (hereinafter referred to as L).

In FIG. 9, an input terminal 1 is a step pulse input terminal, and an L step pulse is set to 1 each time the FDD magnetic head is moved to the inner or outer circumference of one track.
Input from the host device. When the circuit 3 detects the falling edge of the step pulse, it outputs an L level pulse to the terminal 1
5 is a step pulse detection circuit for outputting to 5.

The input terminal 2 is a clock signal input terminal to which a clock signal that determines the operation timing of the circuits 3 and 4 is input. The input terminal 10 is an initialization signal input terminal, which becomes active at L and sets the initialization state of the stepping motor control circuit. The circuit 4 is a counting circuit that counts the number of pulses of the clock signal. The circuit 5 is a decoding circuit that decodes the output signal of the count circuit 4. The decode circuit 5 generates a pulse signal at the terminal 20 when the output of the count circuit 4 enters a specific state determined by the configuration of the decode circuit 5.

The circuit 6 is a mask circuit for masking the pulse signal supplied to the terminal 20.

The clock signal counting circuit 4 includes a NAND gate 46 connected to the initialization signal input terminal 10 and a NAND gate 47 connected to the clock input terminal 2.
The output of the NAND gate 47 is input to the R terminal T
It is comprised by FF31-34. The step pulse detection circuit 3 includes DFFs 11 to 13 with reset terminals.
, An OR gate 14 and an AND gate 45. The intermediate step internal pulse mask circuit 6 is
An inverter 21 and an OR gate 24 to which the signal of the terminal 20 is input, and a DFF 22 with a set and reset terminal
It is composed by. Further, the internal pulse counting circuit 7 is composed of TFFs 42 and 43.

When a step pulse is input to the step pulse input terminal 1, the step pulse detection circuit 3 operates at the terminal 1
The L pulse is output to 5. This pulse resets the FF 22 of the mask circuit 6 and the Q terminal 2 of the FF 22.
3 becomes L, and the mask circuit 6 is in the mask release state.
That is, the mask circuit 6 makes the pulse signal supplied to the terminal 20 pass through to the terminal 25. On the other hand, the mask circuit 6 enters the mask state after the number of internal pulses required for the head to move one track is output to the terminal 20. The mask circuit 6 shown in FIG. 9 allows only one pulse signal on the terminal 20 to pass to the terminal 25.

The output terminal 25 of the gate 24 (hereinafter, the output pulse of the gate 24 is called an intermediate step internal pulse) is L active in the example of FIG. The gate 26 is a circuit for synthesizing the differential signal of the input step pulse and the intermediate step internal pulse at the terminal 25, and the output pulse (hereinafter referred to as the internal pulse) is L active in the example of FIG. The circuit 7 is an internal pulse counting circuit and counts internal pulses. The circuit 8 is an excitation output decoding circuit that decodes the output signal from the circuit 7,
The excitation output 9 is output to the stepping motor.

Next, the operation of the intermediate step generating circuit shown in FIG. 9 will be described with reference to the timing chart of FIG.

When the input terminal 10 is set to L at the timing A of FIG. 10, the circuit of FIG. 9 is initialized. In this initial state, it is assumed that the input terminals 1 and 20 are at a high level (H) and non-active, and the output terminal 9 is in an output state corresponding to the state where the head of the FDD is just on the track.

When the first step pulse is input to the input terminal 1 (timing B), the circuit 3 outputs the L pulse to the terminal 15 in synchronization with the clock signal supplied to the terminal 2 (timing C). ).

In response to the L pulse on terminal 15, gate 26 outputs an L pulse to terminal 27. Also, the terminal 15
By the L pulse above, the D flip-flop 22 of the circuit 6
(Hereinafter referred to as DFF22) is reset.

When the clock signal on the terminal 2 becomes H (timing D), the L pulse on the terminal 27 causes the T flip-flops 31-34 (hereinafter TFF 31-3) of the circuit 4.
4) is reset and starts counting the number of pulses of the clock signal.

The count circuit 7 counts up by the negative pulse output from the terminal 27, and the decode circuit 8
Decodes the count value of the count circuit 7. The excitation output 9 from the decoding circuit 8 changes to an excitation state advanced by one step from the state assumed in the initial state, that is, an excitation state advanced by half a track (1/2 track). Next, when the count value of the count circuit 4 reaches a predetermined value,
The decoder circuit 5 sets the terminal 20 to L (active state) (timing E).

At this time, since the terminal 23 is L, the terminal 2
The intermediate step internal pulse is output to 5 and the internal pulse is output to the terminal 27. The circuit 7 counts this internal pulse, and the excitation output 9 further advances by one step and is in the state of advancing one track from the initial state.

At the next rise of the clock signal (timing F), the counter circuit 4 is reset and the terminal 20 becomes H. In response to this, the Q terminal 23 of the DFF 22 becomes H, the signal output to the terminal 20 is masked thereafter, and the intermediate step internal pulse is not generated from the terminal 25 until the next step pulse is input. The circuit of FIG. 9 repeats the above process (timing BF) every time one step pulse is input.

[0021]

However, in the above-described intermediate step generation circuit, the timing of generation of the intermediate step is determined by the frequency of the clock input signal and the configuration of the circuit 5, and may not change depending on the pulse interval of the step pulse. Absent. Therefore, if the timing of the generation of the intermediate step is appropriate for the interval of the step pulse, the operation of the stepping motor is smoothly performed.

However, if the temporal timing of the intermediate step becomes improper with respect to the interval of the step pulse, the operation of the stepping motor is not smoothly performed, and vibration and noise are generated. Therefore, the circuit of FIG. 9 has a problem that it is difficult to use in a circuit in which the step pulse interval or the frequency of the clock signal changes.

The present invention has been made in view of the above problems, in which vibration and noise are not generated, and the timing of the generation of the intermediate step is automatically adjusted according to the change of the step pulse input interval or the frequency of the clock signal. It is an object of the present invention to provide an intermediate step generation circuit that can be changed to a suitable one.

[0024]

SUMMARY OF THE INVENTION An intermediate step generation circuit according to the present invention comprises a detection circuit for detecting a time interval of a step pulse externally input to a stepping motor control circuit, and a time interval detected by this detection circuit. And a setting circuit for setting the temporal position of the intermediate step generation based on the above.

[0025]

In the present invention, the setting circuit sets the generation position of the intermediate step according to the time interval of the detected step pulse. Therefore, for example, the generation position of the intermediate step is changed according to the change of the time interval of the step pulse,
The timing of the intermediate step generation can be appropriately set according to the time interval of the step pulse.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the circuit configuration of an intermediate step generation circuit according to the first embodiment of the present invention. This intermediate step generation circuit has a configuration for a stepping motor control circuit that drives a stepping motor by a two-phase excitation method, and is configured so that the generation timing of the intermediate step is about 1/2 of the time interval of the input step pulse. ing.

The input terminals 1, 2, 10 and the output terminal 9 in FIG. 1 have the same functions as the corresponding terminals in FIG. The circuits 3, 4, 6, 7, and 8 in FIG. 1 also have the same functions as the corresponding circuits in FIG.

The features of the circuit shown in FIG. 1 are the configuration of the decoding circuit 5 and the point that a read timing instruction circuit 19 is newly provided. Therefore, the configurations of the circuits 5 and 19 will be mainly described below.

The circuit 5 is a decoding circuit for decoding the output signal of the counting circuit 4. The circuit 19 is a circuit that sets the Q-bar output 18 of the DFF 17 to L when the number of input step pulses reaches 2 after the initialization of the circuit is completed. In response to the output 18, the memory circuits DFF35 to 37 shift the pulse interval of the input step pulse detected by the circuit 4 by 1 bit and read it. The intermediate step timing reading circuit 19 is composed of DFFs 16 and 17.

Next, the basic operation of the circuit shown in FIG. 1 will be described.

The DFFs 35 to 37 of the decoding circuit 5 are
The initial state is set by the connection state of the set terminal S and the reset terminal R and the input terminal 10. DFF
The initial state of 35 to 37 is set to correspond to, for example, half of the minimum time interval of the expected step pulse.

The counting circuit 4 is reset by the first step pulse, and then counts the number of pulses included in the clock signal supplied to the terminal 2.
The output signal of the counting circuit 4 is input to exclusive OR (hereinafter referred to as EXOR) 38 to 40 in the circuit 5.

DFFs 35 to 3 set by initialization
When the output of 7 and the output of the count circuit 4 become equal,
That is, when a predetermined period of time elapses from the input of the first step pulse, the outputs of the EXORs 38 to 40 all become L,
The decoding circuit 5 generates the first intermediate step internal pulse at the terminal 20.

When the second step pulse is input to the terminal 1, the Q-bar output 18 of the DFF 17 becomes L, and the DFFs 35 to 37 of the decoding circuit 5 read the data from the circuit 4. That is, the time between the first step pulse and the second step pulse is stored in the DFFs 35 to 37. In this embodiment, the data of the detected time interval is lowered by 1 bit (corresponding to 1/2).
It is read and used for comparison with the output of the count circuit 4. Therefore, the intermediate step internal pulse generated by the second and subsequent step pulses is generated at a time point about ½ of the time interval of the step pulse from the generation of the step pulse.

Next, the detailed operation of the intermediate step generating circuit shown in FIG. 1 will be described with reference to the timing chart of FIG.

First, when an L signal is supplied to the input terminal 10 (timing A), the circuit of FIG. 2 is initialized. At this time, the outputs of the DFFs 35 to 37 of the decoding circuit 5 are the set terminal S and the reset terminal R and the input terminal 1
It is set to a predetermined state depending on the connection state with 0. This state gives the initial value of the timing of generating the intermediate step internal pulse.

When the step pulse is input to the input terminal 1 (timing B), the detection circuit 3 outputs the differential signal of the falling edge of the step pulse to the terminal 15 in synchronization with the clock signal supplied to the terminal 2. (Timing C-
D). In response to this differential signal, the AND gate 26 outputs an internal pulse to the terminal 27, and the DFF2 of the mask circuit 6
2 is reset and its Q output 23 goes low.

Count circuit 7 counts the number of internal pulses on terminal 27, and decode circuit 8 decodes this count value. Therefore, the excitation output 9 changes to an excitation state that is one step advanced from the assumed state in the initial state, that is, an excitation state that is advanced by half a track.

Further, in response to the internal pulse, the NAND gate 46 outputs H, and the NAND gate 47 outputs L at the next rising edge of the clock signal, whereby the TFFs 31 to 34 of the count circuit 4 are reset. .. After that, the count circuit 4 counts the number of pulses included in the clock signal (timings D to E).

At the timing E, the outputs of the count circuit 4 are the DFFs 35 to 37 in the initial setting state of the decoding circuit 5.
Assuming that the state of the output of
(Active state). At this time, since the terminal 23 is L, the intermediate step internal pulse is output to the terminal 25 and the internal pulse is output to the terminal 27. The count circuit 7 updates the count value by this internal pulse, and the excitation output 9 further advances by one step and is advanced by one track from the initial state.

At the next rising edge (timing F) of the clock signal, the counting circuit 4 is reset. As a result, the terminal 20 becomes H (non-active state), and the DFF
22 counts this up and the terminal 23 goes to H (timing F). Therefore, the output of the terminal 25 maintains H until the next step pulse is input, and the intermediate step internal pulse does not occur. That is, the signal output to the terminal 20 is masked.

When the second step pulse is input to the terminal 1 at the timing G, the Q bar output of the DFF 11 becomes L.
Becomes In response to this signal, the DFF17 causes the DFF16
Latching the Q output of H, the output terminal 18 of the DFF 17 changes from H to L. In response to this change, the DFFs 35 to 37 in the decoding circuit 5 output the output value of the counting circuit 4, that is, from the generation of the first step pulse to the second
The value corresponding to the time until the generation of the first step pulse is shifted by 1 bit and read. After that, the output 18 does not change until the circuit of FIG. 1 is in the initial state (state in which L is input to the input terminal 10), so that the DFFs 35 to 37 hold the stored value.

Subsequently, the detection circuit 3 and the counting circuit 4 operate in the same manner as in the case of the first step pulse input, and output the internal pulse signal to the terminal 27 (timing H).
Due to this internal pulse, the excitation output 9 changes to an excitation state that is advanced by 3 steps, that is, 1.5 tracks from the initial state. At the next rising edge of the clock signal, the count circuit 4 is reset (timing I), and then the clock input signal is counted up (timing I-J).

Next, when the count value of the count circuit 4 and the stored values of the DFFs 35 to 37 of the decode circuit 5 match, an L pulse is output to the terminal 20. That is, the count value indicating the time interval between the step pulses is set to about 1/2, and the output of the counter circuit 4 is set to EXOR 38 to 4
If they match at the input of 0, the terminal 20 becomes L. At this time, since the terminal 23 is L, the internal pulse is output to the terminal 27. The counting circuit 7 counts this pulse, and the excitation output 9 further advances by one step, resulting in a state of advancing two tracks from the initial state (timing J).

With the next rising edge of the clock signal,
The TFFs 31 to 34 of the counting circuit 4 are reset,
When the terminal 20 becomes H, the Q output 23 of the DFF 22 becomes H and the output terminal 25 of the gate circuit 24 becomes H (timing K). Therefore, thereafter, the signal output from the terminal 20 is masked, and the intermediate step internal pulse is not generated at the terminal 25 until the next step pulse is input.

Also for the input of the third and subsequent step pulses, every time one step pulse is input, the above-described process (timing G) caused by the second step pass is generated.
-K) is repeated.

As described above, in this embodiment, the intermediate pulse is generated at almost the intermediate timing when the step pulse is supplied.

Next, a second embodiment of the present invention will be described.

In this second embodiment, 1-2 phase excitation (or 2-phase excitation)
This is an example related to the intermediate step generation circuit of the stepping motor control circuit that drives the stepping motor by the one-phase excitation method and the timing of the intermediate step generation is set to about ¼ of the time interval between the input step pulses.

FIG. 3 is a block diagram showing the structure of the intermediate step generating circuit according to the second embodiment. In FIG. 3, the input terminals 1, 2, 10 and the output terminal 9 have the same functions as the corresponding terminals in FIGS. 9 and 1. However, since the output terminal 9 is an output for the 1-2 phase excitation (or 2-1 phase excitation) system, it is a 4-phase output (4 output lines).
The circuits 3, 4, 6, 7, and 8 in FIG. 3 have the same functions as the corresponding circuits in FIG. However, circuits 5, 6,
Nos. 7 and 8 are configured to obtain the output of the 1-2 phase excitation (or the 2-1 phase excitation) system. That is, the decoding circuit 5
Stores the data indicating the step pulse interval from the circuit 4 by lowering it by 2 bits (equivalent to 1/4) and comparing the stored value with the count number supplied from the count circuit 4. For this reason, the internal pulse count circuit 7 has a third T
It has FF44. Further, the intermediate step internal pulse mask circuit 6 has DFFs 28 and 29.

Considering the reset and mask functions of the count circuit 4 by the mask circuit 6, the internal pulse is about 1/4, 2/4, 3/4 of the time interval between the step pulse input and the step pulse. It occurs when it is delayed.

The counting circuit 7 counts four internal pulses for the magnetic head to move one track,
The decoding circuit 8 decodes the output of the count circuit 7 and outputs it.

Next, the operation of the intermediate step generation circuit of FIG. 3 will be described with reference to the timing chart of FIG.

First, at timing A, L is applied to the input terminal 10.
Is supplied, the outputs of the DFFs 35 to 37 of the circuit 5 are set to a state determined by the connection state of the reset terminal R or the set terminal S and the input terminal 10. Here, the input terminal 10 and the DFFs 35 to 3 of the circuit 5
The reset terminal R and the set terminal S of 7 are connected in advance so that the outputs of the DFFs 35 to 37 in the initialized state correspond to 1/4 of the time interval between the lowest expected step pulses.

Next, when the step pulse is input to the input terminal 1 at the timing B, the detection circuit 3 outputs the differential signal of the falling edge of the step pulse to the terminal 15 at the timing C in synchronization with the clock signal. To do. The DFFs 22, 28, 29 of the mask circuit 6 are reset by this differential signal. In addition, in response to this differential signal, the gate 26
Outputs an internal pulse to the terminal 27.

The counting circuit 7 counts the number of internal pulses output to the terminal 27, and the decoding circuit 8 decodes the count value of the counting circuit 7 and outputs it as the excitation output 9. As a result, the excitation output 9 is in an excitation state that is half step advanced from the state assumed in the initial state, that is, 1 /
It changes to a state in which it has advanced by 4 tracks (timing C).

At the next rising edge of the clock signal, the TFFs 31 to 34 of the counting circuit 4 are reset (timing D), and then the counting circuit 4 counts up the clock input signal (timings D to E).

The output D of the count circuit 4 is initialized.
When the outputs of the FFs 35 to 37 match (timing E), the outputs of the EXOR gates 38 to 40 all become L, and the OR gate 41 sets the terminal 20 to L. At this time, since the terminal 23 is at L, the OR gate 24 has 1
The AND gate 26 outputs the internal pulse to the terminal 27.

The counting circuit 7 counts up by the internal pulse, and the excitation output 9 advances by a half step and is advanced by one step (1/2 track) from the initial state.

At the next rising edge of the clock signal, the TFFs 31 to 34 of the counting circuit 4 are reset and the terminal 2
When 0 becomes H, the Q output of the DFF 28 becomes H (timing F).

The same operations as those of the timings D to F described above are repeated at timings F to H and timings H to J, the second and third intermediate step internal pulses are output, and the excitation output is generated. 9 advances by two half steps, and is in a state of advancing two steps from the initial state, that is, by one track (timing I).

At the next rise of the clock signal, the TFFs 31 to 34 of the counting circuit 4 are reset, the terminal 20 becomes H, and the Q output of the DFF 22 becomes H (timing J). Therefore, the OR gate 24 always outputs H, and thereafter, the signal output from the terminal 20 is masked, and the intermediate step internal pulse is not generated at the terminal 25 until the next step pulse is input.

At timing K, when the second step pulse is supplied to the terminal 1, the DFF of the timing circuit 19 is
The output terminal 18 of 17 becomes L. Therefore, the DFFs 35-37 in the decoding circuit 5 output the value of the circuit 4, that is,
The value corresponding to the time interval from the first step pulse to the second step pulse is read. When reading,
The value is shifted by 2 bits (approximately 1/4). The output 18 does not change until the circuit of FIG. 3 is in the initialization state (the state in which L is input to the input terminal 10), so that the DFFs 35 to 3 are provided.
7 holds the stored value.

Subsequently, the detection circuit 3 and the counting circuit 4 operate in the same manner as in the case of the first step pulse input (timing C), the internal pulse signal is output to the terminal 27 (timing L), and the excitation output 9 Indicates that the state is advanced by 2.5 steps (5/4 tracks) from what is assumed at the initial state point A (timing L to M).

At timing M, TFF3 of the count circuit 4
1 to 34 are reset, and then the count circuit 4 counts up the clock signal (timings M to N).

The output of the count circuit 4 is the DFF3 of the circuit 5.
When the output state of 5 to 37, that is, the state corresponding to ¼ of the time interval between the step pulses is reached, the terminal 20
Becomes L (active state). At this time, the terminal 23 is L
Therefore, the intermediate step internal pulse is output to the terminal 25 and the internal pulse is output to the terminal 27. The counting circuit 7 counts up by this internal pulse, and the excitation output 9 further advances by one half step, and by the initial state, advances by 3 steps, that is, by 1.5 tracks (timing N).

At the next rising edge of the clock signal, TFF3
1 to 34 are reset, the terminal 20 becomes H, and DF
The Q output of F28 becomes H (timing P).

The same operation as that at the timings M to P is repeated at the timings P to R and the timings R to T, the second and third internal pulses are output to the terminal 27, and the excitation output 9 is further divided into two half. The step advances, and the state advances by two tracks (timing S).

At timing T, the TFFs 31 to 34 are reset, the terminal 20 becomes H, and the Q output 23 of the DFF 22 becomes H. Therefore, the OR gate 24 always outputs H, the signal output to the terminal 20 is masked, and the intermediate step internal pulse is not generated at the terminal 25 until the next step pulse is input.

Thereafter, the same operation is repeated each time the third, fourth, ... Step pulses are input.

As described above, in the second embodiment, the intermediate step pulse is output at every 1/4 cycle of the step pulse input interval, and the excitation of the stepping motor can be switched at an appropriate timing.

In the above embodiment, the intermediate step pulse is set to 1/2 or 1/4 of the time interval of the step pulse.
The intermediate step pulse is ⅓, ⅕ of the step pulse time interval,
If the data is stored in the DFF 31-34 as ⅛, etc., it is ⅓, ⅕, 1 of the time interval of the step pulse.
An intermediate step can be generated at a timing such as / 8.

Next, a third embodiment of the present invention will be described.

In this embodiment, the intermediate step generation circuit is
It is applied to a stepping motor control circuit that drives a stepping motor by a phase excitation method. Further, the present embodiment relates to the case where the number of selectable intermediate step timings is four.

FIG. 5 is a block diagram showing the configuration of the intermediate step generation circuit according to this embodiment. The input terminals 1, 2, 10 and the output terminal 9 in FIG. 5 have the same functions as the corresponding terminals in FIGS. 1 and 9. In addition, the circuit 3 in FIG.
4, 6, 7, 8 and 19 also have the same functions as the corresponding circuits in FIG.

In FIG. 5, the circuit 5 is a decoding circuit for the output signal from the circuit 4, the circuit 30 is a selection circuit for intermediate step timing, and the circuit 19 is a counting circuit for step pulses after the initialization of the circuit.

When L is input to the input terminal 10, the circuits are initialized, the outputs of the circuits 11 to 13, 16, 17, 42 and 43 are set to L, and the output of the circuit 22 (terminal 23) is set to H. In addition, one of the gates 60 to 63 (here, the one corresponding to the earliest one (here, the terminal 48 among the terminals 48 to 51) among the timings of the intermediate steps determined in advance by the configuration of the circuit 5 is used. Gate 60)
Only L is set so that the pulse can pass to the terminal 20.

Therefore, after the circuit 4 is reset by the input of the first step pulse, the clock continues to be counted, the circuit 5 decodes it, and at each timing, one terminal is provided to each of the terminals 48 to 51. Step pulses are generated. Then, only the output of the terminal 48 corresponding to the gate 60 is passed to the terminal 20, and the first intermediate step internal pulse is generated.

In parallel with this, an appropriate decode value for the count state of the circuit 4 is input from the circuit 5 to the DFFs 58 and 59 of the circuit 30 through the terminals 56 and 57.

Then, when the second step pulse is input, the Q-bar output from the terminal 18 of the gate 17 is L level.
Then, the above-mentioned DFFs 58 and 59 read the data, and the timing of the intermediate step internal pulse to be generated next is newly selected again in consideration of the time intervals of the first step pulse and the second step pulse.

Next, the operation of the intermediate step generation circuit according to this embodiment will be described. FIG. 6 shows the input / output relationship in the intermediate step generation circuit of this embodiment, that is, the circuits 3 to 8, 19, 30 for the input terminals 1, 2, 10 (terminal 1).
5, 18, 60-63, 20, 23, 25, 27, 9)
The timing chart of is shown.

First, considering the same state as the conventional example as the initial state, the outputs of the DFFs 58 and 59 are once in the reset state, so that the output of the gate 60 is set to L and the timing corresponding to the terminal 48 is set to the intermediate step internal pulse. (See timing A in FIG. 6).

When a step pulse is input to the input terminal 1 (timing B in FIG. 6), the circuit 3 synchronizes with the clock input signal (terminal 2) and outputs the differential signal of the falling edge of the step pulse to the terminal. It outputs from 15 (timing C-D of FIG. 6). Then, an internal pulse is output to the terminal 27 through the gate 26, and the TFFs 31 to 3 of the circuit 4 are output.
4 and the DFF 22 of the circuit 6 are reset, and the terminal 23 becomes L. At the same time, the circuit 7 counts the internal pulse signal at the terminal 27, the circuit 8 decodes it, and the excitation output 9 advances by one step from the one assumed in the initial state, that is, by 0.5 tracks. However, the excitation state changes (timing C in FIG. 6).

The operation up to this point is similar to that of the conventional example.

Subsequently, the circuit 4 counts up the clock input (timing D to E in FIG. 6). Thus, when the pulse is output to the terminal 48, the terminal 20 becomes L (active state). At this time, since the terminal 23 is L,
An intermediate step internal pulse is output from the terminal 25, and an internal pulse is also output from the terminal 27. The circuit 7 counts this, and the excitation output 9 advances one step further, which is a step advanced from the initial state by two steps, that is, 0.5 × 2 = 1 tracks (timing E in FIG. 6).

Then, when the circuit 4 is reset by the next fall of the clock signal and the terminal 20 becomes H (non-active state), the DFF 22 counts this up and the terminal 23 becomes H (timing F in FIG. 6). ),
After that, the signal output from the terminal 20 is masked,
No intermediate step internal pulse is generated from the terminal 20 until the next step pulse is input.

Further, when the second step pulse is input (timing G in FIG. 6), the terminal 18 becomes L,
The DFFs 58 and 59 output the output value of the circuit 4, that is, the decode value of a suitable circuit 5 (terminal 5 corresponding to the time interval between the first step pulse and the second step pulse).
(Corresponding to 6 and 57), and the terminal 18 is no longer shown in FIG.
It does not change until the circuit of (1) enters the initialized state (the state where L is input to the input terminal 10), and this is held. Subsequently, the circuits 3 and 4 operate similarly to the timing C in the case of the first step pulse input, output the internal pulse signal from the terminal 27 (timing H in FIG. 6), and the excitation output 9 of the stepping motor. Is 3 steps from what is assumed in the initial state (timing A), that is, 0.5 × 3 = 1.5
It changes to the excitation state in which the track has advanced (timings HI in FIG. 6).

Subsequently, the circuit 4 counts up the clock input (timing I, J in FIG. 6). Thus, the output of the circuit 4 is set by the signal of the terminal 18 obtained from the second step pulse as described above, and the DFF 5 is set.
When the timing corresponding to the states of 8 and 59 comes, terminal 2
0 becomes L (active state). That is, the terminals 60 to
Since one of the terminals 63 is L, the signal of one of the terminals 48-51 corresponding to this is gate 52-55.
To reach the terminal 20.

At this time, since the terminal 23 is at L, an internal pulse is output from the terminal 27, the circuit 7 counts this, and the excitation output 9 advances one step further, four steps from the initial state, that is, 0. 5 × 4 = 2 tracks are advanced (timing J in FIG. 6).

Then, when the next clock signal rises, the TFFs 31 to 34 of the circuit 4 are reset, and when the terminal 20 becomes H (non-active state), the terminal 23 becomes H (timing K in FIG. 6), and thereafter. Terminal 20
The output signal is masked, and no intermediate step pulse is generated from the terminal 25 until the next step pulse is input.

As described above, in the third embodiment of the present invention, every time one step pulse is input, the second step pulse is also input for the input of the third and subsequent step pulses. The above-described process (corresponding to timings G to K in FIG. 6) caused by is repeated.

FIG. 7 is a circuit diagram showing an intermediate step generation circuit according to the fourth embodiment of the present invention.

In this embodiment, the intermediate step generation circuit is
It is applied to a stepping motor control circuit that drives a stepping motor by a two-phase excitation method or a 2-1 phase excitation method. The number of intermediate step timings that can be selected is four as in the third embodiment.

The input terminals 1, 2, 10 and the output terminal 9 in FIG. 7 have the same functions as the corresponding terminals in FIGS. 5 and 9. However, since the output terminal 9 is an output for the 1-2 phase excitation or the 2-1 phase excitation method, it is a 4-phase output (4 output lines). In addition, the circuits 3, 4, 5, in FIG.
6, 7 and 8 also have the same functions as the corresponding circuits in FIGS. 9 and 5. However, the circuits 5, 6, 7 in the fourth embodiment are
Since 8 is configured to obtain the output of the 1-2 phase excitation method or the 2-1 phase excitation method, three intermediate step internal pulses are generated for one step pulse input, and the timing thereof is also the first. It is necessary to make the time interval smaller than that in the above embodiment.

FIG. 8 shows the input / output relationship in the intermediate step generating circuit according to the fourth embodiment of the present invention, that is, the circuits 3 to 8, 19, 30 for the input terminals 1, 2, 10 (terminals 15, 18, 60-63, 20, 23, 25, 27,
An example of the timing chart of 9) is shown.

First, considering the same state as the conventional example and the first example as the initial state, the outputs of the DFFs 58 and 59 are once in the reset state, so that the output of the gate 60 is set to L and corresponds to the terminal 48. The timing to perform is given as the initial value of the intermediate step internal pulse (timing A in FIG. 8). When a step pulse is input to the input terminal 1 (timing B in FIG. 8), the circuit 3 outputs a differential signal of the falling edge of the step pulse from the terminal 15 (timings C to D in FIG. 8). , Terminal 2 through gate 26
7, the internal pulse is output to TFF 31 to 34 and DF
F22 is reset and the terminal 23 becomes L. At the same time, the circuit 7 counts the internal pulse signal at the terminal 27,
The circuit 8 decodes this, and the excitation output 9 of the stepping motor changes to an excitation state advanced by 0.5 steps from what was assumed in the initial state, that is, an excitation state advanced by 0.25 tracks (in FIG. 8, Timing C). Subsequently, the circuit 4 counts up the clock input (timing D to E in FIG. 8).

Thus, when a pulse is output to the terminal 48 of the circuit 4, the terminal 20 becomes L (active state).
At this time, since the terminal 23 is at L, the first intermediate step internal pulse is output from the terminal 25, and the internal pulse is also output from the terminal 27. The circuit 7 counts this, and the excitation output 9 advances 0.5 step further, 0.5 × 2 = 1 step from the initial state, that is, 0.25 × 2 = 0.
The state advances by 5 tracks (timing E in FIG. 8). Then, at the rising edge of the next clock, TFF3
1 to 34 are reset, and when the terminal 20 becomes H (non-active state), the Q output of the DFF 28 becomes H (timing F in FIG. 8).

The process of timings D to F described above is repeated twice thereafter as timings F to H and timings H to J, the second and third intermediate step internal pulses are output, and the excitation output 9 Is further advanced by 0.5 × 2 = 1 step, which is a state advanced by 0.5 × 4 = 2 steps, that is, 0.25 × 4 = 1 tracks from the initial state (timing I in FIG. 8).

Then, at the next rising edge of the clock, T
When the FFs 31 to 34 are reset and the terminal 20 becomes H, the terminal 23 becomes H (timing J in FIG. 8), and thereafter, the signal output from the terminal 20 is masked and the next step pulse is input. Until then, no intermediate step internal pulse is generated from the terminal 25.

Furthermore, when the second step pulse is input (timing K in FIG. 8), the terminal 18 becomes L, and the DFFs 58 and 59 output the value of the circuit 4, that is, the first value.
The decode value (corresponding to terminals 56 and 57) of a suitable circuit 5 corresponding to the time interval between the second step pulse and the second step pulse is read. Since it does not change until it becomes the activated state (the state where L is input to the input terminal 10), this is held.

Subsequently, the circuits 3 and 4 operate in the same manner as the timing C in the case of the first step pulse input, and output the internal pulse signal from the terminal 27 (timing L in FIG. 8) to drive the stepping motor. Excitation output 9 changes to an excitation state that is 0.5 × 5 = 2.5 steps, that is, 0.25 × 5 = 1.25 tracks ahead of what is assumed in the initial state timing A (timing in FIG. 8). LM).

Then, the circuit 4 counts up the clock (timings M and N in FIG. 8). Thus, the output of the circuit 4 is set by the signal of the terminal 18 obtained from the second step pulse as described above, and the DFF 58,
At a timing corresponding to the state of 59, the terminal 20 becomes L (active state).

At this time, since the terminal 23 is at L, the intermediate step internal pulse is output from the terminal 27, the circuit 7 counts it, and the excitation output 9 further advances by 1/2 step to 0.5 from the initial state. × 6 = 3 steps, that is,
0.25 × 6 = 1.5 tracks are advanced (timing N).

Then, the TFFs 31 to 34 are reset by the next rising of the clock, and when the terminal 20 becomes H, the Q output of the DFF 28 becomes H (timing P).

The above-described process of timings M to P is repeated twice as timings P to R and timings R to J, and inside the second and third intermediate steps by the second step pulse. A pulse is output, and the excitation output 9 further advances by 1/2 × 2 = 1 step, which is 0.5 × 8 = 4 steps from the initial state, that is, 0.25 × 8 = 2 tracks advanced (FIG. 8). Medium, timing S).

Then, at the next rising edge of the clock, T
The FFs 31 to 34 are reset, and when the terminal 20 becomes H, the terminal 23 becomes H (timing T). Thereafter, the signal output from the terminal 20 is masked, and the terminal 25 outputs the signal until the next step pulse is input. Does not generate an intermediate step internal pulse.

As described above, in the fourth embodiment of the present invention, even when the third and subsequent step pulses are input, the second step pulse is input each time one step pulse is input. The above-described process (timing K to T in FIG. 8) caused by is repeated.

[0109]

The intermediate step generating circuit according to the present invention is
The step pulse input interval is detected, and the time position at which the intermediate step occurs is set accordingly. Therefore, the intermediate step can be generated at an appropriate timing regardless of the input time interval of the step pulse and the change of the frequency of the clock signal, the stepping motor can be smoothly rotated, and vibration and noise can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an intermediate step generation circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of the intermediate step generation circuit shown in FIG.

FIG. 3 is a block diagram showing a circuit configuration of an intermediate step generation circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart diagram for explaining the operation of the intermediate step generation circuit shown in FIG.

FIG. 5 is a block diagram showing a circuit configuration of an intermediate step generation circuit according to a third embodiment of the present invention.

6 is a timing chart for explaining the operation of the intermediate step generation circuit shown in FIG.

FIG. 7 is a block diagram showing a circuit configuration of an intermediate step generation circuit according to a fourth example of the present invention.

8 is a timing chart diagram for explaining the operation of the intermediate step generation circuit shown in FIG. 7. FIG.

FIG. 9 is a block diagram showing a circuit configuration of a conventional intermediate step generation circuit.

10 is a timing chart for explaining the operation of the intermediate step generation circuit shown in FIG.

[Explanation of symbols]

 1; Step pulse input terminal 2; Clock signal input terminal 3; Step pulse detection circuit 4; Clock signal counting circuit 5; Intermediate step decoding circuit 6; Mask circuit 7; Internal pulse counting circuit 8; Excitation output decoding circuit 9; Excitation output Terminal 10; Initialization signal input terminal 19; Read timing instruction circuit 30; Intermediate step timing selection circuit

Claims (3)

[Claims] 1. A detection circuit for detecting a time interval of a step pulse externally input to the stepping motor control circuit in an intermediate step generation circuit of the stepping motor control circuit, and a detection circuit based on the time interval detected by the detection circuit. And a setting circuit for setting the temporal position of the generation of the intermediate step. 2. The setting circuit sets a memory circuit that stores the time interval detected by the detection circuit, and sets a temporal position at which an intermediate step occurs from the stored value of the memory circuit and the detection value of the detection circuit. The intermediate step generation circuit according to claim 1, further comprising a decoding circuit. 3. The setting circuit has a decoding circuit having a plurality of intermediate step generation timings which are predetermined by its configuration, and an intermediate step generation timing of the decoding circuit according to a time interval of an input step pulse. The intermediate step generation circuit according to claim 1, further comprising a selection circuit that selects one.