JPH0548676A - Data transmission system - Google Patents

Abstract

PURPOSE:To always normally display abnormality occurence by displaying abnormality when a terminal processor which does not re-transmit monitor data two times, at least, continuously to the transmission of control data by means of a central controller(CCU) is detected. CONSTITUTION:When CCU 10 cannot receive monitor data from some LCUs(terminal processor) 30-32, CCU 10 repeats the operation of data transmission to same LCU. When monitor data is received by responding to this, data transmission is shifted to next LCU as it is with a case as temporary abnormality due to accidental circumstances. Unless monitor data is received two times in a row, it is judged that abnormality owing to fault, etc., occurs in the LCU and is displayed in a display device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly to a data transmission system suitable for an integrated wiring system by multiple transmission in an automobile or the like.

[0002]

2. Description of the Related Art For example, an automobile is provided with various electric components such as various lamps and motors, and a large number of electric devices such as various sensors and actuators for controlling the automobile. It is on the rise. Therefore, as in the conventional case, wiring is performed independently for each of a large number of these electric devices, which makes the wiring extremely complicated and large-scaled, resulting in cost increase and weight, Increased space,
Alternatively, a big problem such as mutual interference occurs.

Therefore, as an example of a method for solving such a problem, a wiring simplification system by a multiplex transmission system capable of transmitting a large number of signals with a small number of wirings is disclosed in, for example, Japanese Patent Application Laid-Open No. 57-17535. It has been proposed by Nori. FIG. 1 shows an example of an integrated wiring system in a vehicle by such a multiplex transmission system.

The system of FIG. 1 uses an optical fiber cable OF as a signal transmission line, and uses a central control unit CCU.
(Hereafter, simply referred to as CCU. This is Central Cont
rolUnit) and a plurality of terminal processing units LCU (hereinafter, simply referred to as LCU. This is an abbreviation for Local Control Unit) are commonly connected by an optical signal channel.
Optical branch connector OC at the branch point of the optical fiber cable OF
Is provided.

The CCU is installed in an appropriate place such as near the dashboard of an automobile and controls the entire system. LCU is various operation switch S
W, meters M, and other indicators, lamps L, sensors S, and the like are arranged in the vicinity of a large number of electric devices installed in the automobile in a distributed manner by a predetermined number. A photoelectric conversion module O / E that bidirectionally converts an optical signal and an electric signal is provided in a portion where the CCU and each LCU are coupled to the optical fiber cable OF.

The CCU is equipped with a microcomputer and has a data communication function by serial data. Correspondingly, each LCU has a communication processing circuit CIM (hereinafter simply referred to as CI).
It is called M. This is Communication Interface Ada
(abbreviation of ptor) is provided, the CCU sequentially selects one of the LCUs, exchanges data with that LCU, and by repeating this, multiplex transmission via the 1-channel optical fiber cable OF. It is possible to simplify complicated and large-scale wiring in a car.

[0007]

By the way, in such a system, if a failure occurs in one of the LCUs, an error may occur in the control of the load, resulting in an abnormal operation. The present invention has been made in view of the above circumstances, and when an LCU (terminal processing unit) has a failure due to a simple configuration and there is a risk that a load will enter an abnormal operation, it is possible to display it. It is to provide a data transmission system.

[0008]

Means for Solving the Problems The above-mentioned object is to reduce the transmission of control data by the CCU to the same LCU by the same control data and the means for monitoring the response of the monitor data from the LCU to the transmission of the control data by the CCU. It is achieved by providing a means for repeating both times, and performing an abnormal display when an LCU that does not send back monitor data is detected at least twice in succession for transmission of control data by the CCU.

[0009]

When the monitor data from the LCU cannot be received, the data transmission operation from the CCU to the same LCU is repeated again. If the monitor data is received in response to this, the temporary transmission due to an accidental situation occurs. However, it will shift to data transmission for the next LCU as it is.
If the monitor data is not received twice in a row,
It is determined that an abnormality due to a failure or the like has occurred in the LCU, and this is displayed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data transmission system according to the present invention will be described below with reference to the drawings. 2 is an overall block diagram showing an embodiment of the present invention, and 10 is a central processing unit.
(Corresponding to the CCU of FIG. 1), 20 is a signal transmission line (corresponding to the optical fiber cable OF of FIG. 1), 30 to 32 are terminal processing devices (corresponding to the LCU of FIG. 1), 40 is A / D (analog- Digital converters) 51-58 are external loads. In this embodiment, an electric signal transmission line is used as the signal transmission line 20, and therefore,
The central processing unit 10 and the terminal processing devices 30 to 32 do not require a photoelectric conversion module, and therefore the terminal processing device 30
The contents of ~ 32 are substantially only CIM.

A central processing unit 10 including a computer (microcomputer) is provided with each terminal processing unit 3 via a transmission line 20.
An external load 51, which is connected to 0 to 32 and includes various sensors, lamps, actuators, electric devices such as motors, etc.
The transmission of control data to and from 58 is carried out by the multiplex transmission system. At this time, external loads 57, 58 such as sensors that output analog data
Is connected to the terminal processing unit 32 via the A / D 40 so that transmission operation by digital data can be performed.

The signal transmission line 20 may be bidirectional, and not limited to an electric signal transmission system, an arbitrary optical signal transmission system such as an optical fiber may be used. The communication system based on this is a so-called half-duplex system ( In Half Duplex), in response to a call from the central processing unit 10 to one of the plurality of terminal processing units 30 to 32, transmission / reception of data between one of the terminal processing units and the central processing unit 10 is performed on the transmission line. Alternately through 20.

Due to the multiplex transmission by the half-duplex method, the data sent from the central processing unit 10 is provided with an address indicating the destination thereof, and the address given to the data received from the transmission line 20. Only one of the terminal processing devices, which has recognized that the address is its own, responds.

In this way, only one of the terminal processing devices that understands the address and determines that it belongs to the address processing device 10 according to the data sent from the central processing device 10 is given to it. In response, by transmitting its own data to the central processing unit 10, the above-mentioned data transmission operation by the half-duplex system can be obtained.

Further, in this embodiment, each terminal processing device 3
The functions of 0 to 32 are integrated into a specific function to facilitate the integration of these terminal processing devices 30 to 32 into a large scale integrated circuit (LSI). The specific functions at this time include the above-mentioned data transmission function, that is, the function required for multiplex transmission by the half-duplex method, and the A / A attached to each terminal processing device.
It has two types of functions for controlling external devices such as the D40.

As a result, the data transmission function can be specialized. For example, when the data transmission function is applied to an integrated wiring system in an automobile, the half-duplex system described above is used and the required transmission speed and address are set. It is possible to decide the number of bits according to it.

Further, in this multiplex transmission system, the function of the terminal processing device made into an LSI as described above is utilized as it is, and it is also applicable to the central processing unit 10.
As a result, a general-purpose computer (microcomputer or the like) having no data transmission function is used as the central processing unit 10, and the LSI terminal processing unit 33 described above is used.
The central processing unit 10 can be configured only by combining the above, the load on the software required for the computer of the central processing unit 10 can be reduced, and the versatility of the terminal processing device can be increased. .. In this case, in the terminal processing device 33 combined with the central processing device side, some of the functions of the terminal processing device 33 remain unutilized, but this is unavoidable.

Next, FIG. 3 shows each of the terminal processing devices 30 to 32.
FIG. 2 is a schematic block diagram showing an embodiment of the present invention, in which the reception signal RXD input from the transmission line 20 is synchronized with the synchronization circuit 10.
2, the clock from the clock generator 107 is synchronized, and the control circuit 101 is supplied with a clock that is start-stop synchronized with the clock component of the received signal RXD, whereby the control circuit 101 generates a control signal and shifts it. The data portion of the received signal is serially read into the register 104.

On the other hand, the address comparison circuit 103 is given an address assigned to the terminal processing device in advance, and this address and the data read into a predetermined bit position of the shift register 104 are compared with each other.
The data in the shift register 104 is transferred to the I / O buffer 105 and provided to the external device only when they are compared with each other.

Further, the control circuit 101 includes a counter that advances by a clock, generates a sequential control signal, and outputs data by the reception signal RXD to the I / O buffer 10.
5, the data is subsequently taken in parallel from the I / O buffer 105 to the shift register 104, and the data to be transmitted from the external device to the central processing unit 10 is serially stored in the shift register 104. Prepare as. Then, this data is serially read from the shift register 104 and sent to the transmission line 20 as a transmission signal TXD.

At this time, the address given to the received signal RXD is sent as it is given to the transmitted signal TXD. Therefore, since the central processing unit 10 matches the address sent by itself, the transmitted signal is The TXD is fetched, whereby the transfer of data for one cycle by the half-duplex method is completed. In this way, the central processing unit 10 sends data to the next terminal processing unit, and by repeating this, a plurality of each terminal processing unit 3
Data is exchanged between 0 and 32 periodically,
Multiplex transmission becomes possible.

The A / D control circuit 106 is an A / D 40 required when used as the terminal processing device 32 in FIG.
The data from the external loads 57 and 58 such as sensors that generate analog signals are
/ D40 digitizes and shift register 10
It works to give the control function necessary for loading into 4. The details will be described later.

Next, FIG. 4 is a block diagram showing an embodiment of the terminal processing devices 30 to 33. The same or equivalent parts as in FIG. 3 are designated by the same reference numerals, and in FIG.
Reference numeral 01 is a synchronizing circuit for generating a clock that is start-stop synchronized with the received signal RXD, and 302 is a two-phase clock φ _S and φ.
A counter for generating _M , a counter for sequential control 303, a sequence decoder for generating various control signals from the output of the counter 303, a fault detector for 305, and a selector for input / output switching of the I / O buffer 105. Address decoder, 307 is 4 for address comparison
A bit comparator, 308 is an exclusive OR gate for error detection, 312 is an AND gate for data transmission, 313 and 314 are tri-state buffers, 3
20 is an 8-bit shift register, 321 is a 32-bit register, 322 is a 32-channel gate, 323
Is an A / D control counter, 324 is an A / D control signal generation circuit, and 325 is an A / D channel selection counter. The shift register 104 has 25 bits
(24 bits + 1 bit), I / O buffer 105 is 1
It has 4 ports (14 bits).

The terminal processing devices 30 to 33 (hereinafter, these are referred to as CIMs) are adapted to operate by selecting one of a plurality of operation modes. The CIMs 30 to 31 shown in FIG.
DIO mode when used as
The AD mode is selected when the CIM 33 is used as the CIM, and the MPU mode is selected when the CIM 33 of FIG. 2 is used. The mode selection will be described later.

First, when these CIMs are selected in the DIO mode, the A / D control circuit 106 does not operate,
The data contents of the shift register 104 at this time are as shown in FIG. 5, 6 bits from No. 0 to No. 5 are not used, and 14 bits from No. 6 to No. 19 are I / O. It is assigned to the data DIO of the buffer 105.

4 bits from No. 20 to No. 23 are assigned to the address data ADDR, and No. 24 is assigned to the start bit. The number of bits assigned to the DIO data is 14 because the I / O buffer 105 has 14 bits. Also, for this reason, C according to this embodiment
In the IM, the maximum number of external loads connectable to the I / O buffer 105 is 14.

The data transmission method according to this embodiment is called start-stop synchronization, bidirectional, inversion dual transmission method, and digital data is transmitted by the NRZ (nonreturn to zero) method, and its transmission waveform. Is as shown in FIG. That is, from CIM on the CCU side to L
If a frame that transmits data to the CIM on the CU side is a received frame, and a frame that transmits data from the LCU side to the CCU side is a transmitted frame, the received frame and the transmitted frame are both 74 bits, so that one frame and the transmitted frame Have the same frame structure, and there is a 25-bit "0" at the beginning, followed by a start bit consisting of a 1-bit "1" for start-stop synchronization, followed by 24-bit reception. The data RXD or the transmission data TXD is transmitted in the NRZ signal format, and the inverted data (RXD) or (TXD) of these data is further transmitted. Here, this inversion data (RXD) or
(TXD) is transmitted because of a transmission error check.

Regarding such inverted data,
In the drawings, characters and symbols are shown with bars attached, but in this specification, they are shown with parentheses. That is, the inverted data of the data RDX is represented by (RDX) as described above.

As described above, in this embodiment, since the multiplex transmission is carried out by the half-duplex method, the LCU which the CCU makes an interrogation at that time is applied to the first 4 bits of the data RXD of the received frame. Address data ADDR is added as shown in FIG. 5, and in response thereto, the data TX of the transmission frame transmitted from the LCU.
The same address data ADDR is attached to the first 4 bits of D and transmitted.

Since the transmission frame is transmitted from the LCU side only to the LCD interrogated on the CCU side, even if the address is not added to the transmission data TXD, the data is not transmitted on the CCU side. It can be immediately determined whether it is from the LCU. Therefore, it is not always necessary to attach an address to the data TXD of the transmission frame, and the first 4 bits of the data TXD may be an LC such as (0000).
The data may not match any of the U addresses.

Now, returning to FIG. 4, the CIM address will be described. As described above, in this embodiment, different 4-bit addresses are assigned to the CIMs on the LCU side, and the half-duplex data transmission is performed based on these addresses. Is becoming

Then, this address is assigned to each CIM.
To assign an input which serves is an input 2 ^{0-2 3} 4 that is connected to the comparator 307, the CI by the data ADDR ₀ ~ADDR ₃ to be given to these inputs
The address of M is specified. For example, to specify the address of the CIM as "10", the address data A
DDR ₀ = 0, ADDR ₁ = 1, ADDR ₂ = 0, ADD
R ₃ = 1 and (1010) may be input to the inputs 2 ⁰ to 2 ³ . In this embodiment, since the data "0" is represented by the ground potential and the data "1" is represented by the power supply voltage _Vcc , the inputs 2 ⁰ , 2 ² are grounded for the address "10". Inputs 2 ¹ and 2 ³ will be connected to the power supply.

By the way, in this embodiment, the address inputs 2 ⁰ to 2 ³ are also input to the address decoder 306, and the output thereof controls the directionality of the I / O buffer 105. As a result, if you specify the address,
Which of the 14 terminals of the I / O buffer 105 will be the data output port is determined. In this embodiment, the address directly corresponds to the number of output ports. Therefore, the address is now set to "1".
If set to 0 ", 10 out of 14 terminals of the I / O buffer are controlled as output ports, and the remaining 4 are controlled as input ports.

Although not shown in FIG. 4, the output of the address decoder 306 is also given to the sequence decoder 304 of the control circuit 101, whereby the operation mode of the CIM is changed as shown in FIG. It can be switched. That is, in this embodiment, the CIM set to the address "0" is in the MPU mode, and the CIM set to the address between "1" and "D" is the DIO.
The CIM in which the address is set to "E" or "F" is operated in the AD mode.

Next, the functions of the control circuit 101 and the synchronizing circuit 102 will be described. In this embodiment, as described above with reference to FIG. 6, the start-stop synchronization method is adopted. Therefore, when data is transmitted in both the reception frame and the transmission frame, 25 bits "0" must be stored before the start of the data transmission. After that, "1" data is inserted as a 1-bit start bit.

Therefore, the synchronizing circuit 301 detects the rising edge of the start bit following the "0" of 25 bits existing at the beginning of the received frame, and establishes bit synchronization of the internal clock.
Therefore, until the next reception frame appears, the operation is performed by the internal clock bit-synchronized with the timing at this time.

The counter 302 produces two-phase clocks φ _S and φ _M from the internal clock synchronized by the synchronizing circuit 302. As a result, the clocks φ _S and φ _M are in phase synchronization with the received data RXD that is input subsequently.

The sequence counter 303 is the synchronization circuit 3
02, a signal indicating the rising edge detection timing of the start bit is received, and a specific count value, for example, count value 0
, And then counted by the clock φ _S or φ _M. Therefore, the control procedure of the entire CIM can be determined by the count output, and by observing the count value, the CIM at an arbitrary timing can be determined.
You can know in which step the operation of is.

Therefore, the count output of the counter 303 is supplied to the sequence decoder 304, for example, RXMODE, TXMODE, R required for the operation of the CIM.
The sequence decoder 304 is configured to generate all internally required control signals such as EAD and SHIFT. That is, this embodiment is based on the sequence control method using the clocks φ _S and φ _M. Therefore, if the output of the counter 303 is decoded, all necessary control can be performed.

Next, the operation of determining whether or not the transmitted data RXD is data for that CIM, that is, whether or not the interrogation by the transmission of the received frame from the CCU is for itself will be described.

As already explained, the comparator 307
Address data from the inputs 2 ⁰ to 2 ³ is applied to one input of the shift register 1 and the other input is applied to the shift register 1
Data up Q ₂₃ bits are provided from the Q _20-bit 04. And this comparator 30
7 outputs the match signal MYADDR only when both input data match. Therefore, the shift register 10
4, the received data RXD is input, and the output signal of the comparator 307 is output at the timing when the address data (see FIG. 5) attached to the head of the data RXD is stored in the portion from Q ₂₀ bit to Q ₂₃ bit. When MYADDR is checked, it is understood that if this signal MYADDR is "1", the data RXD is addressed to itself and the call from the CCU is addressed to itself.

Therefore, the control signal COMPMODE is supplied to the error detection circuit 308, the signal MYADDR is taken in at the above-mentioned predetermined timing, and when it is "0", the output INITIAL is generated, whereby the sequence counter 303 is generated. Set to count 0,
The operation of the entire CIM is restored and the next data transmission is prepared for input. On the other hand, when the signal MYADDR is "1", the error detection circuit 308 outputs INI.
Since TIAL is not generated, the CIM operation is continued as it is according to the count value of the sequence counter 303 at that time.

Next, the transmission error detection operation will be described. In this embodiment, as already shown in FIG. 6, the data transmission by the inversion double transmission system is adopted, whereby the transmission error can be detected. Therefore, data is supplied to the exclusive OR gate 311 from the first Q ₀ bit and the last Q ₂₄ bit of the shift register 104, and the output of this gate 311 is supplied to the error detection circuit 308 as a signal (ERROR). It has become.

The sequence decoder 304 outputs the control signal RXMODE during the transmission period of the reception signals RXD and (RXD) (FIG. 6) following the start bit to output the composite gate 310.
The lower gate is opened so that the data from the transmission line 20 is input to the shift register 104 as the serial signal SI. At this time, since the composite gate 310 includes the NOR gate, the data supplied from the transmission line 20 is inverted and input to the shift register 104.

Therefore, 24 bits of data following the start bit of the reception frame (FIG. 6) are stored in the shift register 1.
At the time of input to 04, this shift register 104
The inverted data (RXD) of the reception signal RXD is written in the portion from the Q ₀ bit to the Q ₂₃ bit.

Next, as is apparent from FIG. 6, when the 24-bit reception signal RXD is transmitted and then the 24-bit inversion signal (RXD) is transmitted,
It is inverted by the composite gate 310 to become the data RXD, which starts to be input to the shift register 104 as the serial signal SI.

As a result, at the timing when the leading bit of the inverted signal (RXD) is inverted and input to Q ₀ of the shift register 104, the received signal RX that was written before that is input.
At the timing when the inverted data of the first bit of D is transferred to the Q ₂₄ bit of the shift register 104 and the data of the second bit of the inverted signal (RXD) is written in Q ₀ , the second bit of the received signal RXD Data is transferred to the bits of Q ₂₄ , and eventually, at each bit timing when the inversion signal (RXD) is serially written to the shift register 104 bit by bit, the shift register 104
Data of the same bit of the reception signal RXD and the inversion signal (RXD) is always written in the Q ₂₄ bit and the Q ₀ bit of the corresponding.

By the way, as described above, Q ₀ bit data and Q ₂₄ bit data of the shift register 104 are input to the two inputs of the exclusive OR gate 311. Therefore, if no error occurs during the transmission of the reception signal RXD and the inversion signal (RXD), the inversion signal R
Exclusive or gate 311 during XD transmission
The output of should always be "1". This is because "1" and "0" must be inverted in each corresponding bit of the reception signal RXD and its inversion signal (RXD), and as a result, the inputs of the gate 311 always show a mismatch. , Because it is only when there is an error in the transmission.

Therefore, the error detection circuit 308 outputs the signal during the 24-bit period during which the inverted signal (RXD) is transmitted.
If (ERROR) is monitored and the signal INITIAL is generated when it becomes "0" level, an error detecting operation can be obtained. As a transmission error processing method in such a data transmission system, there is also known a method in which when a transmission error is detected, it is repaired to obtain correct data. However, in this embodiment, the transmission error is When it is detected, the data reception operation of the frame is canceled at that time, and the system prepares for the data reception of the next frame, which simplifies the configuration.

Next, the overall operation of data transmission in the DIO mode of the embodiment of FIG. 4 will be described with reference to the timing chart of FIG. In the figure, φ _S and φ _M are two-phase clocks output from the counter 302 and are generated based on an internal clock generated by a clock oscillator included in the synchronizing circuit 301.

On the other hand, (RESET) is this CI from the outside.
The signal supplied to M is the same as the reset signal of the microcomputer, etc., and is supplied to all CIMs in FIG. 2, and is supplied from an external reset circuit when necessary such as when the power is turned on. Then, the entire transmission system is initialized.

When the initialization is completed, the count value of the sequence counter 303 is set to 0, and the clock φ _M advances from that point. No operation is performed until the count value reaches 25. When the count value reaches 25, the IDLE signal and the (RXENA) signal are generated, and the CIM
Becomes an idle state, the sequential control by the count value of the sequence counter 303 is stopped, the tri-state buffer 313 is opened, and a signal receivable state is set.

At this time, the reason why the signal receiving state is not kept until the count value of the sequence counter 303 becomes 25 after initialization is because of the start-stop synchronization by the synchronizing circuit 301 and the receiving signal RXD.
This is because it is necessary to give the minimum "0" period of 25 bits because it has 24 bits.

In the idle state, the sequence counter 303 continues to step by counting the clocks φ _S and φ _M , but the sequence decoder 304 keeps generating the control signals IDLE and INITIAL and receives the received signal. Just waiting for it. For this reason, as shown in FIG. 6, 25-bit "0" is added to the beginning of each received frame and transmitted frame.

In this way, it is assumed that the idle state is entered, in which the reception signal RXD is input at time t ₀ . Then, a 1-bit start bit is added to the head of the signal RXD. Therefore, the synchronizing circuit 301 detects this start bit and establishes bit synchronization of the internal clock. Therefore, thereafter, the synchronization between the data RXD, RXD and the clocks φ _M , φ _S until the transmission operation for one frame is completed is maintained by the stability of the internal clock, and the start-stop synchronization function is obtained. Become.

When the start bit is detected, the sequence counter 303 is set to count output 0 (hereinafter, the output data of this counter 303 is marked with S, for example, represented by S0 in this case), and the sequence is thereby set. The decoder 304 stops the control signal IDLE, and the control signal RX
Generate MODE. In parallel with this, the shift pulse SHIFT is supplied to the shift register 104 with the clock φ.
It is supplied in synchronization with _M.

As a result, the 48-bit received signal RXD following the start bit and the inverted signal (RXD) (FIG. 6) pass through the composite gate 310 from the transmission line 20 and are sequentially transferred to the shift register 104 as serial data. It is written while shifting bit by bit. At this time, the first 24-bit reception signal RXD is serially written in the shift register 104 serially as data (RXD) inverted by the composite gate 310, so that the 24-bit period following the start bit, that is, the sequence counter 303. Shifts from S1 to S24, the shift register 10
In the bits from Q ₀ bit to Q _{23 of} 5, the received signal RX
Data (RXD) in which D is inverted will be written.

At the next rise of the clock φ _M in S25, the control signal (COMPMODE) is output and the error detection circuit 308 functions. Then, in this state, the inverted signal (RXD) is subsequently input, and as a result, the data RXD in which the inverted signal (RXD) is inverted is serially written from the Q ₀ bit of the shift register 105. Go on.

[0059] Thus, in S24 from S1, data written into the shift register 104 (RXD) passes through Q ₂₄ bit positions of the shift register 104 from the head of the bit, the sequence counter 303 is S48 from S25 Until then, one bit is sequentially overflowed. Meanwhile, in parallel with this, the shift register 104
Of the inverted signal (RXD), the data RXD is serially written from the first bit through the Q ₀ bit position of the exclusive gate 31.
1 and the error detection circuit 308 detects a transmission error,
It will be carried out as described above.

Therefore, the sequence counter 303 sets S4.
When it reaches 8, the same data RXD as the received signal RXD is written as it is from Q ₀ bit to Q ₂₃ bit of the shift register 104. Therefore, at the timing of S48, the output signal MYADDR of the comparator 307 is checked to confirm the above-mentioned address, and whether or not the data RXD just received is addressed to itself, that is, the CCU at this time. It is judged whether or not the call from is addressed to oneself.

The sequence counter 303 sets the value in S25.
A transmission error was detected during the period from
Alternatively, when an address mismatch is detected, the error detection circuit 308 causes the control signal INITIA at the time of S48.
L is generated, and the sequence counter 303 outputs S at this point.
It is set to 0, returns to the 25-bit state before idle, and all the reception operations for this reception frame are canceled to prepare for the input of the next signal.

Now, the sequence counter 303 sets S25.
From S48 to S48, when no transmission error is detected and no address mismatch is detected, that is, S48
Error detection circuit 308 becomes INITIAL
If no signal is generated, the sequence decoder 304 causes the control signal WRITE at the time when this S48 is reached.
Generate STB. As a result, at the time of S48, either the INITIAL signal or the WRITESTB signal is generated, and when neither the transmission error nor the address mismatch occurs, the former occurs, and either the transmission error or the address mismatch occurs. If you do, the latter will be output respectively.

Thus, at the time of S48, the control signal WR
When ITESTB is output, the data in the shift register 104 at that time is written in parallel to the I / O buffer 105, and as a result, C is received by the received data RXD.
The data provided by the CU is the I / O buffer 105.
Is supplied to any of the external loads 51 to 56. At this time, since it is operating in the DIO mode, a maximum of 14 bits from the Q ₆ bit to the Q ₁₉ bit can be transmitted as the data RXD, and some of the bits can be transmitted to the I / O buffer 105.
It has already been described with reference to FIG. 5 that the output port is determined by the address.

When the process reaches S48 in this way, the process of the received frame is completed, and the process of the transmitted frame starts from the next S49 (FIG. 6). First, no processing is performed from S49 to S72. This is because of the start-stop synchronization of the CIM on the CCU side, and the IDL in the processing of the received frame described above.
It is for the same purpose as the operation in the period set before E.

When entering S73, the sequence decoder 30
4 outputs a control signal PS, which causes the shift register 104 to perform a parallel data read operation and I /
The external load 51 to 56 is connected to the input port of the O buffer 105.
Input the data given from either of them in parallel. The bit number of the data read at this time is the remaining bit number of the ports of the 14-bit I / O buffer 105 minus the bit used as the output port in the processing of the reception frame. For example, as described above, this CI
When the address of M is set to 10, the number of output ports is 10, so at this time the number of input ports is 4 bits.

To write the parallel data to the shift register 104, the shift clock SH is issued together with the signal PS.
Since one bit of IFT is required, the signal SP is raised by the clock φ _S of S73, and then the shift pulse SHIFT synchronized with the clock φ _S of S74 is applied to the control signal T.
Supply before rising of XMODE.

At this time, as is clear from FIG. 6, a start bit is added before the transmission data TXD,
Furthermore, an address must be added to the first 4 bits of the data TXD. Therefore, although omitted in FIG. 4, only during the period when the signal PS is generated, a signal representing data “1” is added to the Q ₂₄ bit of the shift register 104 and Q ₂₀ to Q ₂₃ bits. Input 2 in the part of
^{0-2 3} from the address data, are supplied, respectively.

Thus, the DUMM from S49 to S73
After the 25-bit data "0" sending period required for start-stop synchronization is set in the Y state, the control signal TXMODE rises when entering S74, whereby the TX (transmission) state is set. The generation of this signal TXMODE activates the AND gate above the composite gate 310, and further activates the AND gate 312.

As a result, Q ₂₄ of the shift register 104
Bit data, that is, data “1” that is a start bit is sent to the transmission path 20 through the AND gate 312. Then, the subsequent clock φ after S75
By the shift clock SHIFT generated in synchronization with _M , the contents of the shift register 104 are shifted to the subsequent stage bit by bit, and are sequentially sent out from the Q ₂₄ bit through the AND gate 312 to the transmission line 20. The transmission signal TXD including the start bit of 6) is transmitted.

On the other hand, in parallel with the data reading process from the shift register 104, the data read from the Q _23- bit cell is inverted through the composite gate 310 and is input to the serial input of the shift register 104. Is being supplied. As a result, after S75, the shift register 10
The transmission data TXD written from the Q ₀ bit to the Q ₂₃ bit of 4 are sent out to the transmission line 20 bit by bit by the shift clock SHIFT, and are inverted to be serial data SI as the Q ₀ bit of the shift register 104. It will be written in order starting from.

Therefore, during the period when the control signal PS is being generated, at the time when all the transmission data TXD written in the cells of the shift register 104 from the Q ₀ bit to the Q ₂₃ bit have been read, this Q ₀ bit Inverted data (TXD) is stored in the cells from Q to Q ₂₃ bits instead of the transmitted data TXD up to that point.

Therefore, after the completion of the reading of the transmission data (TXD), subsequently, the reading of the inverted data (TXD) from the shift register 104 is started, and as shown in FIG. The data (TXD) will be transmitted to the transmission line 20 after the transmission data TXD.

[0073] Thus when reaching the S122, transmission inverted data from Q _23-bit shift register 104 to the Q ₀ bits, since all read completion, the control signal TXMODE is falling, supply of the shift clock SHIFT is stopped End the state. Then, the control signal INITIAL is generated by the next clock φ _M following S122, the sequence counter 303 is set to S0, and the CIM is idle.
(IDLE) Return to the previous signal reception preparation state.

Therefore, according to this embodiment, start-stop synchronization,
It is possible to reliably perform half-duplex multiplex communication by the bidirectional and reverse two-way transmission method between the CCU and the LCU,
The transmission lines can be integrated wiring.

Next, the operation of the CIM in the AD mode according to this embodiment will be described. As mentioned above, C
As an electric device for exchanging data with the CCU via IM, there are external loads 57 and 58 (FIG. 2) that output analog signals such as various sensors. Therefore, in the embodiment of the present invention, A / It also includes a D control circuit 106 and has a function of controlling an external A / D 40. The CIM operation mode at this time is the AD mode.

[0076] Now, as also previously described, in this embodiment, the address data to be supplied to the input 2 ^{0 ~} 2 are adapted to set the operation mode is performed, the address data corresponding to the AD mode Are "E" and "F" as shown in FIG.

Next, shift register 10 when this CIM is set to operate in the AD mode
The contents of the data stored in No. 4 are as shown in Fig. 5, and the 8 bits from No. 0 to No. 7 are the AD data stored from the external load 57, 58, etc. via the A / D 40. 2 bits of No. 8 and No. 9 are for storing AD channel data. Therefore, for DIO data,
It has 10 bits from No. 10 to No. 19, and the others are the same as in the DIO mode.

Here, the AD channel data is data for specifying a channel when multi-channel A / D is used, and in this embodiment, A / D4.
Since 0 of 4 channels is used as 0, 2 bits are allocated.

The shift register 320 is an 8-bit type, and stores digital data serially taken in from the external A / D 40 (A / D converted analog data given from the external loads 57, 58, etc.). In addition to enabling parallel reading, 2-bit channel selection data given from the counter 325 for designating the channel of the A / D 40 is received in parallel, serially read and supplied to the A / D 40. To do.

The register 321 is of 32 bits and is
Since / D40 is of 8 bits and 4 channels, it is used as a register of 8 bits of 4 channels correspondingly, and the data taken in by 8 bits from A / D 40 is accommodated for each channel.

The gate 322 is also 32 bits (8 bits 4 channels) corresponding to the register 321, and AD channel data read from the Q ₈ bit and Q ₉ bit cells of the shift register 104 for data transmission (see FIG. 5) select one of the channels of the register 321 and transfer its 8-bit data to the shift register Q _0.
It operates to write AD data (FIG. 5) from the bit to the Q ₇ bit cell.

The counter 323 steps in accordance with the count of the clock φ _M , and functions to control the operation of the entire A / D control circuit 106 sequentially and cyclically. The A / D control signal generation circuit 324 includes a decoder for decoding the output of the counter 323 and a logic circuit, and has a function of generating various control signals necessary for the operation of the entire A / D control circuit 106.

Next, the operation of the entire A / D control circuit 106 will be described. In this embodiment, the counter 323
The control proceeds sequentially corresponding to each of the count outputs of, the number of steps is 27, and the count output is 0.
(This is called S0) count output 26 (this is S2
6)), 1-cycle control is completed, and A / D4
Data for one channel of 0 is taken into the register 321.

First, when the control for one cycle is started, the signal INC increments the counter 325 for channel selection, whereby the output data of the counter 325 is sequentially (0, 0) → (0, 1) →
It changes from (1, 1) to (0, 0).

The output data of the counter 325 is written in parallel at the leading 2-bit position of the shift register 320, then read as serial data ADSI and supplied to the A / D 40. In parallel with this, the output data of the counter 325 is output to a decoder (not shown).
Is also supplied to the register 321 via
8 bits of the corresponding channel of are selected.

Then, the A / D 40 outputs the serial data A
Depending on the channel selection data input as DSI,
Select the corresponding analog input channel, convert the analog data to digital data, then
The bit serial data ADSO is stored in the shift register 320.

Thereafter, the 8-bit digitally converted data AD stored in the shift register 320 is
The counter 32 is read in parallel at a predetermined timing.
Register 3 preselected by the output data of 5
21 is moved to 8 bits of a predetermined channel, and the control operation for one cycle is completed.

Thus, for example, if the output data of the counter 325 is (0, 0), the analog data of the channel 0 of the A / D 40 is digitized and stored in the 8 bits of the channel 0 of the register 321. Then, the counter 323 is reset to S0, the operation of the cycle is advanced next, the counter 325 is incremented and its output data becomes (0, 1), this time the analog data of the channel 1 is digitized, and the register 32 is read.
It is stored in 8 bits of channel 1 of 1.

Therefore, according to this embodiment, the operation of fetching data from the A / D 40 by the A / D control circuit 106 is
Sequence counter 303 and sequence decoder 304
The data of each channel of the register 321 is refreshed once every four cycles of AD control operation, and is input to the four channels of the A / D 40 in the register 321. This means that the analog data that is provided is always prepared as 8-bit digital data for each channel.

Therefore, now, the received signal RXD from the transmission line is
Is input, and the address data attached thereto is for this CIM. The address data at this time is "E" or "F", as already described. Then, the format of the data to be written into the shift register 104 in (S48 in FIG. 8) when the input of the received frame is over, since that is the AD mode of FIG. 5, the shift register 104 Q _8-bit Q
_{In the 9-} bit, 2-bit AD channel data is stored.

Therefore, this AD channel data is S
It is read at 48 when the signal WRITETESTB is generated, thereby selecting one of the four channels of gate 322. As a result, when the signals PS and SHIFT are generated in S73 (FIG. 8), the Q of the shift register 104 out of the four channels of the register 321 is output.
Only the AD data of the channel selected by the two bits of ₈ and Q ₉ are read out, and this is read by the Q of the shift register 104.
It is written in the 8-bit part from ₀ bit to Q ₇ bit, which is included in the transmission signal TXD in the transmission state after S74 and is transmitted to the CCU.

By the way, in this embodiment, as described above, the reception process of the reception signal RXD and the subsequent transmission signal T are performed.
AD data is always prepared in the register 321 regardless of the XD transmission processing. Therefore, according to this embodiment, at what timing the received signal R addressed to itself is received.
Even if XD appears, the transmission signal T by AD data is immediately transmitted.
XD transmission can be performed, the transmission processing is not affected by the operation of the A / D 40, and there is no fear that the transmission speed will decrease due to the time required for the A / D conversion operation.

In this embodiment, the A / D 40 is externally attached when the CIM is formed into an LSI, and the cost is reduced when the CIM is generalized. That is, as described with reference to FIG. 2, in this embodiment, one type of CIM is used as the LCU 30 to 31, the LCU 32, or the CIM 3 of the CCU 10 depending on the mode setting.
It can be used as 3.

However, at this time, if the A / D is built in, it becomes useless when used as the CIMs 30, 31, 33, and moreover, when it is generally applied to an integrated wiring system of an automobile, the CIM 32 is used. Since the number used as the CIM is smaller than the number used as the other CIMs 30, 31, 33, there is not much merit by incorporating the A / D in all the CIMs. for that reason,
The A / D is externally attached.

By the way, since this A / D is externally attached, as is apparent from FIG.
Since a book connection terminal is required, there is a possibility that the number of terminal pins may increase when the LSI is formed.

Therefore, in one embodiment of the present invention, when the CIM is set to the AD mode, the I / O buffer 10
Four of the 14 ports of 5 are switched as connection terminals for the A / D 40. That is, in the embodiment of the present invention, the I / O buffer 105 has 14 ports, and as is clear from FIG.
When M is set to DIO mode, all may be used as I / O ports, but in AD mode only 10 ports are used at maximum and 4 ports are not used for input / output of DIO data. It is left over.
Therefore, switch the remaining 4 ports in AD mode, and
If it is used as a terminal pin for / D40, the number of terminal pins does not increase even if the A / D is externally attached, versatility is increased when LSI is formed, and cost can be reduced.

Next, the CIM's MPU according to this embodiment
The operation in the mode will be described. As is clear from FIG. 7, in order to switch and set the CIM according to this embodiment to the MPU mode, its addresses ADDR0 to ADD are set.
Address setting by DR3 is "0", that is, input 2 ² ~
All of 2 ³ should be kept at the ground potential and set to (0000).

The MPU mode is the CI shown in FIG.
In a mode for giving necessary functions when used as M33, unlike when used in DIO mode and AD mode, when data is given from a microcomputer of CCU 10 (hereinafter, simply referred to as a microcomputer),
The transmission interface operation of transmitting the data to one of the CIMs 30 to 31 of a predetermined LCU and, when receiving the data returned in response thereto, transferring the data to the microcomputer is performed.

By the way, in the above description, as described with reference to FIG. 6, since the description was mainly from the CIM on the LCU side, a frame for transmitting data from the CIM on the CCU side to the CIM on the LCU side will be described. The received frame, conversely, the frame transmitted from the LCU side to the CCU side has been referred to as the transmitted frame, but from now on, the frame for transmitting the data as seen from each CIM is the transmitted frame, and the frame at which it accepts the data is the received frame. explain. Therefore, after that, a CIM, for example, CIM
The transmit frame at 33 is another CIM, eg CIM3.
At 0, it becomes a received frame, while at the same time, the transmitted frame at CIM 30 becomes a received frame at CIM 33.

FIG. 9 shows a CI according to an embodiment of the present invention.
An address “0” is set in M, and it is a rough functional block diagram when it is controlled to operate in the CPU mode.
This shows the state of the CIM 33 in FIG. In addition,
As described above, in this embodiment, the CIM having the same configuration can be set in three modes, that is, the CPU by the address setting.
The function in any of the modes, the DIO mode, and the AD mode can be provided. Therefore, the state of FIG. 9 represents a functional block in the CPU mode. It does not mean that the configuration is different from that of FIG.

As is apparent from FIG. 9, in the CPU mode, the functions of the I / O buffer 105 (FIG. 3) and the A / D 40 are stopped, and the I / O buffer 105 (FIG. 3) and the microcomputer are connected by a 14-bit data bus. Needless to say, the terminal pin at this time is used in common with the input / output port of the I / O buffer 105, and the increase or decrease of the terminal pin does not occur at all. And, of these 14-bit (14 lines) input / output, 8
The bits are for data and the remaining 6 bits are for control signals.

First, in this CPU mode, the data contents of the shift register 104 are as shown in FIG.
The 24 bits from Q ₀ to Q ₂₃ are all MPU data, and the microcomputer uses an 8-bit data bus.
The control circuit 101 receives the control signal from the microcomputer while the shift register 104 is accessed, and the data from the microcomputer is stored in all the bits Q _{0 to} Q ₂₃ of the shift register 104. At the same time, the transmission operation is started, and transmission of the transmission frame is started from time t _X when this data is stored, as shown in FIG.

When the transmission frame is thus transmitted from the CIM 33, the CIMs 30 to 32 on the LCU side are accordingly responded.
Of the shift register 10 at the time t _Y , which is one frame (148 bits) after the time t _X, since the CIM starts transmitting.
CIM which interrogated from CIM33 in 4
The data transmitted from (one of the CIMs 30 to 32) will be stored and the process will end.

Therefore, the control circuit 101 of the CIM 33 is
At this time t _Y , an interrupt request (IRQ) is generated, and in response to this, the microcomputer reads the data in the shift register 104 and ends the data transmission for one cycle. Needless to say, the data transfer operation between the CIMs at this time is the same as that in the DIO mode described with reference to FIG.

Next, FIG. 11 shows CIM 33, that is, MP.
FIG. 4 is a functional block diagram showing an embodiment of CIM when set in U mode, showing only blocks corresponding to functions required in MPU mode, in which 400 and 402 are 8-bit switches, and 404. Is an 8-bit data latch, and the others are the same as in the embodiment of FIG.

In this MPU mode, the shift register 1
Bits Q ₀ to Q _{23 of} 04 are connected to the data bus of Mycok via the input / output pins of 8 bits and exchange data with each other.
The bits of Q _{0 to} Q ₂₃ of the shift register 104 are divided into three groups, Q _{0 to} Q ₇ (Reg3), Q _{8 to} Q ₁₅ (Reg2),
It is treated as being divided into Q _{16 to} Q ₂₃ (Reg 1), and sequentially accessed in time division.

Therefore, for this reason, the 8-bit switch 4
00 and 402 and control signals READ1 to READ3 of the switch 400 and the switch 402 by the combination of the register select signals RS0 and RS1 given from the microcomputer.
I / O terminal pins 7-1
4 is sequentially connected from Reg1 to Reg2, and then to Reg3, and by accessing 8 times for 3 times,
Data is exchanged between the microcomputer and the shift register 104. In this case, when writing data from the microcomputer to the shift register 104, a latch 404 is provided in order to compensate for the difference between the data read time from the microcomputer and the data write time to the shift register 104. The data from is latched and then written.

In this MPU mode, the address added to the beginning of the 24-bit data at the time of data reception is not collated in this CIM 33. Therefore, the address (0000) given to inputs 2 ^{0 to} 2 ³ is
Address decoder 306 is used only to set this CIM in MPU mode, leaving comparator 307 in FIG. 4 inoperative.

Next, in this MPU mode, CIM33
I / O terminal pins 1 to 6 are transmission lines for control signals to the microcomputer.
A clock E, a chip select signal (CS), a read / write signal RW, and the above-described register select signals RS0 and RS1 are given to the IM control circuit 101. On the other hand, from the CIM, an interrupt request signal (IRQ ) Is output to the microcomputer.

FIGS. 12 and 13 show an embodiment of a processing circuit for these signals, which is omitted in FIG. 11, but is included in a part of the control circuit 101. Is supplied to the circuit of FIG.
It is processed together with K to generate two-phase clocks EH and EL. Then, these clocks EH, EL and the signals RW, CS, RS0, RS1 from the microcomputer are processed by the circuit of FIG. 12, and signals STB0-3, READ0-1 are generated. The signal MPU is a signal which becomes "1" when the CIM is set to the MPU mode.

Further, FIG. 14 and FIG. 15 show signal processing timings by the circuit of FIG. 13, of which FIG. 14 shows the generation timing of the signals READ0 to READ3 and FIG. 15 shows the signal STB0. The occurrence timings of ~ 3 are shown respectively. In these figures, which one of the signals READ0 to 3 and which one of the signals STB0 to 3 is to be generated is determined by the combination of the signals RS0 and RS1. As a result, the groups Reg1, Reg2, Reg3 of the shift register 104 described above are selected.

By the way, these signals READ0-3,
The signals READ0 and STB0 of STB0 to 3 are
It is not used for the group selection of the shift register 104 described above, but is used for generating an interrupt request signal (IRQ) described later. Therefore, the selection state by the signals RS0 and RS1 is shown in FIG.

Next, FIG. 17 shows an embodiment of an interrupt request signal (IRQ) generation circuit, which is also included in the control circuit 101 of FIG. Signal WRITESTB (Fig. 8) and signal REA generated when storage of received data is completed
A circuit for generating a signal (IRQ) by D0 and any one of the data lines D0-D7 connected to the data bus of the microcomputer by the input / output terminal pins 7-14, for example, the signal DATA from the data line D0. A circuit for generating the signal MASK1 from the signal STB0, and its operation is shown in the timing charts of FIGS.

Of these, FIG. 18 shows the signal DA.
FIG. 19 shows the operation when TA is "0" at the generation timing of STB0, and FIG. 19 shows the operation when the signal DATA is "1". In the circuit of FIG. 17, the flip-flop to which the signals DATA and STB0 are supplied is called Reg0. Therefore,
In the circuit of FIG. 17, when "1" is written in Reg0, the interrupt request signal (IRQ) is masked.

Next, the overall operation of data transmission in the embodiment of FIG. 11, that is, one embodiment of the CIM according to the present invention set in the MPU mode will be described with reference to the timing chart of FIG. In the embodiment of the present invention, the operation of each of the CIMs 30 to 33 is controlled by the count output of the sequence counter 303. Therefore, if the count output of the sequence counter 303 is set to a predetermined value, the operation state becomes arbitrary. The fact that the CIM can be rearranged is as described above with reference to FIGS. 4 and 8, and this is the same regardless of the mode of the CIM.

By the way, as shown in FIG. 11, the CIM set in the MPU mode is as shown in FIG.
CIM3 set to DIO mode or AD mode
It is 0 to 32. And this CIM is DIO
When the mode and the AD mode have been set, FIG.
As described in, when data from another CIM is received, the data of its own is subsequently transmitted,
The data transfer operation for one frame is performed, so to speak, only passive operation is performed.

On the other hand, like the CIM 33, the MPU
In the mode set, when the data from the microcomputer is written in the shift register 104, the data transmission is started by itself, that is, an active operation is required.

Therefore, in this embodiment, in order to start the active data transmission, the signal STB among the signals STB1 to STB1 to STB1 for selecting the group of the shift register 104 is used.
I am trying to use 3. This is because the transmission data written by the microcomputer to the shift register 104 is R
This is because the process is performed in the order of eg1, Reg2, Reg3, and therefore, when the signal STB3 is generated, the microcomputer finishes storing all the data in the shift register 104.

Then, returning to FIG. 20, it is assumed that data to be transmitted to one of the LCUs is prepared for the microcomputer of the CCU 10 (FIG. 2) at a certain point in time.

Then, this microcomputer executes the signals (CS), RW, RS0, RS via the input / output terminal pins 1-6.
1 is supplied to the control circuit 101 in the CIM 33, and
As described with reference to FIG. 16, signals STB0 to 3 are generated (upper left end of FIG. 20), and 8-bit data is sequentially transferred from the data bus to Reg1 and Re of the shift register 104.
Write to g2 and Reg3.

On the other hand, the control circuit 101 sends the signal STB
3 is generated, the sequence counter 303 displays "4".
9 "is loaded. An embodiment of a circuit for setting the output data of the sequence counter 303 by this signal STB3 to" 49 "is shown in FIG. 21, and a timing chart showing the operation of this circuit is shown in FIG.

In this way, the sequence counter 303 sets the S
When it is set to 49, processing of the transmission frame starts at this time t _X (FIG. 10). The processing of the transmission frame from S49 to S122 is almost the same as the case of the DIO mode described in FIG. 8, but in this MPU mode, data to be transmitted has already been written in the shift register 104. , nothing in between from S49 to S73, only for start bit Q ₂₄ of the shift register 104 to "1" that only writing is only different from the case of DIO mode.

When S122 is reached in this way, the signal INIT
An IAL occurs and then enters an idle state that includes the minimum time from S0 to S24. That is, unlike the case of the DIO mode, in the MPU mode, instead of waiting for the data to be received from another CIM, when the data writing from the microcomputer to the shift register 104 is completed, the data 49 is forced to the sequence counter 303. Loaded in
As a result, the processing of the transmission frame is automatically started.

Now, in this way, the CIM 33 of the CCU 10
When the transmission of the transmission frame is started from, the transmission data TXD is transmitted to the CIM on the LCU side as already described in FIG.
The reception processing is performed as the reception data RXD by 30 to 32, and the return data is transmitted by the CIM in which the address is located, so that this time is received by the CIM 33 as the reception data RXD.

The processing of the received frame at this time is almost the same as in the case of the DIO mode in FIG. 8, except that the MPU mode does not check the coincidence of the addresses. Then, from S0 to S48, when the reception data is completely stored in the shift register 104 and no error is detected, when the signal WRITE STB rises by the clock φ _S of S48, the signal shown in FIG.
7 to 19, the interrupt request signal (IRQ) is generated as described with reference to FIG. 19, and the signal INITIA is generated by the subsequent clock φ _M.
When L is generated, this ZCIM 33 enters the idle state, and remains in the idle state until the next signal STB3 is generated.

When the interrupt request signal (IRQ) is generated in this way, the microcomputer in the CCU 10 jumps to the interrupt processing routine by this signal IRQ and shift register 10
The received data is fetched from 4. At this time, to receive the reception data from the shift register 104, a switch 400 is used, to which signals READ1 to READ3 are sequentially supplied from the circuit described in FIGS. 12 and 13, and the 8-bit data bus D0 to D7 is supplied. R of the shift register 104
As described above, it is performed in the order of eg1, Reg2, and Reg3.

By the way, in this embodiment, as already described with reference to FIG. 17, this signal (IRQ) is maskable, and the microcomputer of the CCU 10 has Reg0 (FIG. 17).
By writing "1" to this signal (IR
Q) can be masked.

Therefore, as shown in FIG. 20, if the data bus D0 is set to "1" in accordance with the time point of generation of the signal STB0 (lower left of FIG. 20) before the time point t _X of generation of the signal STB3, the signal MASK changes. It becomes "1" and then the signal WRI
Interrupt request signal (IRQ) even when TESTB occurs
Are not supplied to the microcomputer, which allows the microcomputer to preferentially perform other processing during a predetermined period as needed.

Note that, as is clear from FIG. 17, the mask is released when the data bus D is generated when the signal STB0 is generated.
It is sufficient to set 0 to “0” and write “0” to Reg0.

On the other hand, when the microcomputer of the CCU 10 masks the signal (IRQ) in this way, the microcomputer of FIG.
Signal IRQ is checked, and if it is "1", it means that the data reception has been completed. Therefore, the data is fetched from the shift register 104, and if it is "0", the data reception is completed. Wait for The signal (IR
Q) is a signal R generated when data is taken in
It is clear from FIG. 17 that it is canceled by EAD0.

Here, as shown in FIG. 2, a state transition diagram shows a data transmission operation by a combination of the CIM 33 set in the MPU mode and the CIMs 30 to 32 set in the DIO mode (or AD mode). It looks like 23.

Next, transmission control by the microcomputer of the CCU 10 will be described. The microcomputer of the CCU fetches data from various switches and sensors in the load of each LCU, and accordingly, outputs data for controlling various lamps and actuators of the load of each LCU to each LCU. To send to the LCU, but also processing at startup when the power is turned on to the transmission system and each LCU when the data transmission is in a steady state.
CIM operation is monitored.

FIG. 24 shows an embodiment of the CCU 10, which is 500
Is a central processing unit (CPU), 502 is a read only memory (ROM) for storing programs, 504 is a random access memory (RAM) for storing data, and 506 is a peripheral interface adapter. (Referred to as PIA), the CRM 33 set to the CPU mode, the photoelectric conversion module O / E, and the optical fiber cable O.
The bidirectional transmission path 20 and the like made of F are as described in FIGS. 1 and 2.

Next, the operation of the embodiment shown in FIG. 24 will be described with reference to FIG.
It will be described with reference to the flowchart of FIG. When the power supply for operation of the entire data transmission system is turned on by turning on the engine key switch of the automobile and the transmission operation is started, the process according to this flow is started, and the first step S1 (hereinafter, step S1) is started. Omitted and simply S1, S
2).

At S1, a system activation flag prepared in advance is set. In S2, after the system is started, it is checked whether or not the data transmission from the CCU to each LCU has completed one cycle, and the result is NO, that is, the CCU is still running after the system is started.
Data transmission from the LCU, that is, an LCU that has not been challenged
To S3 while remains, otherwise S9
Head to.

In S3, it is checked whether or not data transmission from the CCU has been performed even once after the system is activated, and it is determined whether or not it is the first transmission. When the result is YES, the process proceeds to S4, and when the result is NO, the process proceeds to S10. S
4, the specific control data created in advance and stored in the ROM 502 is stored in the specific LCU, which is also defined in advance.
Send to. As the specific control data at this time, data is set so that the control state of the load in the specific LCU which should receive the data becomes appropriate at the time of system startup. For example, if the load of the LCU is a lamp, it should be set as data for extinguishing it anyway. After finishing the process of S4, S5
Proceed to.

In S5, it is checked whether or not data is transmitted from any one of the LCUs. If the result is NO, the process proceeds to S6, and if the result is YES, the process jumps to S8. It should be noted that the data transmitted from the LCU to the CCU is data representing the operating states of the switches and sensors in the load coupled to the LCU, and is therefore referred to as monitor data.

At S6, the determination result at S5 continues to be 2
If the result is YES, the process proceeds to S7, and if the result is NO, the process returns to the determination in S3.
In S7, warning processing of abnormality occurrence is performed, and at this time, to the LCU that has not transmitted the monitor data twice,
It is displayed on the DIS 508 that an abnormality has occurred due to a failure or the like, and then the process proceeds to S8.

At S8, the LCU to which data is to be transmitted next from the CCU is determined to be the next LCU. Therefore, after the system is started in S4, the specific LCU to which data is to be first transmitted from the CCU is the first, and the other LCUs are numbered in advance so that they can be sequentially designated. Needless to say, it is necessary. After S8, the process returns to S2.

On the other hand, if the result in S2 is YES, the process proceeds to S9, and if the result in S9 and S3 is NO, the process proceeds to S10. First, in S9, the system start flag is cleared. Processing is performed.
Then, in S10, a process for transmitting the control data for each LCU, which is created based on the monitor data received from each LCU, to the corresponding LCU is performed.

The transmission process in S4 and S10 is automatically started when the CPU 500 of the microcomputer completes the writing of 24-bit data to the shift register 104 of the CIM 33 and the signal STB3 is generated. This is as already explained.

On the other hand, when the microcomputer including the CPU 500 is operating according to S1 to S10, when the CIM 33 associated therewith receives data, an interrupt request signal (IRQ) is generated, and Figure 20
As described above, the processing of the microcomputer jumps to the interrupt processing for fetching data from the CIM 33. Then, as shown in FIG. 26, the CIM
Based on the monitor data received from each LCU via 33, a processing of newly displaying necessary control data on the DIS 508 is performed each time.

Thus, the data created in the interrupt process corresponds to the corresponding LCU in the process of S10 of FIG.
Will be sent to. As described above, when the interrupt request signal (IRQ) is masked, the operation depends on the state at the time of mask release.

Next, the result of the processing of FIGS. 25 and 26 will be described. First, S2, S3, S4
Due to the existence of the respective processes, the first data transmission operation after the power is turned on is the transmission of the specific control data to the specific LCU. As a result, the load provided in this specific LCU is immediately changed from the abnormal control state due to the indefinite data when the power is turned on to the sufficiently appropriate control state according to the specific control data.

On the other hand, if the monitor data is received even once after the power is turned on, the control data can be created based on the received monitor data. After that, the LCU other than the specific LCU can be transmitted by the data transmission in S10. , Fairly reasonable control data will be sent, which is emphasized as the number of data transmission increases, and when the number of data transmission is close to the number of LCUs, it is almost the same as the steady state and almost completely controlled state. Obtainable.

Therefore, according to this embodiment, it is possible to minimize the abnormal control state of the load when the power is turned on,
It is possible to perform control that causes practically little problem.

Next, according to this embodiment, S in FIG.
Due to the existence of the processing of 5, S6 and S7, the CCU has an LC
If the monitor data from the LCU cannot be received when the data is transmitted to the U, the operation of transmitting the data to the same LCU is repeated from the CCU, and the monitor data is received in response to this. For example, as a temporary abnormality due to an accidental situation, the data transmission to the next LCU is directly performed, but if the monitor data is not received twice in a row, it is determined that the LCU has an abnormality due to a failure or the like. And that is DIS508
Will be displayed in.

Therefore, according to this embodiment, the data response operation of all LCUs is monitored during the data transmission operation, and when an abnormality occurs, it is automatically confirmed whether or not it is temporary. Therefore, it is possible to always display the abnormality normally.

In the embodiment of FIG. 25, the judgment in S6 is whether or not reception is impossible twice in succession. However, the number of times at this time is not limited to two, and any number of times of two or more may be used. Good. For example, if the noise environment is bad and the probability of temporary data transmission error occurrence is high, the number of times is set to 4, 3, or 5 times. On the contrary, it is installed in a good environment and accidental data transmission is performed. It goes without saying that when the probability of error occurrence is low, even two times may be sufficient, as shown in the above embodiment.

By the way, in the embodiment of FIG. 25, after the power is turned on, the data first transmitted from the CCU to the LCU becomes the specific control data prepared in advance for only one specific LCU, and the other data. For LCU, the control data is created each time based on the monitor data, but specific control data is prepared for each LCU, and the first transmission to each LCU is performed. On the other hand, specific control data corresponding to each LCU may be transmitted.

Next, FIG. 27 shows another embodiment of the CCU 10 in which the number of loads included in the data transmission system becomes large and L
An example suitable for a case where a plurality of CIMs are required in a CU is shown in FIG.
0, 512, 514 are O / E (photoelectric conversion module),
20a, 20b, 20c are signal transmission lines by OF, 30
Reference numerals a, 30b, 31a and 31b are CIMs set in the DIO mode or the AD mode, and the other points are the same as those in the embodiment of FIG.

O / E 510, 512, 514 are PIA5
Is selected and controlled by 06, and a plurality of OFs 20a, 20
One of b and 20c is a signal transmission line T of the CIM 33.
It works to combine with X and RX. Each LCU includes a plurality of CIMs 30a, 31a, 30b, 31b, and OFs 20a, 20b, 20 which are independent of each other.
bound to CCU by c.

As the CPU 500, HD4680 is used.
2 and the IC known as HD46821 is used for the PIA 506. Of these, since the ROM and RAM are built in the HD4682, it is not necessary to provide them externally. ..

According to this embodiment, the microcomputer including the CPU 500 and the like operates the O / E 512 via the PIA 506.
~ 514 can be selectively controlled, and the LCU for data transmission can be designated by the CIM 33. Therefore, a CIM with the same address can be provided for each LCU, and the number of CIMs on the LCU side can be the number of addresses. It is possible to increase the number sufficiently, and the function of the data transmission system can be easily expanded.

[0155]

According to the present invention, one CCU and a plurality of LCUs are provided, and each LC responds to a call from the CCU.
In a data transmission system adapted to perform data transmission between U and CCU, a data transmission system capable of preventing an abnormal operation of a load because an abnormal display is accurately displayed even when a LCU fails, Can be easily provided.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of an integrated wiring system in a vehicle.

FIG. 2 is a block diagram showing an embodiment of a data transmission system according to the present invention.

FIG. 3 is a block diagram showing an embodiment of each terminal processing device.

FIG. 4 is a block diagram showing the embodiment of FIG. 3 in more detail.

FIG. 5 is an explanatory diagram showing an example of data contents.

FIG. 6 is an explanatory diagram showing an example of a transmission waveform.

FIG. 7 is an explanatory diagram showing an example of mode selection.

FIG. 8 is a flowchart for explaining the operation of the embodiment of the present invention in the DIO mode.

FIG. 9 is a CPU of an embodiment of the terminal processing device according to the present invention.
It is the functional block diagram which set and showed the mode.

FIG. 10 is an explanatory diagram showing an example of transmission waveforms in a CPU mode.

FIG. 11 is a functional block diagram explaining the embodiment of FIG. 9 in more detail.

FIG. 12 is a block diagram showing an embodiment of a signal processing circuit.

FIG. 13 is a block diagram showing an embodiment of a signal processing circuit.

FIG. 14 is a timing chart for explaining the operation of one embodiment of the signal processing circuit.

FIG. 15 is a timing chart for explaining the operation of one embodiment of the signal processing circuit.

FIG. 16 is a block diagram showing a selection operation by a register select signal.

FIG. 17 is a block diagram showing an embodiment of an interrupt request signal generation circuit.

FIG. 18 is a timing chart for explaining the operation of one embodiment of the interrupt request signal generation circuit.

FIG. 19 is a timing chart for explaining the operation of the embodiment of the interrupt request signal generation circuit.

FIG. 20 is a timing chart for explaining the operation in the CPU mode.

FIG. 21 is a block diagram showing an embodiment of a circuit for setting a counter.

FIG. 22 is a timing chart for explaining the operation of the embodiment of the circuit for setting the counter.

FIG. 23 is a state transition diagram showing a data transmission operation by a combination of the CPU mode and the DIO mode.

FIG. 24 is a block diagram showing an embodiment of a central processing unit.

FIG. 25 is a flow chart for explaining the operation of the central processing unit.

FIG. 26 is a flow chart for explaining the operation of the central processing unit.

FIG. 27 is a block diagram showing another embodiment of the central processing unit.

[Explanation of symbols]

 10 Central Processing Unit 20 Signal Transmission Line 30 to 32 Terminal Processing Device 33 Communication Control Device 40 A / D (Analog to Digital Converter) 51 to 58 External Load 101 Control Circuit 102 Synchronous Circuit 103 Address Comparison Circuit 104 Shift Register 105 I / O buffer 106 A / D control circuit 107 Clock generator 301 Synchronous circuit 302 Counter 303 Sequence counter 304 Sequence decoder 305 Abnormality detector 306 Address decoder 307 Comparator 308 Error detection circuit 310 Composite gate 311 Exclusive OR gate 312 AND gate 320 Shift register 321 Register 322 Gate 323 Counter 324 A / D control signal generation circuit 325 Counter 500 CPU 502 ROM 504 RAM 506 P IA 508 display device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Hasegawa 2520 Takaba, Katsuta City, Ibaraki Pref., Sawa Factory, Hiritsu Manufacturing Co., Ltd.

Claims (1)

[Claims] 1. A central processing unit and a terminal processing unit are provided,
In a data transmission system in which data transmission and reception in frame units between the central processing unit and the terminal processing unit are started in response to a call from the central processing unit, a terminal processing for transmission of control data by the central processing unit. Means for monitoring the reply of the monitor data from the device and means for repeating the transmission of the control data by the central processing unit to the same terminal processing device by the same control data at least twice are provided. A data transmission system characterized in that an abnormal display is made when a terminal processing device which does not send back monitor data at least twice in succession to transmission is detected.