JPH0548499A - Automatic adaptive equalizer - Google Patents

Abstract

PURPOSE:To enhance the compensation capability sufficiently even when the arrangement of signal points of the modulation system is specific in the automatic adaptive equalizer compensating distortion of a propagation line waveform of the digital microwave communication. CONSTITUTION:The part with specific signal point arrangement with respect to QAM modulation is subjected to area designation in advance, and an area discrimination circuit 26 discriminates whether or not a reception data is within the designated area and a discrimination signal D is generated, and the discrimination signal D is used to select the state of either output inhibition or output permission for each amplitude of the automatic adaptive equalizer 2 and a correlation signal of a control signal generating circuit 25 of delay distortion equalization circuits 21-24.

Description

Detailed Description of the Invention

[0001]

The present invention is used in a multilevel digital microwave radio communication system. In particular, it relates to an automatic adaptive equalizer.

[0002]

2. Description of the Related Art In recent years, in the digital microwave radio communication system, the modulation / demodulation technology tends to be multi-valued for effective frequency utilization (16QAM to 64QAM, 256QAM, etc.). Compensation technology for distortions generated in the same manner and distortions generated in the propagation path becomes an important issue. Therefore, in order to reduce the distortion generated in the transmitter or the like, for example, the document “A STEPPED SQUA” is used.
AR256QAM FOR DIGITAL RADI
O SYSTEM "(TOSHIHIKO RYU et al.
1986 IEEE P1477-1481), as shown in SS-QAM (Stepped-Squar).
The QAM method has been proposed. As for the compensation technique for the distortion generated in the propagation path, various compensation techniques using an automatic adaptive equalizer or a transversal equalizer have been proposed.

A conventional technique (32QAM) will be described. FIG. 3 shows an embodiment of a digital demodulator using an automatic adaptive equalizer, and FIG. 4 shows an embodiment of a control signal generating circuit of the automatic adaptive equalizer. 1 is an input terminal for a digital modulation signal, 2 is an automatic adaptive equalizer, 3 is a demodulation circuit, 4 is a transversal type equalizer, 21 is a second-order delay distortion equalization circuit, 2
2 is a first-order delay distortion equalization circuit, 23 is a first-order amplitude distortion equalization circuit,
Reference numeral 24 represents a secondary amplitude distortion equalization circuit, and 25 represents a control signal generation circuit. Further, 101 to 108 are 1-bit delay circuits, 11
3 to 115 and 117 to 119 are exclusive ORs (EX
-OR) circuit, 116 and 120 are exclusive OR negation (EX-NOR) circuits, 125 and 126 are addition circuits, 127 and 128 are subtraction circuits, and 129 to 132 are averaging circuits. Further, N in the figure indicates that it is an N (N is a certain integer) bit digital signal. The digital modulation signal input from the input terminal 1 is input to the automatic adaptive equalizer 2, the secondary delay distortion equalization circuit 21 compensates the secondary delay distortion, and this output is input to the primary delay distortion equalization circuit 22. The signals that have been input and are compensated for the first-order delay distortion, and then similarly the signals whose first-order amplitude distortion and second-order amplitude distortion have been compensated by the first-order amplitude distortion equalization circuit 23 and the second-order amplitude distortion equalization circuit 4, respectively, are automatically adaptive equalized. It is output from the device 2. Regarding the operation and control of this automatic adaptive equalizer, for example, Japanese Patent Laid-Open No. 58-0686.
35 "Automatic adaptive equalizer" or reference number 511-04
51P0 "Automatic Adaptive Equalizer". The output of the automatic adaptive equalizer 2 is input to the demodulation circuit 3, and the demodulation circuit 3 performs quadrature coherent detection of the input digital modulated signal on the carrier synchronized with the carrier modulated on the transmitting side, and the analog-digital conversion circuit The digital signals of P and Q channels sent from the transmitting side are identified and reproduced,
It becomes the output signal of the demodulation circuit 3. P of the output of the demodulation circuit 3,
MSB of each digital signal of Q channel (M
Ost Significant Bit) is used as the quadrant determination signals Dp and Dq, and the next significant bit (4th bit in the case of 32QAM) of the data signal of the digital signal is used as error signals Ep and Eq.
(Control signal generation circuit 25). Further, the output of the demodulation circuit 3 is input to the transversal type equalizer 4. The transversal type equalizer 4 outputs a data signal in which intersymbol interference due to distortion generated in the propagation path is compensated. The operation of the above transversal type equalizer is, for example, reference number 511-2185P0 "digital demodulator".
In detail.

[0004]

In such a conventional example, the quadrant decision signal and the error signal are directly extracted from the output of the analog-digital conversion circuit of the demodulation circuit, and the amplitude is converted into a normal QAM signal by the automatic adaptive equalizer. Since the distortion equalization circuit and the delay distortion equalization circuit are controlled, there is a drawback that the control is performed as if the signal is at that point even though there is no signal in the actual signal point arrangement, resulting in malfunction.

A detailed description will be given with reference to FIG. 6 is 3
Each signal point on the phase plane of the 2QAM modulated signal is shown. When the first-order amplitude distortion of the frequency characteristic of the propagation path occurs, the data signal receives orthogonal interference, that is, the P channel data interferes with the Q channel data and the Q channel data interferes with the P channel data. To give. This is equivalent to the relative rotation of the P-axis (Q-axis) to the right or left in the signal point arrangement diagram of FIG. 6, and it can be said that the control of the automatic adaptive equalizer is normal. Controls to rotate the shaft in the opposite direction. Therefore, assuming that the first-order amplitude distortion of the frequency characteristic becomes more severe and the signal point located at the point A in FIG. 6 rotates to the point B, whether the point A actually rotates to the point B or not. Although it is indistinguishable whether or not it is rotated to the point B, the automatic adaptive equalizer determines that the point D has become smaller and performs control, resulting in a malfunction. This phenomenon may cause malfunction of control even in the case of secondary amplitude distortion, primary delay distortion, and secondary amplitude distortion.

The present invention eliminates such drawbacks, and provides an automatic adaptive equalizer capable of sufficiently exerting the ability to compensate for channel waveform distortion even when the signal points of the modulation method are unique. The purpose is to

[0007]

The present invention includes a demodulation circuit and a demodulation circuit.
An N + 1 tap (N is a positive integer) transversal type equalizer is connected in a subsequent stage in a cascade manner, and a primary amplitude distortion equalization circuit, a secondary amplitude distortion equalization circuit, a primary delay distortion equalization circuit and a secondary delay distortion An adaptive equalizer including an equalizer circuit, and an in-phase control signal Re (−) corresponding to the transversal equalizer according to the error signal generated from the demodulated baseband signal, the quadrant decision signal, and the clock signal. N) ~ Re
Re (-1) and Re (+1) are extracted from (+ N) and Im (-1) is extracted from the orthogonal control signals Im (-N) to Im (+ N) corresponding to the transversal equalizer. ) And Im (+1), and a signal R extracted by the control signal generating means.
e (-1), Re (+1), Im (-1) and Im
A first subtraction circuit and a first averaging circuit for inputting (+1) to generate a control signal Im (-1) -Im (+1) for controlling the first-order amplitude distortion equalization circuit, the second-order amplitude distortion etc. Second adder circuit and second averaging circuit for generating a control signal Re (-1) + Re (+1) for controlling the equalizer circuit, and control signal Im (-1) + Im for controlling the first-order delay distortion equalizer circuit.
A third adder circuit and a third averaging circuit that generate (+1), and a control signal Re that controls the second-order delay distortion equalization circuit.
In an automatic adaptive equalizer having a fourth adder circuit for generating (-1) -Re (+1) and a fourth averaging circuit, a phase plane of each signal of a multilevel digital modulation signal. An area discriminating circuit for discriminating whether or not the existing position on the phase plane is outside a preset signal arrangement area, and is inserted in a path between the control signal generating means and the adding / subtracting means. The in-phase control signals Re (-1) and Re (1) and Re (7) according to the output signal of the area discrimination circuit.
(+1) and switching means for prohibiting passage of the orthogonal control signals Im (-1) and Im (+1).

Here, the adaptive equalization means includes at least one of the primary amplitude distortion equalization circuit, the secondary amplitude distortion equalization circuit, the primary delay distortion equalization circuit, and the secondary delay distortion equalization circuit. You may prepare.

[0009]

The area judgment circuit judges whether or not the received data is within the specified area, and the amplitude of the automatic adaptive equalizer and the delay distortion equalizer circuit from the control signal generator circuit are judged according to the judgment result. Prohibits or permits the output of correlation signals. As a result, the compensation capability can be sufficiently exerted even when the signal points of the modulation method are unique.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a digital demodulator using an automatic adaptive equalizer according to the present invention, and FIG. 2 shows an embodiment of a control signal generating circuit of the automatic adaptive equalizer according to the present invention. 1
Is a digital modulation signal input terminal, 2'is an automatic adaptive equalizer, 3 is a demodulation circuit, 4 is a transversal type equalizer,
Reference numeral 21 is a secondary delay distortion equalization circuit, 22 is a primary delay distortion equalization circuit, 23 is a primary amplitude distortion equalization circuit, 24 is a secondary amplitude distortion equalization circuit, 25 is a control signal generation circuit, and 26 is a region discrimination circuit. Indicates. Further, 101 to 110 are 1-bit delay circuits, 11
1 and 112 are AND circuits, 113 to 11
5 and 117 to 119 are exclusive OR (EX-OR)
Circuits 116 and 120 are exclusive-or negated (EX-
NOR circuit, 125 and 126 are addition circuits, 127
And 128 are subtraction circuits, 129 to 132 are averaging circuits, and 133 to 136 are shift register circuits.

In this embodiment, as shown in FIG. 1, a demodulation circuit 3 and a transversal type equalizer 4 of 2N + 1 taps (N is a positive integer) are connected in a subsequent stage, and a primary amplitude distortion equalization circuit. 23 and a second-order amplitude distortion equalization circuit 24 and an adaptive equalization means including a first-order delay distortion equalization circuit 21 and a second-order delay distortion equalization circuit 22, an error signal generated from a demodulated baseband signal, and a quadrant. Re (-N) is selected from among the in-phase control signals Re (-N) to Re (+ N) corresponding to the transversal equalizer 4 according to the determination signal and the clock signal.
1) and Re (+1) are extracted and the quadrature control signal Im (−) corresponding to the transversal type equalizer 4 is extracted.
Im (-1) and Im among N) to Im (+ N)
Shift registers 133 to 136, which are control signal generating means for extracting (+1), 1-bit delay circuits 101 to 108
And exclusive OR circuits 113 to 120 and the signals Re (-1) and Re (+) extracted by the control signal generating means.
1), Im (-1) and Im (+1) are input to control the first-order amplitude distortion equalization circuit 23. Control signal Im (-1)-
The subtraction circuit 128 and the averaging circuit 132 that generate Im (+1), and the addition circuit 12 that generates the control signal Re (−1) + Re (+1) that controls the secondary amplitude distortion equalization circuit 24.
5 and the averaging circuit 129 and the first-order delay distortion equalizing circuit 22.
Control circuit Im (-1) + Im (+1) for generating the control signal and control signal Re (-1) -R for controlling the quadratic delay distortion equalization circuit 21.
and an adder / subtractor including an adder circuit 127 and an averaging circuit 131 for generating e (+1). Further, as a feature of the present invention, the position of each signal of the multilevel digital modulated signal on the phase plane is present. Is inserted into a path between the control signal generating means and the adding / subtracting means, and the area discriminating circuit 26 for discriminating whether or not the area is outside the preset signal arrangement area on the phase plane. Discrimination circuit 26
Of the in-phase control signals Re (-1) and Re (+1) and the quadrature control signal Im (-1) according to the output signal of
And 1 which is a switching means for prohibiting the passage of Im (+1).
Bit delay circuits 109 and 110, AND circuit 111
And 112 and flip-flop circuits 121 to 1
24 and.

Next, the operation of this embodiment will be described. Here, the flow of the digital signal output from the digital modulation signal input terminal through the automatic adaptive equalizer 2 ', the demodulation circuit 3 and the transversal equalizer 4, and the quadrant determination signal from the output of the demodulation circuit 3 Dp, Dq and error signal Ep,
The signal flow until Eq is input to the automatic adaptive equalizer 2 is the same as in the conventional example. The area discriminating circuit 26 inputs the output data signal of the transversal equalizer 4 and discriminates whether or not the signal point arrangement is in the hatched portion of the signal point arrangement shown in FIG. 5, for example, in the area in the hatched portion. If there is, "0" is output to the control signal generation circuit 25 as the discrimination signal D.
In the control signal generation circuit 25, the quadrant determination signals Dp and Dq and the error signals Ep and Eq are respectively generated in the shift register circuit 1.
The bit delay due to the discrimination signal D having been inputted to 17 to 119 and having passed through the transversal type equalizer 4 is compensated and inputted to the 1-bit delay circuits 101 to 108. 1
In the bit delay circuits 101 to 108, Dp (0), Dp (+1), D
It outputs q (0) and Dq (+1), Ep (0) and Ep (+1), and Eq (0) and Eq (+1). Also, 1
The bit delay circuits 109 to 110 output the determination signals D (0) and D (+1) having the same temporal relationship as the error signals Ep (0) and Ep (+1) or Eq (0) and Eq (+1). .. The discrimination signals D (0) and D (+1) are input to the OR circuits 111 and 112, and the logic is "0".
In the case of, the output of the clock signal which is the other input of the AND circuits 111 and 112 is prohibited. This AND circuit 1
The outputs of 11 and 112 are flip-flop circuits 121.
To 124 clock signals, the in-phase interference control signals Re (-1), Re (+1) or the quadrature interference control signals Im (-1), Im input to the flip-flop circuits 121 to 124 are input. It is not output only when it has the same temporal relationship as the discrimination signal D (0) or D (+1) whose logic is "0" in (+1).

[0013]

As described above, the present invention does not use the control signal of the signal point position which does not actually exist by providing the area discriminating circuit, so that the automatic adaptive type or the like accompanying the deterioration of the frequency characteristic of a certain propagation path can be obtained. This has the effect of preventing malfunction of the control of the chemical converter.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a partial configuration of an embodiment of the present invention.

FIG. 3 is a block configuration diagram showing an overall configuration of a conventional example.

FIG. 4 is a block configuration diagram showing a partial configuration of a conventional example.

FIG. 5 is an area designation diagram.

FIG. 6 is a signal point arrangement diagram.

[Explanation of symbols]

1 Digital Modulation Signal Input Terminal 2 2'Automatic Adaptive Equalizer 3 Demodulator 4 Transversal Equalizer 21 Secondary Delay Distortion Equalizer 22 Primary Delay Distortion Equalizer 23 Primary Amplitude Distortion Equalizer 24 Secondary Amplitude Distortion Equalization Circuit 25 Control Signal Generation Circuit 26 Region Discrimination Circuit 101-110 1-bit Delay Circuit 111, 112 Logical Product (AND) Circuit 113-115, 117-119 Exclusive OR (EX
-OR) circuit 116, 120 Exclusive OR NOT (EX-NOR) circuit 121-124 Flip-flop circuit 125, 126 Adder circuit 127, 128 Subtractor circuit 129-132 Averaging circuit 133-136 Shift register circuit

Claims (2)

[Claims] 1. A demodulation circuit and a 2N + 1-tap (N is a positive integer) transversal type equalizer are connected in a subsequent stage, and a first-order amplitude distortion equalization circuit, a second-order amplitude distortion equalization circuit, and a first-order delay distortion are provided. An adaptive equalizer including an equalizer circuit and a second-order delay distortion equalizer circuit, and the transversal type according to an error signal generated from a baseband signal demodulated by the demodulation circuit, a quadrant determination signal, and a clock signal. Re (-1) out of the in-phase control signals Re (-N) to Re (+ N) corresponding to the equalizer
And Re (+1) are extracted and the orthogonal control signal Im (-N) corresponding to the transversal type equalizer 4 is extracted.
~ Im (+ N) out of Im (-1) and Im (+
1) extracting control signal generating means, and the signal Re (-1) extracted by the control signal generating means,
A control signal Im for inputting Re (+1), Im (-1) and Im (+1) to control the first-order amplitude distortion equalization circuit.
A first subtraction circuit and a first averaging circuit for generating (-1) -Im (+1), and a control signal Re (-1) + Re (+1) for controlling the second-order amplitude distortion equalization circuit. A second addition circuit and a second averaging circuit, a third addition circuit and a third averaging circuit that generate a control signal Im (-1) + Im (+1) for controlling the first-order delay distortion equalization circuit, and the second order Control signal Re (-1) -Re for controlling the delay distortion equalization circuit
In an automatic adaptive equalizer provided with a fourth addition circuit for generating (+1) and an addition / subtraction means including a fourth averaging circuit, the existence position of each signal of the multilevel digital modulation signal on the phase plane is A region discriminating circuit for discriminating whether or not the region is outside the preset signal arrangement region on the phase plane, and the region discriminating circuit inserted in the path between the control signal generating means and the adding / subtracting means. Switching means for inhibiting passage of the in-phase control signals Re (-1) and Re (+1) and the quadrature control signals Im (-1) and Im (+1) according to the output signal of Automatic adaptive equalizer. 2. The adaptive equalizing means comprises at least one of the primary amplitude distortion equalization circuit, the secondary amplitude distortion equalization circuit, the primary delay distortion equalization circuit and the secondary delay distortion equalization circuit. The automatic adaptive equalizer according to claim 1.