JPH0548429A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the number of terminals of the semiconductor integrated circuit. CONSTITUTION:The integrated circuit is provided with a circuit consisting of a DFF circuit 3 and a clock generating circuit 2 to eliminate a short pulse included in a signal inputted from one input terminal 1a and with a circuit comprising an exclusive OR circuit 4 and a TFF circuit 5 whose level changes with the pulse, and an output of the circuit whose level changes with the pulse included in the input signal is used for a 2nd output thereby obtaining two kinds of signals from one input terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit with a reduced number of terminals and a multi-value input from one input terminal.

[0002]

2. Description of the Related Art Recently, the input / output signals of semiconductor integrated circuits are increasing with the increase in scale and functions. Further, in addition to the input / output signal required for actual use, an input / output signal for performing a test or the like may be required. FIG. 9 is a diagram showing an input portion of a conventional semiconductor integrated circuit. In the figure, 1a and 1b are input terminals, 8a and 8b are two circuit blocks built in the same semiconductor integrated circuit, and a circuit block 8a is shown. , 8b are connected to the input terminals 1a, 1b, respectively. The signal input to the input terminal 1a is input to the circuit block 8a, and the signal input to the input terminal 1b is input to the circuit block 8b.

As described above, conventionally, there is a serial data input circuit as means for giving a plurality of values to a plurality of circuit blocks with a small number of pins in response to an increase in input / output signals.
FIG. 10 is a diagram showing a block configuration of a serial data input circuit in which a block for supplying data is a 2 ^m block and a data for supplying is n bits, in which 30 is an input terminal,
Reference numeral 31 is a control signal input terminal, 32 is a serial-parallel converter, 33 is a decoder, 34 is a control signal generator, and 35 is a control signal generator.
Is a data output terminal, and 36 is an address output terminal. 11 (a) to 11 (d) are timing charts for explaining the operation of this serial data input circuit.

Next, the operation will be described. Input terminal 30
The serial input signal shown in Fig. 11 (a) input from
It is given to the serial-parallel converter 32. The control signal input from the control signal input terminal 31 is input to the control signal generation unit 34, generates a necessary control signal to be supplied to the serial-parallel conversion unit 32 and the decoder unit 33, and determines the internal operation state.

Here, the operation of outputting data from the address output terminal 36 and the data output terminal 35 is shown in FIG. 11 (d).
Follow along. The serial data input from the input terminal 30 during the address input period undergoes serial-parallel conversion as shown in FIG. 11 (b) and is determined as an m-bit address signal during the address determination period.
Input to 3.

Similarly, the data input during the data input period is also subjected to serial-parallel conversion as shown in FIG. 11 (b) and is determined as n-bit output data during the data address output period. It is output to the output terminal 35. In the data / address output period, the address input to the decoder unit 33 during the address determination period is as shown in FIG.
As shown in (c), it is decoded and becomes 2 ^m signals, which are output from the address output terminal 36.

As described above, in the semiconductor integrated circuit, n output from the data output terminal 35 is output to the internal block corresponding to the address output from the address output terminal 36.
Gives bit data.

[0008]

The conventional semiconductor integrated circuit shown in FIG. 9 is configured as described above, and in order to give one input signal to one circuit block, the input terminal is provided for each input signal. When one input signal is required and a large number of input signals are provided, the number of terminals is increased because the input terminals are provided accordingly, and the semiconductor integrated circuit becomes inconvenient to handle.
There is a problem that the cost of the package also increases. The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor integrated circuit with a reduced number of terminals.

Further, since the serial data input circuit of the conventional semiconductor integrated circuit shown in FIG. 10 is configured as described above, it is possible to give multivalues to a plurality of blocks inside the semiconductor integrated circuit. However, the circuit scale is redundant and the input signal is slightly complicated when used for simple function switching. Further, there is a problem in that an input terminal for serial data and an input terminal for a control signal are required, and these terminals need to be provided only for inputting serial data.

On the other hand, in the semiconductor integrated circuit, in order to maintain compatibility with the conventional product, it may be necessary to make the terminal arrangement the same as that of the conventional product. In such a case, there is a problem that the serial data input circuit cannot be used. The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor integrated circuit with a reduced number of terminals.

The present invention has been made to solve the above-mentioned problems of the circuit shown in FIG. 10, and its object is to enable multi-value input from one terminal. Another object is to obtain a semiconductor integrated circuit that facilitates addition of functions without changing the specifications of the terminals.

[0012]

A semiconductor integrated circuit according to the present invention is provided with a circuit for removing a pulse shorter than a clock from an input signal of an input terminal, and a circuit for changing an output level by the short pulse. It is a thing. Also,
The semiconductor integrated circuit according to the present invention is provided with a circuit for counting the interval between the pulses.

[0013]

According to the present invention, a circuit for eliminating short pulses, which is connected to one input terminal, ignores short pulses and outputs a fixed signal of H or L, and is connected to the input terminal. By outputting the signal obtained by the circuit that changes the level by the short pulse, two kinds of signals can be obtained from one input terminal, and thus the number of terminals of the semiconductor integrated circuit can be reduced. ..

Further, in the present invention, since the value counted by the circuit for counting the interval between the pulses is output, it is possible to input multiple values from one input terminal.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block configuration of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, 1a is an input terminal,
2 is a clock generation circuit, 3 is a D-type flip-flop (hereinafter referred to as DFF) circuit, 4 is an exclusive OR circuit (hereinafter referred to as EOR circuit), 5 is a T-type flip-flop (hereinafter referred to as TFF) Circuit, 6 is the first output terminal, 7
Is a second output terminal, and 8a and 8b are circuit blocks connected to the first output terminal 6 and the second output terminal 7, respectively. 2 (a) and 2 (b) are timing charts for explaining the operation of the embodiment shown in FIG.

Next, the operation when the H fixed output is applied to the first output terminal 6 will be described with reference to the timing chart of FIG. 2 (a). The clock generation circuit 2 generates the clock shown in FIG. 2 (a) and supplies it to the DFF 3. H is mainly input as an input signal to the input terminal 1a, and an L pulse having a pulse width shorter than that of the clock is given at the timing shown in FIG. 2 (a). As a result, the input short L pulse is DFF.
The output of the circuit 3 is not changed, and H is always output to the first output terminal 6 and applied to the circuit block 8a.

The input terminal 1 is connected to one input of the EOR circuit 4.
The signal input to a is input, and the other input is D
The output of the FF circuit 3 is input, and the output of the DFF circuit 3 is H.
Therefore, an inverted signal of the input signal given to the input terminal 1a appears at the output of the EOR circuit 4. Since the output of this EOR circuit 4 is given to the input of the TFF circuit 5, TF
The output of the F circuit 5 changes from H to L or from L to H each time the input signal applied to the input terminal 1a falls to L. The output of the TFF circuit 5 is output from the second output terminal 7 and given to the circuit block 8b.

Next, the operation when the L fixed output is applied to the first output terminal 6 will be described with reference to the timing chart of FIG. 2 (b). The clock generation circuit 2 generates a clock at the timing shown in FIG. 2 (b), as in the above description of the operation.
L is mainly input as an input signal to the input terminal 1a.
A short H pulse is given at the timing shown in (b). As a result, the input short pulse of H does not change the output of the DFF circuit 3, and L is always output to the first output terminal 6 and applied to the circuit block 8a. Since the signal input to the input terminal 1a appears at the output of the EOR circuit 4,
The output of the TFF circuit 5 changes from H to L or from L to H every time the input signal applied to the input terminal 1a rises to H. The output of this TFF circuit 5 is the second output terminal 7
Is output by the circuit block 8b.

As described above, in this embodiment, since the circuit for removing the short pulse from the input signal and the circuit for changing the output level by the short pulse are provided at the input terminal of the semiconductor integrated circuit, one input terminal is provided. It is possible to obtain two signals, a fixed signal of H or L and a signal in which H and L change, and these two signals can be given to the necessary circuit blocks respectively, so that the input terminals of the semiconductor integrated circuit are Can be reduced.

In the above embodiment, the case where two circuit blocks are included in the integrated circuit has been described.
The same can be applied to the case where more circuit blocks are included, and the same effect as that of the above-described embodiment can be obtained.

FIG. 3 is a block diagram of a semiconductor integrated circuit according to another embodiment of the present invention, in which 10 is an external signal input terminal, 12 is a first clock generating circuit, and 13 is a first clock generating circuit. 2 clock generator circuit, 14 and 17 DFF circuit, 15 EOR circuit, 16 TFF circuit, 1
8 and 19 are AND circuits, 20 is an n-bit counter circuit,
21 is a 3-input OR circuit, 22 is an n-bit DFF circuit, 2
3 is a first output terminal and 24 is a second output terminal.

Next, the structure will be described in detail. The external signal input terminal 10 is a terminal provided in the package portion of the semiconductor integrated circuit, and is internally connected to the data input of the DFF circuit 14 and one input terminal of the EOR circuit 15.

The output of the second clock generation circuit 13 is DF
It is connected to the clock input terminal of the F circuit 14. DF
The output terminal of the F circuit 14 is the first output terminal 23 and the EOR.
It is connected to the other input terminal of the circuit 15. The output terminal of the EOR circuit 15 is the input terminal of the TFF circuit 16 and the AN.
It is connected to one input terminal of the D circuit 18. TFF
The output terminal of the circuit 16 is connected to the data input terminal of the DFF circuit 17 and the other input terminal of the AND circuit 18.

The output terminal of the first clock generation circuit 12 is connected to the clock input terminal of the DFF circuit 17 and the 3-input OR circuit 2
It is connected to one input terminal of 1 and one input terminal of the AND circuit 19. The output terminal of the DFF circuit 17 is AN
It is connected to the other input terminal of the D circuit 19 and one input terminal of the 3-input OR circuit 21. The output terminal of the AND circuit 19 is connected to the clock input terminal of the n-bit counter circuit 20. The output terminal of the AND circuit 18 is connected to the reset signal input terminal of the n-bit counter circuit 20. The output terminal of the n-bit counter circuit 20 is connected to the input terminal of the n-bit DFF circuit 22, respectively. The output terminal of the 3-input OR circuit 21 is connected to the clock input terminal of the n-bit DFF circuit 22. The output terminal of the n-bit DFF circuit 22 is connected to the second output terminal 24.

Next, the operation will be described. The input signal shown in FIG. 4 (a) is the signal input to the external signal input terminal 10,
The first clock shown in FIG. 4 (b) is the clock signal generated by the first clock generation circuit 12, and the second clock shown in FIG. 4 (c).
Clocks represent clock signals generated by the second clock generation circuit 13.

FIGS. 4A to 4L show the external signal input terminal 10
The input signal that is input to is mainly an H level signal and has a short L
It is a timing chart figure which shows operation | movement when it is a signal in which the pulse of the level is inserted.

The second clock shown in FIG. 4 (c) is shown in FIG.
It is a clock having a half cycle of the first clock shown in (b), and is a clock signal that changes at each falling edge of the first clock, and the L level of the input signal shown in FIG. 4 (a). Pulse is shorter than the cycle of the first clock and is inserted at a timing that is not gated at the rising edge of the first clock.

FIG. 4 input to the external signal input terminal 10.
The input signal shown in (a) is input to the DFF circuit 14 and the EOR circuit 15. Since the DFF circuit 15 latches the input signal by the second clock, the L level pulse does not appear in the output, and the H level is always output to the first output terminal 23. At the same time, H is input to one input of the EOR circuit 15.

Since the H level is fixedly input to one input of the EOR circuit 14, an inverted signal of the input signal shown in FIG. 4A is output to the output of the EOR circuit 15. The waveform at point A is shown in Fig. 4 (d). TFF circuit 16 is EOR
Every time the output of the circuit 15 rises to the H level, its output is inverted. The waveform at point B is shown in Fig. 4 (e).

The output of the AND circuit 18 is supplied to the TFF circuit 1
Since the signal at the point A is propagated only when the output of 6 is at H level, a pulse of H level is output when the output of the TFF circuit 16 rises to H level. The waveform at point C is shown in Fig. 4 (f). The DFF circuit 17 takes in and outputs the signal at point B at the falling edge of the first clock generated by the first clock generation circuit 12. The waveform at point D is shown in Fig. 4 (g).

The output signal of the DFF circuit 17 is input to one input of the AND circuit 19, and the first input is input to the other input.
The clock A is input, and the clock A is propagated to its output only while the point D is at the H level. The waveform at point E is shown in FIG.

For the reset input of the n-bit counter circuit 20, the waveform diagram of point C shown in FIG.
The output of 8 is input, and when this goes to H level, the counter is reset. Further, the output signal of the AND circuit 19 is input to the clock input of the n-bit counter circuit 20, and the counter is performed by this signal. As a result, when the first pulse is input to the input signal, the n-bit counter circuit 20 is reset, the interval between the first pulse and the next pulse is counted by the first clock, and the value is output. The waveform at point F is shown in FIG. 4 (i).

The input of the 3-input OR circuit 21 receives the first clock, the output signal of the TFF circuit 16 and the output signal of the DFF circuit 17, respectively, and the n-bit counter circuit 20.
The output is set to H level from the time when the clock is reset to the time when the count is stopped, and the first clock is propagated otherwise. The waveform at point G is shown in FIG. 4 (j).

The n-bit DFF circuit 22 latches the output signal of the n-bit counter circuit 20 at the falling edge of the output signal of the 3-input OR circuit 21 and outputs it. N by the above operation
While the bit counter circuit 20 is being reset or counted, the previous data is held and output. These signals are output from the second output terminal 24 as the second output signal shown in FIG. 4 (k).

FIGS. 5 (a) to 5 (l) show the case where the signal input to the external signal input terminal 10 is mainly an L level signal and a short H level pulse is inserted. It is a timing chart figure which shows operation.

The input signal input to the external signal input terminal 10 is input to the DFF circuit 14 and the EOR circuit 15.
Since the DFF circuit 14 latches the input signal by the second clock, the H level pulse does not appear in the output, and the L level is always output to the first output terminal 23.
At the same time, the L level is input to one input of the EOR circuit 15. Since the L level is fixedly input to one input of the EOR circuit 15, the input signal is propagated to the output of the EOR circuit 15. The subsequent operation is the same as the case where the signal input to the external signal input terminal 10 is a signal mainly having an H level and a pulse having a short L level is inserted.

Although the operation of the embodiment shown in FIG. 3 has been described above, the periods and phases of the first clock and the second clock are not limited to those of this embodiment, and the first output terminal 23 can be externally supplied. Any timing may be used as long as the pulse inserted in the input signal of can be removed.

Needless to say, the second clock generating circuit 13 may be the frequency dividing circuit of the first clock generating circuit 12. FIG. 6 shows a modification of the semiconductor integrated circuit shown in FIG. In the figure, 25, 26 and 29 are DFF circuits, 27a to 27c are OR circuits, and 28 is a 3-input AND circuit.

Next, the configuration will be described in detail. The external signal input terminal 10 is connected to the data input terminal of the DFF circuit 29. The output of the DFF circuit 29 is the DFF circuit 25.
Data input terminal and one of the inputs of the OR circuits 27b and 27c.

The output of the DFF circuit 25 is connected to the input of the DFF circuit 26 and one input of the OR circuits 27a and 27c, respectively. The output of the DFF circuit 26 is the OR circuit 2
7a, 27b and one input of the EOR circuit 15 are respectively connected. The output of the OR circuits 27a to 27c is 3
Each of the three inputs of the input AND circuit 28 is connected. The clock outputs of the first clock generation circuit 12 are connected to the clock inputs of the DFF circuits 25, 26, and 29. The configuration of the other parts is similar to that of the embodiment shown in FIG.

Next, the operation will be described. Figure 7 (a)
8 (j) and FIGS. 8 (a) to 8 (j) are timing charts for explaining the operation of this embodiment. 7 (a) to 7 (j) show the operation in the case where the signal input to the external signal input terminal 10 is mainly H and a pulse of short L level is inserted. This L-level pulse has a width shorter than the cycle of the first clock and is inserted at the timing of being gated at the rising edge of the first clock.

The input signal input from the external signal input terminal 1 is input to the DFF circuit 29. The signal input to the DFF circuit 29 is latched and output by the first clock generated by the first clock generation circuit 12. This K
The waveform of the dots is shown in Fig. 7 (c).

The output of the DFF circuit 29 is input to the DFF circuit 25, latched by the first clock and output.
The waveform at point L is shown in FIG. 7 (d). The output of the DFF circuit 25 is input to the DFF circuit 26, latched by the first clock, and output. The waveform at point M is shown in FIG. 7 (e). As a result, at the points K, L, and M, a signal obtained by latching the L-level pulse inserted in the input signal is output with a delay of one clock.

The DFF circuit 26 is connected to the input of the OR circuit 27a.
And 25, and the output signals of the DFF circuits 26 and 29 are input to the input of the OR circuit 27b.
The output signals of the DFF circuits 25 and 29 are input to the input of the R circuit 27c. Therefore, the OR circuits 27a to 27
The output of c, that is, the waveforms of each of the points H to J are shown in Fig. 7 (f)
All become H level as shown in (h).

The outputs of the OR circuits 27a to 27c are 3-input A.
The signal from the 3-input AND circuit 28, which is input to the ND circuit 28, is output as a first output signal from the first output terminal 23, which is an H level-only signal from which the L level pulse has been removed, and at the same time, the EOR circuit. 15 is input.

Since the output signal of the DFF circuit 26 is also applied to the other input of the EOR circuit 15 and the output of the AND circuit 28 is at the H level, the output of the EOR circuit 15 is the output of the DFF circuit 26. That is, an inverted signal of the signal at point M appears. This is shown in the waveform at point A in FIG. 7 (j). The subsequent circuit operation is similar to that of the embodiment shown in FIG.

In FIGS. 8A to 8J, the signal input to the external signal input terminal 10 is mainly at the L level, and the short H level.
The operation is shown when the signal has a level pulse inserted. This H-level pulse has a width shorter than the cycle of the first clock and is inserted at the timing of being gated at the rising edge of the first clock.

The input signal input from the external signal input terminal 10 is input to the DFF circuit 29, and the DFF circuit 29 is operated by the same operation as in the case where the L level pulse is mainly inserted into the H level signal. , 25, 26 output,
That is, the respective waveforms at points K to M show output signals as shown in FIGS. 8 (c) to 8 (e).

Two of these output signals are input to the OR circuits 27a to 27c, respectively, and their outputs, that is, the waveforms at points H to J are shown in FIGS. 8 (f) to 8 (h). As a result, an L level output is obtained from the 3-input AND circuit 28, and an L level fixed output is obtained from the first output terminal 23.

Further, L is connected to one input of the EOR circuit 15.
Since the level is input and the output signal of the DFF circuit 26 is input to the other input, the EOR circuit 1
The output signal of the DFF circuit 26 propagates to the output of 5. The waveform at point A is shown in FIG. 8 (j). The subsequent operation is the same as in the above embodiment.

In this embodiment, since a circuit for removing a short pulse from the input signal and a circuit for counting the interval of the short pulse are provided at the input terminal of the semiconductor integrated circuit, one input terminal is used. It is possible to obtain a fixed output signal of H or L and an output signal of a value obtained by counting the intervals of the above pulses, and it is possible to give these two signals to necessary circuit blocks respectively. Multi-value input becomes possible, and an increase in the number of input terminals of the semiconductor integrated circuit can be suppressed.

[0052]

As described above, according to the present invention, since the circuit for removing the pulse and the circuit for changing the output level by the pulse are provided at the input terminal of the semiconductor integrated circuit, the output level is fixed. It is possible to obtain two signals, i.e., a signal whose level changes according to the pulse, from one input terminal, and thus it is possible to reduce the number of input terminals of the semiconductor integrated circuit.

Further, according to the present invention, since the circuit for counting the interval between the pulses is provided, multi-valued input is possible from one input terminal, and the increase in the number of input terminals of the semiconductor integrated circuit can be suppressed. effective. Particularly, when a function is added to the conventional semiconductor integrated circuit, there is an effect that the function of the conventional terminal can be maintained and an increase in the number of terminals can be suppressed.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a block configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the semiconductor integrated circuit shown in FIG.

FIG. 3 is a block circuit diagram showing a block configuration of a semiconductor integrated circuit according to another embodiment of the present invention.

FIG. 4 is a timing chart illustrating the operation of the semiconductor integrated circuit shown in FIG.

5 is a timing chart illustrating the operation of the semiconductor integrated circuit shown in FIG.

FIG. 6 is a block circuit diagram showing a block configuration of a semiconductor integrated circuit according to still another embodiment of the present invention.

FIG. 7 is a timing chart illustrating the operation of the semiconductor integrated circuit shown in FIG.

8 is a timing chart illustrating the operation of the semiconductor integrated circuit shown in FIG.

FIG. 9 is a circuit diagram showing an input portion of a conventional semiconductor integrated circuit.

FIG. 10 is a block circuit diagram showing a block configuration of a conventional semiconductor integrated circuit.

FIG. 11 is a timing chart illustrating the operation of the conventional semiconductor integrated circuit.

[Explanation of symbols]

 1a input terminal 1b input terminal 2 clock input terminal 3 DFF circuit 4 EOR circuit 5 TFF circuit 6 first output terminal 7 second output terminal 8a circuit block 8b circuit block 10 external signal input terminal 12 first clock generation circuit 13 Second clock generation circuit 14 DFF circuit 15 EOR circuit 16 TFF circuit 17 DFF circuit 18 AND circuit 19 AND circuit 20 n-bit counter circuit 21 3-input OR circuit 22 n-bit DFF circuit 23 First output terminal 24 Second output Terminal 25 DFF circuit 26 DFF circuit 29 DFF circuit 27a OR circuit 27b OR circuit 27c OR circuit 28 3-input AND circuit

[Procedure amendment]

[Submission date] March 26, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

To the reset input of the n-bit counter circuit 20, the signal at the point C shown in FIG.
When the output of is input and this becomes H level,
The counter is reset. Further, the output signal of the AND circuit 19 is input to the clock input of the n-bit counter circuit 20, and the counter is performed by this signal. As a result, when the first pulse is input to the input signal,
The n-bit counter circuit 20 is reset, counts between the first pulse and the next pulse with the first clock, and outputs the value. The waveform at point F is shown in FIG. 4 (i).

Claims (2)

[Claims] 1. A semiconductor integrated circuit comprising: a circuit for removing a pulse included in a signal input to an input terminal and outputting the same; and a circuit for changing an output level in response to the pulse, the same input A semiconductor integrated circuit characterized by obtaining two kinds of signals from signals. 2. The semiconductor integrated circuit according to claim 1, further comprising a circuit that counts the interval between the pulses.