JPH0547982A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0547982A
JPH0547982A JP20807091A JP20807091A JPH0547982A JP H0547982 A JPH0547982 A JP H0547982A JP 20807091 A JP20807091 A JP 20807091A JP 20807091 A JP20807091 A JP 20807091A JP H0547982 A JPH0547982 A JP H0547982A
Authority
JP
Japan
Prior art keywords
semiconductor chip
insulating tape
lead
tape
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20807091A
Other languages
Japanese (ja)
Other versions
JP2937564B2 (en
Inventor
Susumu Harada
田 享 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20807091A priority Critical patent/JP2937564B2/en
Publication of JPH0547982A publication Critical patent/JPH0547982A/en
Application granted granted Critical
Publication of JP2937564B2 publication Critical patent/JP2937564B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a semiconductor device in which a large-sized chip can be placed in a small-sized semiconductor package, wire bonding to inner leads on the chip can be disused and the length of the inner lead can be sufficiently provided. CONSTITUTION:In a semiconductor device, an insulation tape 2 is disposed on the upper surface of a semiconductor chip 1, ends of leads 3 are disposed on the tape 2, the ends of inner leads 3a of the leads 3 are respectively electrically connected to electrodes 1a of the chip 1, and wirings 6 extended to the side of the tape 2 are provided on the upper surface of the tape 2. The ends of the inner leads 3a of the leads 3 disposed at the ends on the tape 2 through the wirings 6 are respectively electrically connected to the electrodes 1a of the chip 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置、特に例えば
4Mbit以上の容量を有するDRAM等に使用して最
適で、かつ大型半導体チップを小型の半導体パッケージ
に搭載できるようにした半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device which is suitable for use in, for example, a DRAM having a capacity of 4 Mbit or more, and in which a large semiconductor chip can be mounted in a small semiconductor package.

【0002】[0002]

【従来の技術】従来、上記大型半導体チップを小型の半
導体パッケージに搭載するようにしたものとしては、例
えば日経マイクロデバイス、1988年5月号、第54
頁〜第57頁「“隠し玉”,300ミルに大チップを入
れるリードフレーム」として、リードフレームのダイパ
ッドを無くすとともにこのインナーフレームを半導体チ
ップの上或いは下に引き回すようにしたものが提案され
ている。
2. Description of the Related Art Conventionally, the large-sized semiconductor chip is mounted on a small-sized semiconductor package, for example, Nikkei Microdevice, May 1988, No. 54.
Pp.57-57 "" Hidden Ball ", a lead frame that puts large chips in 300 mils", is proposed in which the die pad of the lead frame is eliminated and the inner frame is routed above or below the semiconductor chip. There is.

【0003】即ち、図3及び図4に示すように、半導体
チップ1の上面にポリイミドテープ等の緩衝部材たる絶
縁テープ2を貼付け、この絶縁テープ2の上面に幾つか
のリード3のインナーリード3aを位置させて、上記半
導体チップ1の各電極1aと各インナーリード3aの先
端をボンディングワイヤ4で電気的に接続した後、アウ
ターリード3bを外部に露出させた状態で封止樹脂5で
樹脂封止し、後工程を施して半導体装置を構成したもの
である。
That is, as shown in FIGS. 3 and 4, an insulating tape 2 which is a buffer member such as a polyimide tape is attached to the upper surface of the semiconductor chip 1, and the inner leads 3a of some leads 3 are attached to the upper surface of the insulating tape 2. Position, and each electrode 1a of the semiconductor chip 1 and the tip of each inner lead 3a are electrically connected by the bonding wire 4, and then the outer lead 3b is exposed to the outside and resin-sealed with the sealing resin 5. After that, the semiconductor device is configured by performing a post process.

【0004】ここに、上記絶縁テープ2上に位置するイ
ンナーリード3aの先端へのボンディングワイヤ4のボ
ンディングは、半導体チップ1を土台としてこの絶縁テ
ープ2の上で行われることになる。
The bonding wire 4 is bonded to the tip of the inner lead 3a located on the insulating tape 2 on the insulating tape 2 with the semiconductor chip 1 as a base.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記の
ようにインナーリードへのボンディングワイヤのボンデ
ィングは、緩衝部材たる絶縁テープの上で行われること
になるため、ボンディング時に超音波や荷重が十分に伝
わらずに、ここでのボンディングワイヤの接合が困難か
つ不安定となってしまうことがある。
However, since the bonding wire is bonded to the inner lead on the insulating tape as the buffer member as described above, ultrasonic waves and load are sufficiently transmitted during bonding. Instead, bonding of the bonding wire here may be difficult and unstable.

【0006】また、半導体チップ上にシリコン等の異物
が付着していて、この上部でインナーリードへのワイヤ
ボンディングが行われると、絶縁テープにより緩衝が十
分に行われずに、土台となる半導体チップが損傷してし
まうことがあり、半導体チップ上でインナーリードにワ
イヤボンディングを行うことは半導体装置としての信頼
性を得る上で好ましくない。
If foreign matter such as silicon adheres to the semiconductor chip and the wire bonding to the inner lead is performed on the foreign matter, the insulating tape does not sufficiently cushion the semiconductor chip to form a base semiconductor chip. Since it may be damaged, it is not preferable to wire-bond the inner leads on the semiconductor chip in order to obtain reliability as a semiconductor device.

【0007】更に、図3及び図4に示すように、インナ
ーリードが他のそれと比較してかなり短いリードが一部
含まれてしまうことがあり、このようなリードにあって
は、耐湿性が悪く、リードの引抜き強度が低下してしま
うといった問題点があると考えられる。
Further, as shown in FIGS. 3 and 4, the inner lead may include a part of the lead which is considerably shorter than the other inner leads, and such a lead has a moisture resistance. Poorly, it is considered that there is a problem that the lead pull-out strength is lowered.

【0008】本発明は上記問題点に鑑み、大型の半導体
チップを小型の半導体パッケージに搭載することがで
き、しかも半導体チップ上でのインナーリードへのワイ
ヤボンディングを廃止するとともに、インナーリードの
長さを十分に取るようにすることができるようにしたも
のを提供することを目的とする。
In view of the above problems, the present invention allows a large semiconductor chip to be mounted in a small semiconductor package, eliminates wire bonding to the inner lead on the semiconductor chip, and increases the length of the inner lead. The purpose is to provide something that can be taken sufficiently.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するた
め、本発明に係る半導体装置は、半導体チップの上面に
絶縁テープを、この絶縁テープの上にリードを夫々配置
しこのリードのインナーリードの先端と上記半導体チッ
プの各電極とを電気的に接続した半導体装置において、
上記絶縁テープの上面に該テープの側方まで延出する配
線を施し、この配線を介して上記各インナーリードの先
端と半導体チップの各電極とを夫々電気的に接続したも
のであり、上記配線を絶縁テープの内部まで入り込ませ
ることにより、インナーリードを長くするようにするこ
ともできる。
In order to achieve the above object, a semiconductor device according to the present invention has an insulating tape on the upper surface of a semiconductor chip and leads on the insulating tape. In a semiconductor device in which the tip and each electrode of the semiconductor chip are electrically connected,
Wiring extending to the side of the tape is provided on the upper surface of the insulating tape, and the tip of each inner lead and each electrode of the semiconductor chip are electrically connected via the wiring. It is also possible to make the inner lead longer by inserting the inside of the insulating tape.

【0010】[0010]

【作用】上記にように構成した本発明によれば、各イン
ナーリードの先端と半導体チップの各電極とは、絶縁テ
ープに施された配線を介して接続されるので、先ずイン
ナーリードと絶縁テープの配線の一端とを接合させ、し
かる後にこの配線の他端と半導体チップの電極とを接合
させることにより、半導体チップ上でのワイヤボンディ
ングを廃止することができる。
According to the present invention having the above-described structure, the tips of the inner leads and the electrodes of the semiconductor chip are connected to each other through the wiring provided on the insulating tape. The wire bonding on the semiconductor chip can be abolished by joining one end of the wiring and then joining the other end of the wiring and the electrode of the semiconductor chip.

【0011】また、上記配線を絶縁テープの内部まで入
り込ませて、インナーリードを長くすることにより、リ
ードの耐湿性及び引抜き強度の向上を図ることができ
る。
Further, by inserting the above wiring into the inside of the insulating tape and lengthening the inner lead, it is possible to improve the moisture resistance and pull-out strength of the lead.

【0012】[0012]

【実施例】以下、本発明の一実施例を図1及び図2を参
照して説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

【0013】例えば4Mbit以上の容量を有するDR
AMたる半導体チップ1の上面には、この両側縁に設け
た電極1aを露出させて状態で、ポリイミドテープ等の
緩衝部材たる絶縁テープ2が貼付けられている。
For example, a DR having a capacity of 4 Mbit or more
On the upper surface of the semiconductor chip 1 which is an AM, an insulating tape 2 which is a buffer member such as a polyimide tape is attached with the electrodes 1a provided on both side edges thereof being exposed.

【0014】この絶縁テープ2の表面には、鉤形に屈曲
して幅方向に延び、その先端を該絶縁テープ2の側方ま
で突出させた複数の配線6が施されているとともに、各
配線6は、下方に屈曲してこの突出端の下面が、絶縁テ
ープ2の裏面で構成される平面の下方に位置するような
されている。
The surface of the insulating tape 2 is provided with a plurality of wirings 6 which are bent in a hook shape and extend in the width direction, and the tips of which are projected to the side of the insulating tape 2 and each wiring. 6 is bent downward so that the lower surface of this protruding end is located below the plane formed by the back surface of the insulating tape 2.

【0015】そして、この各配線6の基端部は、上記絶
縁テープ2の上面に配置された直線状のリード3のイン
ナーリード3aの先端にバンプ7を介して結合され、突
出端はここに設けた下方への突起部6aの及びバンプ8
を介して半導体チップ1の各電極1aに結合され、これ
により、この各配線6を介して半導体チップ1の各電極
1aと各リード3のインナーリード3aの先端が電気的
に接続されているとともに、各インナーリード3aと配
線6とが互いに重合しないようなされている。
The base end of each wire 6 is connected to the tip of the inner lead 3a of the linear lead 3 arranged on the upper surface of the insulating tape 2 via a bump 7, and the protruding end is located here. Providing downward protrusion 6a and bump 8
Are connected to the respective electrodes 1a of the semiconductor chip 1 via the wirings, whereby the respective electrodes 1a of the semiconductor chip 1 and the tips of the inner leads 3a of the leads 3 are electrically connected via the respective wirings 6. The inner leads 3a and the wiring 6 are designed not to overlap with each other.

【0016】更に、上記リード3には、その両側面及び
下面に連続する段部3cが設けられ、これによって、イ
ンナーリード3aのこの段部3cから先端部までをアウ
ターリード3bより細くして、耐湿性及びリード引抜き
強度を向上させるようなさせている。
Further, the lead 3 is provided with a stepped portion 3c which is continuous on both side surfaces and a lower surface thereof, whereby the portion from the stepped portion 3c of the inner lead 3a to the tip end thereof is made thinner than the outer lead 3b. It is designed to improve the moisture resistance and the lead extraction strength.

【0017】そして、アウターリード3bを外部に露出
させた状態で、封止樹脂5で樹脂封止して半導体装置を
構成するである。
Then, the outer leads 3b are exposed to the outside, and a semiconductor device is formed by resin-sealing with the sealing resin 5.

【0018】上記、各インナーリード3aの先端と半導
体チップ1の各電極1aとの絶縁テープ2に施された配
線6による接続は次のようにして行う。
The connection between the tip of each inner lead 3a and each electrode 1a of the semiconductor chip 1 by the wiring 6 provided on the insulating tape 2 is performed as follows.

【0019】即ち、先ずインナーリード3aと絶縁テー
プ2の配線6の一端とをバンプ7を介して接合させ、し
かる後、この配線6の他端と半導体チップ1の電極1a
とを接合させる。これにより、半導体チップ1上でのワ
イヤボンディングを廃止して、ボンディングによる半導
体チップの損傷を防止することができる。
That is, first, the inner lead 3a and one end of the wiring 6 of the insulating tape 2 are bonded via the bump 7, and then the other end of this wiring 6 and the electrode 1a of the semiconductor chip 1 are joined.
Join and. As a result, wire bonding on the semiconductor chip 1 can be eliminated and damage to the semiconductor chip due to bonding can be prevented.

【0020】更に、インナーリード3aを半導体チップ
1の上面の内部まで進入させることにより、モールド外
枠からインナーリード3aと配線6との接合部までの距
離Lを長くして、耐湿性を増大させるとともに、リード
引抜き強度を向上させることができる。
Further, by inserting the inner lead 3a into the upper surface of the semiconductor chip 1, the distance L from the outer frame of the mold to the joint between the inner lead 3a and the wiring 6 is lengthened to increase the moisture resistance. At the same time, the lead extraction strength can be improved.

【0021】[0021]

【発明の効果】本発明は上記のような構成であるので、
大型の半導体チップを小型の半導体パッケージに搭載す
ることができるとともに、各インナーリードの先端と半
導体チップの各電極とは、絶縁テープに施された配線を
介して接続され、従って、先ずインナーリードと絶縁テ
ープの配線の一端とを接合させ、しかる後にこの配線の
他端と半導体チップの電極とを接合させるようにするこ
とができるので、これにより、半導体チップ上でのワイ
ヤボンディングを廃止して、インナーリードの接合不良
及び接合の際の半導体チップの損傷を防止することがで
きる。
Since the present invention has the above-mentioned structure,
A large semiconductor chip can be mounted in a small semiconductor package, and the tip of each inner lead and each electrode of the semiconductor chip are connected via a wiring provided on an insulating tape. Since it is possible to join one end of the wiring of the insulating tape and then join the other end of this wiring and the electrode of the semiconductor chip, thereby eliminating wire bonding on the semiconductor chip, It is possible to prevent the joint failure of the inner leads and the damage of the semiconductor chip at the time of joining.

【0022】また、絶縁テープに施された配線を該絶縁
テープの内部まで入り込ませてインナーリードを長くす
ることができ、これによってリードの耐湿性及び引抜き
強度の向上を図ることができるといった効果がある。
Also, the wiring provided on the insulating tape can be inserted into the inside of the insulating tape to lengthen the inner lead, which can improve the moisture resistance and pull-out strength of the lead. is there.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す半導体チップとインナ
ーリードとを結線させた状態の平面図。
FIG. 1 is a plan view showing a state in which a semiconductor chip and an inner lead according to an embodiment of the present invention are connected.

【図2】同じく樹脂封止後の要部拡大断面図。FIG. 2 is an enlarged cross-sectional view of an essential part after resin sealing.

【図3】従来例を示す一部を切り欠いた要部斜視図。FIG. 3 is a perspective view of a main part with a part cut away showing a conventional example.

【図4】同じく平面図。FIG. 4 is a plan view of the same.

【符号の説明】[Explanation of symbols]

1 半導体チップ 1a 同電極 2 絶縁テープ 3 リード 3a インナーリード 3b アウターリード 5 封止樹脂 6 配線。 1 semiconductor chip 1a same electrode 2 insulating tape 3 lead 3a inner lead 3b outer lead 5 sealing resin 6 wiring.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体チップの上面に絶縁テープを、この
絶縁テープの上にリード先端部を夫々配置しこのリード
のインナーリードの先端と上記半導体チップの各電極と
を電気的に接続した半導体装置において、上記絶縁テー
プの上面に該テープの側方まで延出する配線を施し、こ
の配線を介して上記絶縁テープの上に先端部を配置した
各リードのインナーリードの先端と半導体チップの各電
極とを夫々電気的に接続したことを特徴とする半導体装
置。
1. A semiconductor device in which an insulating tape is provided on the upper surface of a semiconductor chip, and lead tips are arranged on the insulating tape, and the tips of inner leads of the leads are electrically connected to the electrodes of the semiconductor chip. In the above, the upper surface of the insulating tape is provided with wiring extending to the lateral side of the tape, and the tip of the inner lead of each lead having the tip disposed on the insulating tape via this wiring and each electrode of the semiconductor chip. A semiconductor device characterized in that and are electrically connected to each other.
【請求項2】上記絶縁テープに施された配線を該テープ
の内部まで入り込ませることにより、インナーリードの
長さを長くしたことを特徴とする請求項1記載の半導体
装置。
2. The semiconductor device according to claim 1, wherein the length of the inner lead is increased by inserting the wiring provided on the insulating tape into the inside of the tape.
JP20807091A 1991-08-20 1991-08-20 Semiconductor device Expired - Fee Related JP2937564B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20807091A JP2937564B2 (en) 1991-08-20 1991-08-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20807091A JP2937564B2 (en) 1991-08-20 1991-08-20 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP10929499A Division JP3170259B2 (en) 1999-04-16 1999-04-16 Semiconductor device manufacturing method and semiconductor device

Publications (2)

Publication Number Publication Date
JPH0547982A true JPH0547982A (en) 1993-02-26
JP2937564B2 JP2937564B2 (en) 1999-08-23

Family

ID=16550150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20807091A Expired - Fee Related JP2937564B2 (en) 1991-08-20 1991-08-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2937564B2 (en)

Also Published As

Publication number Publication date
JP2937564B2 (en) 1999-08-23

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