JPH0547980A - Ic lead frame for semiconductor device - Google Patents

Ic lead frame for semiconductor device

Info

Publication number
JPH0547980A
JPH0547980A JP22344391A JP22344391A JPH0547980A JP H0547980 A JPH0547980 A JP H0547980A JP 22344391 A JP22344391 A JP 22344391A JP 22344391 A JP22344391 A JP 22344391A JP H0547980 A JPH0547980 A JP H0547980A
Authority
JP
Japan
Prior art keywords
lead frame
semiconductor device
internal leads
lead
dimensional accuracy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22344391A
Other languages
Japanese (ja)
Inventor
Tsukasa Tokunaga
司 徳永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP22344391A priority Critical patent/JPH0547980A/en
Publication of JPH0547980A publication Critical patent/JPH0547980A/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the dimensional accuracy of an IC lead frame for semiconductor device use, which is manufactured by a press punching work, by a method wherein the form of the internal leads of the IC lead frame for semiconductor use is constituted into a waveform form having bent parts, more than two pieces of which are different from one another in direction. CONSTITUTION:Parts of internal leads of an IC lead frame for QFP type semiconductor device use excepting bonding areas (coining areas at the time of a press work) on the tips of the internal leads are provided with bent parts A, B and C, which are different from one another in direction. Accordingly, a difference between plastic shrinkages, which are generated in the left and right sides of the internal leads, is reduced and differences between stresses, which are inflicted on the left and right sides of the internal leads, are brought near to equality. Thereby, the deformation and positional deviation of the internal leads in after a press punching work can be prevented from being generated and the dimensional accuracy of the IC lead frame for semiconductor device use is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置用ICリ−
ドフレ−ムの内部リ−ドの形状に関するものである。
BACKGROUND OF THE INVENTION The present invention relates to an IC reader for semiconductor devices.
The present invention relates to the shape of the inner lead of the dframe.

【0002】[0002]

【従来の技術】従来、半導体装置用ICリ−ドフレ−ム
の内部リ−ドの形状は、図2に示すように一個所の屈曲
部Dを有し、その先はパッド方向に向かって直線的に延
びるように構成されている。また、図3に示すように二
個所以上の屈曲部を有する場合でも同一方向に屈曲する
ように構成されており、方向の異なる屈曲部を有する波
型形状に構成するものは製造されていなかった。
2. Description of the Related Art Conventionally, the shape of the inner lead of an IC lead frame for a semiconductor device has a single bent portion D as shown in FIG. It is configured to extend in a horizontal direction. Further, as shown in FIG. 3, even when it has two or more bending portions, it is configured to bend in the same direction, and a corrugated shape having bending portions with different directions has not been manufactured. ..

【0003】他方、プレス打ち抜き加工によって半導体
装置用ICリ−ドフレ−ムを製造する場合、図4および
図5に示すように内部リ−ド形状の凸側と凹側とでは、
プレス打ち抜き加工による塑性的な縮みに差があるの
で、同一方向に屈曲した形状では、プレス打ち抜き加工
後の内部リ−ドの変形や位置ずれを起こすことになり、
半導体装置用ICリ−ドフレ−ムの寸法精度を劣化させ
るという問題があった。
On the other hand, in the case of manufacturing an IC lead frame for a semiconductor device by press punching, as shown in FIGS. 4 and 5, on the convex side and the concave side of the inner lead shape,
Since there is a difference in plastic shrinkage due to press punching, a shape bent in the same direction will cause deformation and displacement of the internal lead after press punching,
There is a problem that the dimensional accuracy of the IC lead frame for semiconductor devices is deteriorated.

【0004】[0004]

【発明が解決しようとする課題】本発明は、以上のよう
な課題を解決するためになされたもので、二個所以上
の、方向の異なる屈曲部を設けて波型形状に構成するこ
とによって、内部リ−ドの左右の辺に生じる塑性的な縮
みの差を小さくして、内部リ−ドの左右の辺に与えられ
る応力の差を均等に近づけ、プレス打ち抜き加工後の内
部リ−ドの変形や位置ずれを防止し、半導体装置用IC
リ−ドフレ−ムの寸法精度を向上することを課題とする
ものである。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is possible to form a corrugated shape by providing two or more bent portions with different directions. The difference in plastic shrinkage that occurs on the left and right sides of the inner lead is made smaller so that the difference in stress applied to the left and right sides of the inner lead is evenly approached, and the inner lead after press punching Prevents deformation and displacement, and ICs for semiconductor devices
It is an object to improve the dimensional accuracy of the lead frame.

【0005】[0005]

【課題を解決するための手段】本発明は、半導体装置用
ICリ−ドフレ−ムの内部リ−ドの形状を、二個所以上
の、方向の異なる屈曲部を有する波型形状に構成するこ
とを特徴とする半導体装置用ICリ−ドフレ−ムであ
る。
According to the present invention, the shape of the inner lead of the IC lead frame for a semiconductor device is formed in a corrugated shape having two or more bent portions in different directions. Is an IC lead frame for a semiconductor device.

【0006】[0006]

【作用】図4および図5は、半導体装置用ICリ−ドフ
レ−ムの曲げ加工時の屈曲部の応力状態を示す線図およ
び説明図である。すなわち、屈曲部の角度θが180°
以下では屈曲部から流れだす方向に、また、180°以
上では流れ込む方向に応力が働く。この両方向の応力は
均等ではないので、加工後の変形の原因となる。本発明
では、このような屈曲部を二個所以上設けることによっ
てバランスをとり、加工後の変形や位置ずれを防止でき
るように構成したものである。
4 and 5 are a diagram and an explanatory view showing a stress state of a bent portion of an IC lead frame for a semiconductor device during bending. That is, the angle θ of the bent portion is 180 °
Below, stress acts in the direction of flowing out from the bent portion and in the direction of flowing in at 180 ° or more. Since the stress in both directions is not uniform, it causes deformation after processing. In the present invention, by providing two or more such bent portions, it is possible to achieve a balance and prevent deformation and displacement after processing.

【0007】[0007]

【実施例】図1に示す本発明にかかる半導体装置用IC
リ−ドフレ−ムにしたがって実施例を説明する。図1は
QFPタイプの半導体装置用ICリ−ドフレ−ムに適用
した例を示したもので、内部リ−ド先端のボンディング
エリア(プレス加工時のコイニングエリア)を除いた部
分で、方向の異なる屈曲部A、BおよびCを設けてあ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor device IC according to the present invention shown in FIG.
An embodiment will be described according to the lead frame. FIG. 1 shows an example applied to a QFP type IC lead frame for a semiconductor device, in which the direction is different except for the bonding area (coining area at the time of pressing) at the tip of the internal lead. Bends A, B and C are provided.

【0008】発明者は、リ−ドピッチを種々変えた場合
の半導体装置用ICリ−ドフレ−ムの寸法精度の変化
を、リ−ド寄り量の変化として把握して製造実験をおこ
ない、表1に示すような実験結果をえた。ここで、リ−
ド寄り量とは、設定値と実測値とのずれの寸法のことで
あり、表1の数値は30個所の測定値の平均値である。
また、リ−ド幅は、(リ−ドピッチ×0.5)とし、ま
た、抜き幅は、(リ−ドピッチ×0.5)とし、各屈曲
部の角度は22°として実験をおこなった。
The inventor grasped the change in the dimensional accuracy of the IC lead frame for a semiconductor device when the lead pitch was variously changed as a change in the lead deviation amount, and conducted a manufacturing experiment. The experimental results are shown in. Where
The deviation amount is a dimension of a deviation between the set value and the actually measured value, and the numerical value in Table 1 is an average value of the measured values at 30 points.
Further, the lead width was set to (lead pitch × 0.5), the draft width was set to (lead pitch × 0.5), and the angle of each bent portion was set to 22 °.

【0009】[0009]

【表1】 [Table 1]

【0010】表1から明らかなように、本発明による
と、リ−ド寄り量(平均値)は従来法の1/3〜1/5
程度まで減少することができ、半導体装置用ICリ−ド
フレ−ムの寸法精度を飛躍的に向上することができた。
なお、この時使用する打ち抜きパンチの形状は、同様に
波型形状となり、従来の直線状のパンチに比較して、プ
レス打ち抜き加工時に打ち抜きパンチのたわみを減少す
ることができ、パンチの寿命を延長するとともに生産性
を向上することができた。
As is apparent from Table 1, according to the present invention, the lead deviation amount (average value) is 1/3 to 1/5 of the conventional method.
The dimensional accuracy of the IC lead frame for a semiconductor device could be dramatically improved.
In addition, the punching punch used at this time has a corrugated shape as well, and it is possible to reduce the deflection of the punching punch during press punching and extend the life of the punch as compared with the conventional linear punch. It was possible to improve productivity as well.

【0011】[0011]

【発明の効果】以上のように、本発明によると、半導体
装置用ICリ−ドフレ−ムの寸法精度を飛躍的に向上す
ることができるとともに、プレス用パンチの寿命を延長
する効果も奏することができる。
As described above, according to the present invention, the dimensional accuracy of the IC lead frame for a semiconductor device can be dramatically improved, and at the same time, the life of the punch for press can be extended. You can

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明にかかる半導体装置用ICリ−ドフレ−
ムの斜視図である。
FIG. 1 is an IC lead frame for a semiconductor device according to the present invention.
FIG.

【図2】従来の半導体装置用ICリ−ドフレ−ムの一例
を示す斜視図である。
FIG. 2 is a perspective view showing an example of a conventional IC lead frame for a semiconductor device.

【図3】従来の半導体装置用ICリ−ドフレ−ムの一例
を示す平面図である。
FIG. 3 is a plan view showing an example of a conventional IC lead frame for a semiconductor device.

【図4】本発明の作用を説明する屈曲部の応力状態を示
す線図てある。
FIG. 4 is a diagram showing a stress state of a bent portion for explaining the operation of the present invention.

【図5】本発明の作用を説明する屈曲部の応力状態を示
す説明図てある。
FIG. 5 is an explanatory view showing a stress state of a bent portion for explaining the operation of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体装置用ICリ−ドフレ−ム A 第一の屈曲部 B 第二の屈曲部 C 第三の屈曲部 D 屈曲部 θ 屈曲部の角度 1 IC lead frame for semiconductor device A First bent portion B Second bent portion C Third bent portion D Bent portion θ Bent angle

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置用ICリ−ドフレ−ムの内部
リ−ドの形状を、二個所以上の、方向の異なる屈曲部を
有する波型形状に構成することを特徴とする半導体装置
用ICリ−ドフレ−ム。
1. An IC lead for a semiconductor device, characterized in that the shape of the inner lead of the IC lead frame for a semiconductor device is formed in a corrugated shape having two or more bent portions in different directions. Lead frame.
JP22344391A 1991-08-08 1991-08-08 Ic lead frame for semiconductor device Pending JPH0547980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22344391A JPH0547980A (en) 1991-08-08 1991-08-08 Ic lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22344391A JPH0547980A (en) 1991-08-08 1991-08-08 Ic lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0547980A true JPH0547980A (en) 1993-02-26

Family

ID=16798225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22344391A Pending JPH0547980A (en) 1991-08-08 1991-08-08 Ic lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0547980A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7148564B2 (en) * 2004-02-17 2006-12-12 Delphi Technologies, Inc. Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5422770A (en) * 1977-07-22 1979-02-20 Hitachi Ltd Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5422770A (en) * 1977-07-22 1979-02-20 Hitachi Ltd Lead frame

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7148564B2 (en) * 2004-02-17 2006-12-12 Delphi Technologies, Inc. Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness
US7697303B2 (en) 2004-02-17 2010-04-13 Delphi Technologies, Inc. Dual-sided substrate integrated circuit package including a leadframe having leads with increased thickness

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