JPH0546575A - Setting system for parallel computer message packet transfer path determination table - Google Patents

Abstract

PURPOSE:To suppress the rate of an increase of the set time of the table for an increase in the number of processors in a parallel processor device which has information for determining a message packet transfer path as rewritable tables in individual processors. CONSTITUTION:The operation of front-end processors in the setting of the transfer path determination tables is so determined 2a that the generation and generation of the tables are not all performed and values as parameters necessary for the setting of the tables are only supplied to the individual processors. The transfer path determination tables are generated by the individual processors independently after the parameters are distributed by the front-end processors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer path determination table setting method for a parallel processor having a message packet transfer path determination table that can be rewritten by individual processors.

[0002]

2. Description of the Related Art A parallel processor device as shown in FIG. 1 can be considered as one of parallel processor devices which can determine a message packet transfer route based on information in a table having the inside and can reset the table. ing. This parallel processor device has a processor group 2 composed of a plurality of processors 1 connected in a two-dimensional lattice, and a front end processor 3 for starting up the parallel processors.

Information is exchanged between processors by transferring packets. When the processors 1 receive the packets, since the processors 1 are connected in a grid pattern as shown in FIG. 1, the processor 1 determines in which direction the packets are transferred based on the internal transfer path determination table. Or, decide whether or not to receive it yourself. The operation when the processor 1 receives a packet and passes it to another processor 1 will be described with reference to FIG. In FIG. 4A, the communication path i connecting the processors 1L and 1M is referred to as a channel, and the other portions are also the same.
Here, an example is given in which a packet passes from the processor 1L through the channel i, enters the processor 1M, and exits to the processor 1N. As shown in FIG. 4B, the transfer path determination table 4 is a two-dimensional table of destination processors and input channels. If packet 5 comes in,
The packet 5 indicates the destination processor number, and the channel j to which the packet 5 is input determines the channel j to be transferred. Processor 1
When the packet 5 is sent from L to the processor 1M through the channel i, the transfer destination channel j is selected as the transfer direction of the packet 5 and sent to the processor 1N. The transfer path determination table 4 is unique to each processor and is different for each processor. 5A and 5B show the flow of setting in this table.
FIG. 5A shows a processing flow of the front-end processor 3, and FIG. 5B shows a processing flow of the other processors 1. Front-end processor 3
Creates a transfer path determination table 4 for one processor (5
a), and sends it to the corresponding processor 1 (5b). The other processors 1 wait for the transfer path determination table 4 from the front end processor 3 to be sent, and then take in the sent one (5b). The front-end processor 3 sequentially performs this operation for all the processors 1, whereby the setting of the transfer path determination table 4 is completed. Figure 6
6A shows the state of each processor at this time, and FIG. 6A shows the state when the front-end processor 3 is creating the transfer path determination table 4, which is indicated by 5a in FIG. Equivalent to. FIG. 6B shows a state when the created transfer path determination table 4 is being sent to the corresponding processor 1, and corresponds to 5b in FIG. In this case, what is sent to the processor 1 is the transfer path determination table 4 itself.

[0004]

The size of the transfer path determination table is proportional to the number of parallel processors. In the above-mentioned conventional setting method, since all the information to be set is created by the front-end processor and sent to each processor, as the number of processors increases,
The time required for the setting becomes proportional to the square of the number of processors due to the increase in the number of processors and the information set in the transfer route determination table. This point becomes a problem when the number of parallel processors is significantly increased.

The present invention has been made to solve the above problems, and an object thereof is to shorten the time required for setting a transfer route determination table.

[0006]

The problem of the conventional example is that the work load required for setting the transfer route determination table is concentrated on the front-end processor (local). Therefore, in the setting method according to the present invention, in the parallel processor device having the information for determining the message packet transfer path of the parallel processor as a rewritable table inside each processor, the table setting is made for each processor. The necessary parameters are given so that each processor can set the internal table.

[0007]

As described above, in the method of the present invention, each processor sets its own transfer path determination table. In this case, the size of the transfer routing table, that is, the time required to create the transfer routing table of its own, and the time required to distribute the parameters necessary for setting them from the front-end processor to the individual processors. Will be proportional to the number of processors. As described above, in the method of the present invention, the time required for setting can be reduced as compared with the conventional setting method that requires time and effort proportional to the square of the number of processors.

[0008]

EXAMPLES Examples of the present invention will be described below. Figure 1
Shows an example of the configuration of a parallel processor device to which the present invention is applied. As described above, from the processor group 2 including the front-end processor 3 and a plurality of processors 1 connected in a two-dimensional lattice pattern. It is configured.

FIG. 2 shows the flow of processing when the present invention is used. FIG. 2 (A) shows the flow of processing of the front-end processor 3, and FIG. 2 (B) shows the other processor 1. The respective processing flows are shown. The process is composed of two processes, a part (2a) for sending a parameter from the front-end processor 3 to each processor 1 and a part (2b) for each processor 1 to create its own transfer path determination table. First, the front-end processor 3
Gives parameters to each processor 1 (2
a). On the other hand, each of the other processors 1 receives the parameter (2a) and then creates the transfer route determination table (2b). FIG. 3 shows the states of the processors in the portions 2a and 2b of FIG. 2 showing the flow of processing when the present invention is used. FIG. 3A shows a state when parameters are set from the front-end processor 3 to another processor 1, and FIG. 3B shows a state when a transfer route determination table based on the parameters is created.

As described above, in this method, the transfer route determination table 4
The work of the front-end processor 3 in the setting of
All the creation and transfer of the table are not performed, but only the values serving as the parameters are given to the individual processors 1. The transfer path determination table 4 is created by each processor 1 after the front end processor 3 distributes the parameters. In this case, regarding the method of setting parameters for each processor 1, it is premised that the front-end processor 3 and the parallel processor 1 have a broadcast function that is a function of simultaneously giving the same information to all the processors. The setting method in two different cases, one case and the other case, will be described. The parameter setting when the broadcast function is provided is that the front-end processor 3 uses the broadcast function to instruct all processors 1 "which number processor is in which position in the entire parallel processor". This can be done by distributing the information, and before or after that, telling each processor 1 which processor it is. When the broadcast function is not provided, the relationship between the processor number and the position is defined in advance according to a certain rule, and each processor 1 is given information on its own processor number, and the position of the other processors is determined. It can be done by making it possible to specify.

If the above-mentioned method is used, both the creation of the transfer route determination table and the setting of the parameters required for the creation can be performed in a time proportional to the number of processors, and the square of the number of processors in the related art is used. It is possible to reduce the time required for setting as compared with the setting method which requires time and effort proportional to.

[0012]

As described above, according to the present invention, the setting of the message packet transfer route determination table held by each processor is created by the front-end processor or the master processor and is sent to each processor. Instead of sending only the parameters necessary for creating the table to each processor, each processor creates its own table, which has the effect of reducing the time required for setting. is there.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an example of a parallel processor device to which the present invention is applied.

FIG. 2 is a diagram showing a flow of processing when the present invention is used.

FIG. 3 is a diagram showing a state of a processor at the time of performing two processes in FIG.

FIG. 4 is a diagram for explaining a method of referring to a transfer route determination table when a packet is received.

FIG. 5 is a diagram showing a flow of processing in a conventional technique.

FIG. 6 is a diagram showing a state of the processor at the time of performing two processes in FIG.

[Explanation of symbols]

 1 processor 2 processor group connected in a two-dimensional grid 3 front-end processor

Claims (1)

[Claims] 1. In a parallel processor device having information for determining a message packet transfer route of a parallel processor as a rewritable table in each processor, a parameter necessary for setting the table is set for each processor. A parallel computer message packet transfer routing table setting method characterized by allowing each processor to set the internal table.