JPH0546501A - Serial interface system - Google Patents

Abstract

PURPOSE:To protect a serial interface system where the data are synchronously transferred between the host and slave devices from the malfunctions caused by the clock abnormality by performing a canceling operation at the side of the slave device after detecting the abnormality of the clock signal. CONSTITUTION:If an abnormal pulse produced by the noise of a serial synchronizing clock is detected at an abnormal pulse detecting part 6 of a slave device 3, the count value of an octal counter 7 that should originally be equal to '0' is erroneously set at '1' in regard of the data train interval. Under such conditions, an overflow signal is outputted from an interval counter 8 because the time when the next clock is inputted is delayed as long as the period of 'H' is previously counted by the counter 8. The count value of the counter 7 is cleared with output of the overflow signal. Then the influence of the abnormal pulse is eliminated between the data trains and the occurrence of malfunctions can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface system, and more particularly to a serial interface system used between a host device and a slave device.

[0002]

2. Description of the Related Art In a conventional serial interface method used between a host device and a slave device, data transmission and reception between the host device and the slave device are synchronized with a clock signal from the host device and a fixed number of data is transferred. (For example, 8 bits) are periodically transmitted and received.

However, if an unnecessary pulse signal is generated in the clock signal due to noise or the like, data may be garbled,
The counter that counts clock signals goes crazy. In particular, if the counter that counts the clock signal goes wrong, the timing at which the data is sent and received will go wrong, and unless the counter is immediately returned, the operation of the entire system will fall into an abnormal state and cannot be restored.

As a conventional device for avoiding such an abnormal situation in the serial interface system, for example, there is an abnormality detecting device for a serial transfer system described in Japanese Patent Laid-Open No. 62-187951. In this device, when the interval between the serial data string and the data string becomes longer than the permissible interval, an anomaly detecting means is provided to detect an anomaly and notify the anomaly. The abnormal connection system of the transfer connection system can be recognized immediately and accurately.

[0005]

However, in such a conventional abnormality detecting device for a serial transfer system, a counter for counting clock signals can be operated normally only by performing abnormality detection and notifying the abnormality. Since the system has not been restored yet, malfunctions of the system cannot be avoided, and there is a problem in that the system must wait for the operator's restoration process.

Therefore, the present invention provides a serial interface method in which an abnormality of a clock signal is detected on the slave device side to perform a clear operation of received data and a cancel operation of a clock signal to protect the system from a malfunction due to a clock abnormality. The purpose is to

[0007]

The invention according to claim 1 is
In a serial interface method in which a fixed number of bits of data is periodically transmitted and received between a host device and a slave device in synchronization with a clock signal from the host device at a constant interval, the number of bits of data received by the slave device. Is provided, and a second counting means for counting the signal interval of the clock signal is provided, and when the interval of the clock signal counted by the second counting means exceeds a certain interval, The invention according to claim 2 is characterized in that the number of bits counted by the first counting means is cleared.
When the interval of the clock signals counted by the counting means becomes equal to or less than a certain interval, a gate for interrupting the input of the clock signal is provided to cancel the clock signal.

[0008]

According to the first aspect of the present invention, in the serial interface system for transmitting and receiving a fixed number of bits of data periodically between the host device and the slave device in synchronization with a clock signal at a constant interval from the host device, The slave device is provided with a first counting means for counting the number of bits of the received data and a second counting means for counting the signal interval of the clock signal, and the interval of the clock signal counted by the second counting means is When the fixed interval is exceeded, the number of bits counted by the first counting means is cleared, and in the invention according to claim 2, the interval of the clock signal counted by the second counting means becomes equal to or smaller than the fixed interval. At this time, the clock signal is canceled by the gate.

Therefore, the slave device can clear and reset the abnormal pulse generated in the clock signal output from the host device, and can cancel the abnormal pulse to prevent malfunction of the system. ..

[0010]

EXAMPLES The present invention will be specifically described below based on examples. 1 to 7 are diagrams showing an embodiment of a basic system to which the serial interface method according to claims 1 and 2 is applied. FIG. 1 is a block diagram of the basic system 1. The basic system 1 is composed of a host device 2 and a slave device 3, and a serial synchronization clock and serial output data are output from the host device 2 to the slave device 3. From the slave device 3 to the host device 2,
Serial input data is being output. A timing chart of these signals is shown in FIG. 2. In this embodiment, 8-bit data is transmitted / received in synchronization with the serial synchronization clock. In the serial synchronization clock of FIG. 2A, it is shown that abnormal pulses A and B due to noise have occurred, and when normal, no abnormal pulse occurs.

FIG. 3 is a circuit configuration diagram of the abnormal pulse detector 6 provided in the slave device 3. The abnormal pulse detector 6 includes an octal counter 7, interval counters 8 and 9, a NAND gate 10 and an inverter 11. It consists of The octal counter (first counting means) 7 counts 8-bit data by the serial synchronization clock input from the host device 2 via the NAND gate 10.

Interval counters (second counting means) 8, 9
Counts the interval of the serial synchronization clock by the high-speed counter clock, and the interval counter 8 sends an overflow signal via the inverter 11 to the octal counter 7 when the interval of the serial synchronization clock becomes longer than a certain interval due to the abnormal pulse. It is output to the clear terminal of and the count value of the octal counter 7 is cleared. The interval counter 9 outputs a clock gate signal to the NAND gate 10 and cancels the serial synchronization clock output from the NAND gate 10 when the interval of the serial synchronization clock becomes shorter than a certain interval due to the abnormal pulse.

Next, the operation will be described. First, the data number counting process when an abnormal pulse occurs according to the first aspect of the invention will be described with reference to the timing charts of the signals shown in FIGS. FIG. 4 is a timing chart showing the relationship between the serial synchronization counter, the interval counter 8 and the overflow signal in the normal state.

In FIG. 4, when the serial synchronization clock ((a) in the figure) is normal, the interval counter 8 counts the serial synchronization clock at a constant interval (8 counts).
((B) in the figure), the overflow signal is also maintained in the "L" state ((c) in the figure.
As shown in (a), assuming that an abnormal pulse A due to noise occurs in the serial synchronization clock, the data string interval is octal when it should originally be "0", as shown in FIG. 5 (d). The count value of the counter 7 becomes "1". If no measures are taken here, the subsequent data will be processed in 1-bit units. Therefore, the interval counter 8 sets "H" after clearing the "L" period.
The period is counted (Fig. 5 (b)), and when it is normal, the next clock is input and restarted before the overflow, which causes no problem, but since the abnormal pulse A occurs, the next clock is generated. The time until the input of is prolonged, and the overflow signal is output from the interval counter 8 (FIG. 5 (c)). When the overflow signal is output,
The count value of the octal counter 7 is cleared, the influence of the abnormal pulse between the data strings is canceled, and the occurrence of malfunction is prevented in advance.

FIG. 6 is a timing chart showing the relationship between the serial synchronous clock, the interval counter 9 and the gate clock signal at the normal time. In FIG. 6, when the serial synchronization clock ((a) in the figure) is normal, the interval counter 9 counts the interval of the serial synchronization clock by a constant count number (8 counts) ((b) in the figure), and the gate The clock signal is also output in synchronization with the serial synchronization clock ((c) in the figure).

However, as shown in FIG. 2A, if an abnormal pulse B due to noise occurs in the data train in the serial synchronization clock, as shown in FIG. 7A,
Although the data string interval becomes shorter, the interval counter 9 clears the “L” period of the serial synchronization clock and then counts the “H” period ((b) in the figure), and the clock gate signal output from the interval counter 9 ((C) in the figure) and a certain value (n:
The serial synchronous clock is canceled until n <“H” period). That is, the internal operation is not affected by the abnormal pulse generated up to the count value n, and the occurrence of malfunction is prevented in advance.

Therefore, the abnormal pulse generated in the clock signal output from the host device can be cleared and reset by the slave device, and at the same time, it can be canceled and the malfunction of the system can be prevented. ..

[0018]

According to the first aspect of the present invention, a serial device that periodically sends and receives a fixed number of bits of data between a host device and a slave device in synchronization with a clock signal from the host device at fixed intervals. In the interface method,
The slave device is provided with first counting means for counting the number of bits of the received data and second counting means for counting the signal interval of the clock signal, and the interval of the clock signal counted by the second counting means is constant. When the interval is exceeded, the number of bits counted by the first counting means is cleared, and according to the invention of claim 2, the interval of the clock signal counted by the second counting means becomes equal to or less than a certain interval. At this time, since the clock signal is canceled by the gate, the slave device can clear and reset the abnormal pulse generated in the clock signal output from the host device, and at the same time, it can be canceled. It is possible to prevent malfunction.

[Brief description of drawings]

FIG. 1 is a block diagram of a basic system to which a serial interface method according to the present invention is applied.

FIG. 2 is a timing chart of various signals transmitted and received between the host device and the slave device of FIG.

FIG. 3 is a circuit configuration diagram of an abnormal pulse detector in the slave device of FIG.

FIG. 4 is a timing chart when the serial synchronization clock input to the abnormal pulse detection unit of FIG. 3, the count value of the interval counter 8 and the overflow signal output are normal.

5 is a timing chart of a count value and an overflow signal output from the interval counter 8 when an abnormal pulse occurs in the serial synchronization clock input to the abnormal pulse detector of FIG.

FIG. 6 is a timing chart when the serial synchronization clock input to the abnormal pulse detection unit of FIG. 3, the count value of the interval counter 9 and the output clock gate signal are normal.

7 is a timing chart of a count value and an output clock gate signal in the interval counter 9 when an abnormal pulse is generated in the serial synchronization clock input to the abnormal pulse detector of FIG.

[Explanation of symbols]

 1 basic system 2 host device 3 slave device 6 abnormal pulse detector 7 octal counter 8, 9 interval counter 10 NAND gate 11 inverter

Claims (2)

[Claims] 1. A serial interface method for periodically transmitting and receiving a fixed number of bits of data between a host device and a slave device in synchronization with a clock signal from the host device at regular intervals, wherein the slave device receives data. A first counting means for counting the number of bits of the generated data and a second counting means for counting the signal interval of the clock signal are provided, and the interval of the clock signal counted by the second counting means is constant. The serial interface method is characterized in that the number of bits counted by the first counting means is cleared when the number exceeds. 2. The gate according to claim 1, wherein the slave device has a gate for interrupting the input of the clock signal when the interval of the clock signal counted by the second counting means becomes a predetermined interval or less. Is provided to cancel the clock signal.