JPH0546483A - Virtual address conversion system - Google Patents

Abstract

PURPOSE:To manage the limited memory resource with proper page size and to realize good memory access protection. CONSTITUTION:Page size information (PGS) (g) and (l) is registered in each entry of TLBs 17 and 18. Based on the page size information (PGS) (g) and (l), the page size allocated for each page is shown. At the address conversion from the virtual address to the real address, the page size information (PGS) (g) and (l) is read out from the TLBs 17 and 18, whether or not an offset address (RAD)c of the conversion objective virtual address is included in the size shown by the page size information (PGS) (g) and (l) is checked. In the case the offset address (RAD)c exceeds the page size, an error is detected and the value of the converted real address is judged to be invalid.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual address conversion method for converting a virtual address into a real address by a paging method on a computer system, and more particularly to a virtual address conversion method suitable for a high-speed real-time system requiring high reliability. ..

[0002]

2. Description of the Related Art Generally, in a computer system, a virtual address space larger than the real address space of the main memory is realized so that a program can be created without being aware of the upper limit of the real memory capacity on the main memory. A virtual memory method is used. However, in the virtual memory system, since the data must be replaced between the main memory and the secondary memory when the task to be executed is switched, the task switching becomes a relatively large overhead. For this reason, the virtual memory system has heretofore been scarcely adopted, especially in a real-time system that requires high-speed operation.

However, for a real-time system that requires not only high speed but also high reliability, it is sufficiently significant to adopt the virtual memory system. This is because the virtual memory system can easily support memory access protection between the kernel and each task by hardware.

There are various methods for virtual memory, but in order to perform efficient task switching that is sufficiently applicable to the execution of high-speed real-time processing, the paging method is used.
In addition, the address translation table buffer (TL
A virtual memory system with B) is preferred. This is because the paging-based virtual memory system using TLB is
Since the address translation is relatively simple, you can expect high speed,
This is also advantageous in terms of cost.

When such a virtual memory system is used in a real-time system, unlike a normal virtual memory system, basically, in order to eliminate the overhead of swap-out and swap-in page replacement, all codes and data are eliminated. Must be resident in the main memory. Further, it is desirable to prevent the occurrence of TLB mishits.

That is, in the real-time system, the virtual memory system is used as a memory access protection mechanism for the main memory, rather than realizing a virtual address space larger than the real address space.

However, in the conventional paging system, the page size of each page is fixed, and even if the page size can be varied, it is only necessary to uniformly select a common page size for all pages. Therefore, in such a fixed-size paging method, it is difficult to map all the codes and data on the main memory having a limited storage capacity and appropriately protect them.

Generally, when the page size is reduced, the main memory can be properly managed, but since the number of pages increases,
Not all ELITORI fit into TLB, so TL
B's miss hits will occur frequently. On the contrary, if the page size is increased, the number of entries can be reduced, but this time, a wasteful area is likely to occur in the page and the main memory cannot be effectively used.

On the other hand, in the segment system in which the variable length size can be used, the address conversion becomes complicated and the cost cannot be paid for. Also, the memory allocation process is complicated.

Therefore, a paging method for allocating an arbitrary page size for each page is required. However, when an arbitrary page size is allocated in this way, the in-page offset address has a variable length. Therefore, simply adding the actual page address registered in the TLB and the in-page offset address as in the conventional case. In the address translation method of generating a real address, the value of the translated real address may exceed the page size of the page specified by the virtual page address.

In this case, the next page is mistakenly accessed instead of the page originally to be accessed on the main memory, and sufficient memory access protection cannot be realized.

[0012]

In the past, it was difficult to apply limited memory resources effectively, and it was difficult to apply them to a system that requires high speed and high reliability.

The present invention has been made in view of the above circumstances, and when the page size is set for each page, main memory access exceeding the page size can be prohibited, and the limited memory resources can be appropriately used. It is an object of the present invention to provide a virtual address translation method that can be managed with various page sizes and can realize sufficient memory access protection.

[0014]

Means and Actions for Solving the Problems
In a virtual address translation method that translates a virtual address consisting of a virtual page address and an offset address into a real address by the paging method, it has multiple elites provided for each page, and each entry has a virtual page address and a real page address. And an address translation table in which page size information indicating the page size of the page is registered, and a real page address corresponding to the virtual page address of the virtual address to be translated by referring to the address translation table. Means for generating the real address by adding the offset address to the real page address, and the page size information corresponding to the virtual page address of the virtual address to be translated by referring to the address translation table, Indicated by page size information And means for determining whether the validity of the real address depending on whether include offset address of the virtual address of the conversion target in size,
The page size is set for each page, and main memory access exceeding the page size is prohibited.

In this virtual address translation method, page size information is registered in each entry of the address translation table, and the page size assigned to each page is indicated by this page size information. At the time of address translation from virtual address to real address, the page size information is read from the address translation table, and it is checked whether the offset address of the translation target virtual address is included in the size indicated by the page size information. Be done. If the offset address exceeds the page size, an error is detected and the converted real address value is judged to be invalid. Therefore, by assigning the page size to each page in advance, the address conversion by paging of an arbitrary page size can be normally executed. Therefore, it is possible to manage the limited memory resource with an appropriate page size.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration for realizing a virtual address conversion system according to an embodiment of the present invention. This system is a paging type address translation system that performs address translation using a 2-way set associative TLB. Here, the virtual address is 32 bits, the size of each TLB entry is 64 bits, and the page size is 256, 512, 1K, 2
It shows a configuration in which an arbitrary size among K, 4K, and 8K bytes is set for each page.

This system has a virtual address register 1
1, current task register (TID) 12, page size error detector 13, selector 14, merge circuit 1
5, error control unit 16, address translation table buffer (TLB) 17 of set “0”, address translation table buffer (TLB) 18 of set “1”, comparators 19, 20, 21, 22 and AND gate array 23, 5
It is composed of an input OR gate 24 and a decoder 25.

In the virtual address register 11, a 32-bit virtual address consisting of a 19-bit virtual page address and a 13-bit in-page offset address is set. The 19-bit virtual page address is a 14-bit virtual tag (VSN) a and a 5-bit TLB.
Select (VPG) b.

The TLB 17 of the set "0" is a buffer memory addressed by a 5-bit TLB select (VPG) b, and is a TLB select (VPG).
It has a plurality of entries designated by b. Each entry has 8-bit task ID information (TID) e
, A 14-bit virtual address tag (VSN) f, and 3
The page size information (PGS) g of bits, the real page address (PAD) h of 24 bits, and the memory access control bit information (PRO) i of 15 bits are registered.

The TLB 18 of the set "1" is the TLB 17
Is a buffer memory addressed by a 5-bit TLB select (VPG) b.
It has a plurality of entries designated by B select (VPG) b. Each entry has 8-bit task ID information (TID) j, 14-bit virtual address tag (VSN) k, and 3-bit page size information (PG
S) l and 24-bit real page address (PAD) m
And 15-bit memory access control bit information (PR
O) n are registered.

Here, 3-bit page size information (P
GS) g and l are each 8K bytes, 4K bytes, 2K
One of six page sizes of 1 byte, 512 bytes, and 256 bytes is shown.
That is, the page size is set for each page, and the set page size can be recognized by the page size information (PGS). Also,
The correspondence between the contents of the TLBs 17 and 18 and the real address space on the main memory is, for example, as shown in FIG.

As shown in FIG. 2, all codes and data of jobs 1 to n necessary for executing data processing of the real-time system are stored in the main memory, and the page size for each page is stored. Has been assigned. Here, the page size of the first page P-1 of job 1 is 2 Kbytes, the page size of the second page P-2 is 4 Kbytes, the page size of the third page P-3 is 8 Kbytes,
Then, it is assumed that the page size of the 2n-th page is 2 Kbytes.

In this case, information corresponding to all pages of the job to be executed (current task), eg, job 1, is registered in the TLBs 17 and 18, for example, the first
In the first entry of the TLB 17 corresponding to the page P-1, the virtual page address of the first page P-1, the real page address, and information indicating the page size (2 Kbytes) are registered. In the first entry of the TLB 18 corresponding to page P-2, the virtual page address of the second page P-2, the real page address, and information indicating the page size (4 bytes) are registered.

The selector 14 of FIG. 1 has the page size information (PGS) g and the real page address (PAD) h read from the TLB 17, and the page size information (PGS) 1 and the real page address read from the TLB 18. (PA
D) m is input, and page size information (PGS) and real page address (PAD) from one of the TLBs are selected.

The selection operation by the selector 14 is performed by the controller 16 based on the comparison result by the comparisons 19 to 22.
Controlled by. That is, the current task ID information (TID) e, j and the virtual address tags (VSN) f, k of both the TLBs 17 and 18 are compared with the comparators 19 and 21,
And 20, 22, depending on the current task register 1
Current task ID information (TID) set to 2
d and the virtual address tag (VSN) a set in the virtual address register 11 are respectively compared, and the matching current task ID information (TID) and virtual address tag (VSN) are selected by the selector 14.

The page size error detector 13 has page size information (PGS) selected by the selector 14.
It is checked whether or not the in-page offset address (RAD) c belongs to the size indicated by O, and an error output r is generated when the offset address (RAD) c exceeds the page size. It is composed of a gate array 23, an OR gate 24, and a decoder 25.

The decoder 25 uses the page size information (PG
S) 5-bit mask data for page size over detection is generated according to the page size designated by O.
An example of this 5-bit mask data is shown in FIG.

As shown in FIG. 3, the mask data is "11111" when the page size is 256 bytes.
And when the page size is 512 bytes, "1111"
When the page size is 1 Kbyte, it becomes "111".
00 "and" 11 "when the page size is 2 Kbytes
000 "and" 1 "when the page size is 4 Kbytes
0000 ", and" 0000 "when the page size is 8 Kbytes.

The AND gate array 23 includes a decoder 25.
The 5-bit mask data v and the upper 5-bit data u of the in-page offset address c are input, and the corresponding bits are ANDed to generate a 5-bit AND output x. This logical product output x is obtained by masking the upper 5-bit data u of the in-page offset address c with the mask data v corresponding to the page size, and when the in-page offset address c exceeds the specified page size. , Any one of the 5 bits of the logical product output x becomes "1". The OR gate 24 inputs 5 bits of the logical product output x and generates a logical sum of these 5 bits as a page size error output r. In this case, the page size error output r of "1" indicates that a page size error has occurred.

The merge circuit 15 adds a 13-bit in-page offset address c to the 24-bit real page address p selected by the selector 14 to generate a 32-bit real address q. In this case, the in-page offset address c is the 24-bit real page address p.
Is added to the low-order bit side in a state of overlapping with the low-order bit of.

The error control unit 16 is for detecting the occurrence of an error at the time of address translation, and in order to protect the memory access to the main memory, the real page is based on the memory access control bit information (PRO) i, n. It is determined whether the addresses (PAD) h and m are valid / invalid and whether read / write is permitted / prohibited.

Further, the error control unit 16 inputs the page size error output r from the page size error detector 13, and when it is "1", it recognizes that the real address q is invalid. In order to prohibit memory access,
A memory access protection error output t is generated.

Further, when the error control unit 16 detects a mishit in the TLBs 17 and 18 based on the comparison result of the comparators 19 to 22, it outputs a TLB miss output s to instruct the contents update of the TLBs 17 and 18.
Next, the address translation operation of the system of FIG. 1 will be described.

First, the TLB of the virtual address register 11
The entries of TLBs 17 and 18 are selected together by the select information b. The virtual tags (VSN) f and k in the designated entry are read from the TLBs 17 and 18, and are compared with the virtual tags (VSN) a of the virtual address register 11 by the comparators 20 and 22, respectively.

The current task ID information (TID) e, j in the designated entry is the TLB 17,18.
Read from the current task ID information (TI) of the current register 12 by the comparators 19 and 21, respectively.
D) Compared with d.

Of the TLBs 17 and 18, the virtual tag (VSN) a and the current task ID information (T
The entry having the virtual tag and the current task ID information that respectively match both ID) d is selected, and the selector 14 selects the real page address (PAD) and page size information (PGS) corresponding to the entry of the selected TLB. ) Are output as outputs p and o, respectively.

Then, the page size error detector 13 generates 5-bit mask data v corresponding to the page size information o, and the mask data v is ANDed bit by bit with the upper 5 bits u of the in-page offset address c.
Is taken, and the presence or absence of a page size error is detected by ORing the 5-bit AND output.

When a page size error occurs,
The error control unit 16 recognizes that the real address q is invalid and generates a memory access protection error output t in order to prohibit main memory access. Further, even if the page size error does not occur, if the memory access control bit information (PRO) is not valid, the error control unit 16 similarly generates the memory access protection error output t.

As described above, in this embodiment, T
In each entry of LBs 17 and 18, page size information (P
GS) g, l is registered, and the page size assigned to each page is indicated by this page size information (PGS) g, l. When translating an address from a virtual address to a real address, the page size information (PG
S) g, l is read from the TLBs 17,18, and within the size indicated by the page size information (PGS) g, l, the offset address (RA
D) It is checked whether c is included. When the offset address (RAD) c exceeds the page size, an error is detected and it is determined that the converted real address value is invalid. Therefore, by assigning a page size to each page in advance, address translation by paging of an arbitrary page size can be normally executed. Therefore, it becomes possible to manage the limited memory resources with an appropriate page size, which is particularly suitable for a real-time system that requires high speed and high reliability.

[0041]

As described above, according to the present invention, when the page size is set for each page, the main memory access exceeding the page size can be prohibited, and the limited memory resource can be used for the appropriate page. It can be managed by size, and sufficient memory access protection can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration for realizing a virtual address conversion system according to an embodiment of the present invention.

FIG. 2 is a TL in the virtual address translation system of the same embodiment.
The figure which shows the correspondence of the content of B and the real address space on a main memory.

FIG. 3 is a view showing a mask data pattern for detecting a page size error used in the virtual address conversion system of the embodiment.

[Explanation of symbols]

11 ... Virtual address register, 13 ... Page size error detector, 17, 18 ... TLB, g, l ... Page size information.

Claims (1)

[Claims] 1. In a virtual address translation method for translating a virtual address composed of a virtual page address and an offset address into a real address by a paging method, a virtual page is provided in each entry, and each entry has a virtual page. Information indicating the correspondence between the address and the real page address, and the address conversion table in which the page size information indicating the page size of the page is registered, and referring to the address conversion table, the virtual page address of the virtual address to be converted is set. Means for obtaining a corresponding real page address, adding the offset address to the real page address to generate a real address, and referring to the address translation table, the page size corresponding to the virtual page address of the virtual address to be translated Seeking information, this page size And a means for determining whether or not the real address is valid depending on whether or not the offset address of the virtual address to be translated is included in the size indicated by the information, and the page size is set for each page, A virtual address translation method that prohibits access exceeding the page size.