JPH0546381A - Data processor - Google Patents

Abstract

PURPOSE:To simplify the interface of a function block connected to an internal bus by simplifying an instruction issued by a CPU for the purpose of an arithmetic processing containing an immediate operation, and also, decreasing the number of wirings of the internal bus for a data transfer. CONSTITUTION:A first holding register 1 for holding data on a first internal bus 101 is connected directly to an ALU, and on the other hand, between a second holding register 2 for holding data on a second internal bus 102, and the ALU 4, an immediate generating circuit 3 to which a control command 5 is given from a CPU 6 is interposed. The immediate generating circuit 3 gives one of immediate data generated by itself and the data held by a second holding register 2 to the ALU 4 in accordance with the control command 105. Operation result data outputted from the ALU 4 is outputted to a second internal bus 102 through a third holding register 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for executing arithmetic processing including immediate value arithmetic.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional data processing device. In the figure, 1 is a first holding register for holding data on the first internal bus 101, and 2 is a second holding register for holding data on the second internal bus 102. is there. 4 is the first
The data held by the holding register 1 and the data held by the second holding register 2 are used as two input data to execute an arithmetic operation or a logical operation between the two input data, An arithmetic unit (hereinafter referred to as ALU) that outputs the result as arithmetic result data. 5 is ALU
4 is a third holding register for holding the operation result data output from the No. 4 and outputting the held operation result data to the third internal bus 103. Reference numeral 6 denotes a central processing unit (hereinafter referred to as CPU), which is the second internal bus 102.
While being connected to the ALU 4, the ALU 4 is provided with a calculation command 106. Reference numerals 7 and 8 denote first to third internal buses 1 respectively.
The first and second functional blocks are connected to any of 01, 102, and 103.

The operation of the conventional data processing apparatus configured as described above will be described below.

First, the operation of executing an operation between the data of the first function block 7 and the data of the second function block 8 and writing the operation result data to the second function block 8 will be described. .. When the CPU 6 issues an instruction for this arithmetic operation, the first functional block 7 is first connected to the first internal bus 101, and
The second functional block 8 has the second and third internal buses 10.
2, 103 are connected. Then, one data from the first functional block 7 is stored in the first holding register 1 through the first internal bus 101, and the second functional block 8 is stored.
From the other data through the second internal bus 102 to the second
Are stored in the holding register 2. After this, ALU4
The data held by the first holding register 1 and the data held by the second holding register 2 are used as two input data, and the data between the two input data is output in accordance with the operation command 106 given from the CPU 6. The calculation is executed and the result of the calculation is output as calculation result data. This operation result data is stored in the third holding register 5 and written from the third holding register 5 to the second functional block 8 through the third internal bus 103.

Next, an immediate value operation for executing an operation between the data of the first functional block 7 and the immediate data (immediate data) and writing the operation result data in the second functional block 8 will be described. .. When the CPU 6 issues an instruction instructing this immediate value operation, first the first
The functional block 7 of is connected to the first internal bus 101,
The second functional block 8 is connected to the third internal bus 103, and the CPU 6 is connected to the second internal bus 102. Then, one data from the first functional block 7 is stored in the first holding register 1 through the first internal bus 101, and immediate data is stored in the second holding register 2 through the second internal bus 102 from the CPU 6. To be done.
After that, the ALU 4 sets the data held by the first holding register 1 and the data held by the second holding register 2 as two input data in accordance with the operation command 106 given from the CPU 6 An operation is performed between two input data, and the result of the operation is output as operation result data. This operation result data is stored in the third holding register 5 and written from the third holding register 5 to the second functional block 8 through the third internal bus 103.

[0006]

As described above, in the conventional data processing device, the CPU 6 has the first to third functional blocks 7, the CPU 6 itself and the second functional block 8 in the immediate value operation. Internal buses 101, 10
It was necessary to issue a command for connecting to each of 2, 103. Therefore, there is a problem in that the source and destination of the instruction issued by the CPU 6 become complicated.

Further, since one set of internal buses (second internal bus 102) is used to give immediate data to the ALU 4, a total of three sets of internal buses (first to third internal buses 101, 101, 102, 103) had to be provided. Therefore, there is a problem that the number of wires of the internal bus for data transfer increases and the interface between the internal bus and each of the functional blocks 7 and 8 becomes complicated.

It is an object of the present invention to simplify a command issued by a CPU for arithmetic processing including an immediate operation, reduce the number of wires of an internal bus for data transfer, and connect the functional block to the internal bus. Is to simplify the interface of.

[0009]

In order to achieve the above object, the present invention is a data processing device having a CPU and first and second internal buses, which holds data on the first internal bus. While the first holding register for holding the data is directly connected to the ALU, an immediate value generation circuit controlled by the CPU is provided between the second holding register for holding the data on the second internal bus and the ALU. By interposing, the immediate value generation circuit adopts a configuration in which either the immediate value data generated by itself under the control of the CPU or the data held by the second holding register is applied to the ALU. The immediate data is given to the ALU without going through the internal bus.

More specifically, according to the present invention, a first holding register for holding data on a first internal bus and a second holding register for holding data on a second internal bus. When a control command is given from a register and a CPU and the control command is a command for instructing generation of immediate data, the immediate data is generated and the generated immediate data is output, and the control command instructs generation of immediate data. If it is not a command to do so, the immediate value generation circuit that directly outputs the data that is held by the second holding register, and the data that is held by the first holding register and the data that is output from the immediate value generation circuit are input as two inputs. An ALU that executes an operation between the two input data in accordance with an operation command given from the CPU as data and outputs the result of the operation as operation result data;
A third holding register for holding the operation result data output from U and outputting the held operation result data to the second internal bus is adopted.

[0011]

According to the present invention, the arithmetic operation for executing an operation between the data on the first internal bus and the data on the second internal bus and outputting the operation result data to the second internal bus is , Proceed as follows. First, the data on the first internal bus is stored in the first holding register, and the data on the second internal bus is stored in the second holding register. A control command, which is not a command for instructing generation of immediate data, is given to the immediate value generation circuit, and the immediate value generation circuit outputs the data held in the second holding register to the ALU as it is. After that, the ALU is supplied from the CPU with the data held in the first holding register and the data output from the immediate value generation circuit, that is, the data held in the second holding register, as two input data. The calculation between the two input data is executed in accordance with the calculation command and the result of the calculation is output as calculation result data. This operation result data is stored in the third holding register,
The data is output from the third holding register onto the second internal bus.

On the other hand, the arithmetic operation for executing the arithmetic operation between the data on the first internal bus and the immediate data and outputting the arithmetic result data on the second internal bus proceeds as follows. First, the data on the first internal bus is stored in the first holding register. A control command for instructing generation of immediate data is given to the immediate value generation circuit, and the immediate value generation circuit generates immediate data according to the control command given from the CPU and outputs the generated immediate data. After that, the ALU takes the data held in the first holding register and the data output from the immediate value generation circuit, that is, the immediate value data as two input data, according to the operation command given from the CPU, and outputs the two input data. The calculation is performed and the result of the calculation is output as calculation result data.
The operation result data is stored in the third holding register and is output from the third holding register onto the second internal bus.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention. In the figure,
Reference numeral 1 is a first holding register for holding data on the first internal bus 101, and 2 is a second internal bus 102.
It is a second holding register for holding the above data. 3 is given a control command 105, and the control command 10
If 5 is a command for instructing generation of immediate data, it generates immediate data and outputs the generated immediate data, and if the control command 105 is not a command for generating immediate data, the second holding register 2 is an immediate value generation circuit that directly outputs the data held therein. 4 uses the data held in the first holding register 1 and the data output from the immediate value generation circuit 3 as two input data to execute an arithmetic operation or a logical operation between the two input data. It is an ALU that outputs the result of the operation as operation result data. Reference numeral 5 is a third holding register which holds the operation result data output from the ALU 4 and outputs the held operation result data to the second internal bus 102. 6 is C
It is a PU, and the control command 105 is sent to the immediate value generation circuit 3.
And the operation command 106 is given to the ALU 4. 7 and 8 are the first and second internal buses 1 respectively
The first and second functional blocks are connected to both 01 and 102.

The operation of the data processing apparatus according to this embodiment configured as described above will be described below.

First, the operation of executing the operation between the data of the first function block 7 and the data of the second function block 8 and writing the operation result data into the second function block 8 will be described. .. When the CPU 6 issues an instruction for this arithmetic operation, the first functional block 7 is first connected to the first internal bus 101, and
The second functional block 8 is connected to the second internal bus 102. Then, one data from the first functional block 7 is passed through the first internal bus 101 to the first holding register 1
And the other data from the second functional block 8 is stored in the second holding register 2 through the second internal bus 102. On the other hand, the immediate value generation circuit 3 receives a control command 105 which is not a command from the CPU 6 to generate immediate data
Is given, the immediate value generation circuit 3 outputs the data held in the second holding register 2 to the ALU 4 as it is. After that, the ALU 4 uses the data held in the first holding register 1 and the data output from the immediate value generation circuit 3, that is, the data held in the second holding register 2 as two input data, and the CPU 6 A calculation between the two input data is executed in accordance with the calculation command 106 given by the above, and the result of the calculation is output as calculation result data. This operation result data is stored in the third holding register 5 and written from the third holding register 5 to the second functional block 8 through the second internal bus 102.

Next, an immediate value operation for executing an operation between the data of the first functional block 7 and the immediate data and writing the operation result data in the second functional block 8 will be described. The CPU issues an instruction to instruct this immediate operation
6 is issued, the first functional block 7 is first connected to the first internal bus 101 and the second functional block 7 is issued.
The functional block 8 of is connected to the second internal bus 102. Then, one data from the first functional block 7 is stored in the first holding register 1 through the first internal bus 101. The CPU 6 gives a control command 105 to the immediate value generation circuit 3 to generate immediate data, and the immediate value generation circuit 3 generates immediate data according to the control command 105 and outputs the generated immediate data. After this, AL
U4 uses the data held in the first holding register 1 and the data output from the immediate value generation circuit 3, that is, the immediate data as two input data, according to the operation command 106 given from the CPU 6 to input the two input data. The calculation is performed and the result of the calculation is output as calculation result data. This operation result data is stored in the third holding register 5 and written from the third holding register 5 to the second functional block 8 through the second internal bus 102.

As described above, according to this embodiment, the immediate value generation circuit 3 controlled by the control command 105 is interposed between the second holding register 2 and the ALU 4, and in the case of the immediate value calculation operation, Since the immediate value generation circuit 3 generates immediate data, the CPU 6 does not need to give immediate data to the ALU 4 through the internal bus. Therefore, the number of internal buses is changed from the conventional three to two (first and second internal buses 10 and 10).
1, 102).

[0019]

As described above, according to the present invention, the immediate value generating circuit is interposed between the ALU and the second holding register for holding the data on the second internal bus, and the immediate value generating circuit is generated. Since the circuit adopts a configuration in which either the immediate data generated by itself under the control of the CPU or the data held by the second holding register is given to the ALU, the ALU does not go through the internal bus. Immediate data is given to. Therefore, the CPU only has to issue an instruction for connecting each of the two functional blocks to the first and second internal buses in the immediate value calculation operation.
The specification of the source and destination of the instruction issued by U is simplified. In addition, since the immediate data is given to the ALU without passing through the internal bus, it is not necessary to purposely provide three sets of internal buses for the immediate operation unlike the conventional case. That is, since it is sufficient to provide two sets of internal buses (first and second internal buses) as described above, the number of wires for the internal bus is reduced, and each functional block connected to the internal bus is reduced. The interface of is simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional data processing device.

[Explanation of symbols]

 1 1st holding register 2 2nd holding register 3 immediate value generation circuit 4 ALU (arithmetic unit) 5 3rd holding register 6 CPU (central processing unit) 7 1st functional block 8 2nd functional block 101 1st Internal bus 102 Second internal bus 103 Third internal bus 105 Control command 106 Calculation command

Claims (1)

[Claims] 1. A data processing device comprising a central processing unit and first and second internal buses, comprising: a first holding register for holding data on the first internal bus; A second holding register for holding data on the second internal bus, and a control command given from the central processing unit, and when the control command is a command for instructing generation of immediate data, immediate data is stored. An immediate value generation circuit that generates and outputs the generated immediate data, and outputs the data held in the second holding register as it is if the control command is not a command for instructing generation of immediate data; The data held in the first holding register and the data output from the immediate value generation circuit are used as two input data, and the two input data are input in accordance with the operation command given from the central processing unit. An arithmetic unit for executing an arithmetic operation between them and outputting the result of the arithmetic operation as arithmetic result data; an arithmetic operation result data output from the arithmetic operation unit; And a third holding register for outputting to the data processing device.