JPH0543559U - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Objective] To reduce the manufacturing cost by reducing the number of cream solder coating stages, shortening the overall assembly line, and reducing the cream solder coating device. [Composition] Through holes 5a, 7a, 11a, 11b for applying cream solder are provided in one of the overlapping portions of each member, and the through holes 5a, 7a, 11a, 11b are provided.
When cream solder is applied using a, 7a, 11a, and 11b and heated, the molten solder enters the gap of the polymerized portion by a capillary phenomenon, and both members are soldered and fixed. Therefore, it is not necessary to apply the cream solder to the entire surface of the member overlapping portion, and the entire assembly line is shortened. Moreover, the cream solder application device is reduced, the facility cost is reduced, and the manufacturing cost of the composite semiconductor device is reduced. Can be reduced.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor device for protecting a main circuit or another semiconductor element (hereinafter abbreviated as a protected element) from a surge voltage.

[0002]

[Prior Art]

 As shown in FIG. 4, this type of semiconductor device 1 is used by being connected in parallel with the protected element 2 in order to protect the protected element 2 from a surge voltage or the like. FIG. 5 shows an outline of the internal structure of the semiconductor device. In the figure, a semiconductor device 1 has a thyristor structure on the left side of the drawing, which is composed of a P1 layer 3, an N1 layer 4, a P2 layer 8 and an N2 layer 6 formed by a diffusion layer. The right side of the figure has a diode structure of N4 layer 7, N1 layer 4, and P2 layer 8 which are also formed of diffusion layers. Further, the N3 layer 5 immediately below the P2 layer 8 is formed to a depth of about 40 μm by an ion implantation method. Furthermore, an oxide film 9 is formed on one main surface so as to cover the junction between the N1 layer 4 and the P2 layer 8 and the N5 layer 10 formed as a channel stopper. An electrode metal is attached to the window opening of the oxide film 9 to form the main terminal T1, and an electrode metal is also attached to the other main surface to serve as the main terminal T2.

To manufacture the semiconductor device as described above, first, the N-type semiconductor substrate is thermally oxidized, and then the oxide film 9 in the portion where the thyristor portion on the left side of the drawing is formed is removed. Next, the N3 layer 5 is formed by diffusing the N-type impurities at a surface impurity concentration that achieves a desired breakdown voltage by an ion implantation method. After that, the P1 layer 3 and the P2 layer 8 are formed by diffusing P-type impurities into the semiconductor substrate by a selective diffusion method using a known technique. Similarly, N-type impurities are diffused in the P2 layer 8 and the N1 layer 4 to form the N2 layer 6, the N4 layer 7, and the N5 layer 10. Next, in order to form the main terminals T1 and T2, the oxide film 9 on one main surface side and the oxide film on the other main surface side (not shown) are removed, and a metal is deposited on a predetermined portion by vapor deposition. The metal on the oxide film is removed by etching, leaving only the metal to be the electrode portion, and the semiconductor device 1 as shown in FIG. 5 is completed.

Next, FIG. 3 shows a voltage-current waveform diagram during operation of the semiconductor device having the above configuration. In the figure, the right side shows a waveform when the main terminal T1 is a positive (+) potential and the main terminal T2 is a negative (-) potential, which shows that the diode has forward characteristics. The left side shows a waveform when the main terminal T1 has a negative (-) potential and the main terminal T2 has a positive (+) potential, which indicates that the thyristor has a turn-on characteristic. In the figure, the horizontal axis represents voltage and the vertical axis represents current, and the symbols are as follows. VBO ・ ・ ・ Breakover voltage VBR ・ ・ ・ Break voltage VT ・ ・ ・ ON voltage ΔV ・ ・ ・ VBO-VBR IBO ・ ・ ・ Breakover current IH ・ ・ ・ Holding current IT ・ ・ ・ ON current

[0005]

[Problems to be solved by the device]

 By the way, in the above-mentioned semiconductor device, it is difficult to form and control the N3 layers 5 by the ion implantation method, and the ion implantation device is also expensive, resulting in a high manufacturing cost. Further, there is a problem that the IBO increases only by the current component flowing through the N3 layer 5. That is, in FIG. 5, assuming that the hole currents flowing from the P1 layer 3 to the main terminal T1 are I1, I2, I3, I4 and I5, respectively, these hole currents I1, I2, I3, I4 and I5 are given. The sum of the two becomes the IBO in FIG. 3 (current up to VBO). When the surge voltage applied to the protected element exceeds its VBO, electrons are injected from the N2 layer 6, and the thyristor portion turns on as an electron current D, and the current becomes IT. Then, the voltage between the main terminals T1 and T2 drops to VT. Thus, the protected element connected in parallel to this semiconductor device is protected from the surge voltage. However, since the product of the voltage VBO and the current IBO at that time is generated in the semiconductor device as a power loss, the IBO is The smaller the better. Therefore, in order to function more effectively as a protection element, the loss of the element can be reduced, the IBO as an element that reduces heat generation is also small, and the protection function is maintained even when the on-current of the thyristor is small. Is required to be large and ΔV is to be small. However, in the past, there was a problem to be solved in that the IBO cannot be reduced because there are currents I5 and I3 that do not contribute to the turn-on of the thyristor section even when only the IBO is observed.

[0006]

[The purpose of the device]

 The present invention has been made in order to solve the above problems, and has a characteristic that it can be manufactured by a conventional diffusion method without using an ion implantation method and is regarded as a protective element. The object is to provide a semiconductor device with improved IBO, IH and the like.

[0007]

[Means for solving problems]

 In the semiconductor device of the present invention, the layers P1-N1-P2-N2 are sequentially stacked in the semiconductor substrate from one main surface side, and the joint portion between the P2 layer and the N2 layer is formed on the other main surface of the semiconductor substrate. In an exposed semiconductor device in which an N4 layer is formed adjacent to the P1 layer on one main surface side, one end portion of the electrode metal serving as the main terminal T1 in contact with the N2 layer is formed on the P2-N2 layer surface. The feature is that it is formed so as to be inside the pattern shape of the layer.

[0008]

[Action]

 In the semiconductor device of the present invention, the P2 layer-N2 interlayer surface is covered with an insulating film except for a part near the center of one main surface, and one end portion of the electrode metal serving as the main terminal T1 is in contact with the N2 layer. Since the hole currents I5 and I3 do not flow when formed so as to be inside the pattern shape of the layer, IBO is the sum of I1, I2, and I4, which is larger than IBO in the semiconductor device having the conventional structure. Can be made smaller.

[0009]

【Example】

 Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic structural view of a semiconductor device of the present invention, and FIG. 2 is a plan view thereof. In these figures, in order to manufacture the semiconductor device 1 having a desired breakdown voltage, first, the N-type semiconductor substrate having a predetermined specific resistance is thermally oxidized, and then the oxide film 9 in a predetermined portion is removed. P-type impurities are selectively diffused to form P-type guard ring 11. Next, similarly, the P-type impurity is diffused by the selective diffusion method to form the P2 layer 8 and the P1 layer 3. Therefore, the P-type guard ring 11 and the P2 layer 8 are integrated as a P layer. Then, the N-type impurity is diffused in the P2 layer 8 and the N1 layer 4 by using the selective diffusion method as in the conventional method to form the N2 layer 6, the N4 layer 7 and the N5 layer 10 as a channel stopper. Next, in order to form the main terminals T1 and T2, the oxide film 9 in a predetermined portion is removed. Then, after depositing the electrode metal on the entire surface, the deposited metal on the oxide film 9 is removed by etching. At this time, what is important is the dimension for removing the oxide film 9 in order to form the electrode metal serving as the main terminal T1.

That is, as shown in FIG. 1, the oxide film 9 does not extend over the P2 layer 8 beyond the left end portion on the N2 layer 6 as in the conventional structure of FIG. That is, the oxide film 9 is removed so as to be aligned with the left end portion or inside the N2 layer 6. As a result, at the left end in the figure, the vapor-deposited metal does not directly adhere to the P2 layer, and the main terminal T1 is not formed at this portion. With the above configuration, since the main terminal T1 is formed in the same region as the formation region of the N2 layer 6 or in the region surrounded by the insulating film 9 up to the inside thereof, the main terminal T1 flows from the P1 layer 3 through the P2 layer. The hole currents are only I1, I2, I4, and the hole currents I5, I3 flowing in the conventional structure disappear. Therefore, a potential difference occurs in the effective lateral resistance of the P2 layer 8, the junction between the P2 layer and the N1 layer 4 is forward-biased, and the hole current I2 increases due to the voltage increase, and the condition α1 + α2 = ≧ 1 is satisfied. When satisfied, an electron current D flows and breaks over. IBO is the sum of all currents flowing at this breakover.

On the other hand, as is well known, a semiconductor device having a low voltage uses a semiconductor substrate having a high impurity concentration for the N1 layer, so that the hole current I2 of the N1 layer 4 becomes large. Here, a technique for reducing the current of the N1 layer 4 as much as possible and reducing the radius of curvature of the portion of the guard ring 11 due to the impurity concentration difference in order to suppress the voltage will be considered. However, with this technique, the current in the portion of the guard ring 11 increases due to the surface impurity concentration. A semiconductor device having a function as a protection element according to the present invention is not actually operated as a protection element unless the difference between the VBR voltage and the VBO voltage shown in FIG. 3 is within a certain range indicated by ΔV. It causes various problems. Therefore, it is necessary to consider an optimum condition that determines how much the impurity concentration of the guard ring 11 portion should be within a certain voltage range to reduce IBO without increasing VBO.

In the present invention, when the conditions were changed so that the surface impurity concentration of the guard ring 11 portion was 2 × 10 18 to 8 × 10 18 / cubic centimeter, it was found that VBO In the range of 56 to 70 V, VBO did not increase and IBO was small in the range of 3 × 10 18 to 7 × 10 18 powers / cubic centimeter. This semiconductor device has a larger IH than the conventional semiconductor device of this type. Incidentally, comparing the IBO and IH in the semiconductor device of the present invention with those of the conventional structure, the IBO was 500 mA in the conventional structure and 450 mA in the structure of the present invention. Further, IH was 170 mA in the conventional structure, but was 400 mA in the structure of the present invention.

[0013]

[Effect of the device]

 As described above, according to the present invention, the P2 layer-N2 interlayer surface is covered with an insulating film except for a part near the center of one main surface, and is contacted with the N2 layer of the electrode metal serving as the main terminal T1. Since one end of the N2 layer is formed so as to be inside the pattern shape of the N2 layer, the following effects can be obtained. (1) The IBO becomes relatively smaller than that of the conventional product. (2) Since the surface impurity concentration of the guard ring portion is set within a predetermined range, IH becomes larger than that of the conventional product. (3) Since it can be manufactured by a normal diffusion method without using the ion implantation method, it is possible to provide a semiconductor device with low manufacturing cost and stable quality.

[Brief description of drawings]

FIG. 1 is a vertical sectional view showing a schematic structure of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a schematic structure of a semiconductor device of the present invention.

FIG. 3 is a waveform diagram showing electrical characteristics of the semiconductor device.

FIG. 4 is a block diagram showing a usage example of the semiconductor device.

FIG. 5 is a vertical sectional view showing a schematic structure of a conventional semiconductor device of this type.

[Explanation of symbols]

 1 semiconductor device 2 protected element 3 P1 layer 4 N1 layer 6 N2 layer 7 N4 layer 8 P2 layer 9 insulating film 10 N5 layer 11 P-type guard ring T1, T2 main terminal I1, I2, I4 hole current D electron current

Claims (2)

[Scope of utility model registration request] 1. P1-N1-P2-N2 in a semiconductor substrate
Layers are sequentially laminated from one main surface side, and the P2 layer and the N
In a semiconductor device in which a junction with two layers is exposed on the other main surface of the semiconductor substrate and an N4 layer is formed adjacent to the P1 layer on one main surface side, a main terminal is formed on the P2-N2 layer surface. T1
A semiconductor device, wherein one end of the electrode metal to be in contact with the N2 layer is formed so as to be inside the pattern shape of the N2 layer. 2. The outer peripheral portion of the P2 layer constitutes a P-type guard ring, and the surface impurity concentration of the guard ring portion is 3
2. The semiconductor device according to claim 1, wherein the number is set to x10 18 to 7x10 18 / cubic centimeter.