JP4423855B2

JP4423855B2 - Composite semiconductor device and method for manufacturing the same

Info

Publication number: JP4423855B2
Application number: JP2002381887A
Authority: JP
Inventors: 公昭小杉; 哲也高橋
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2002-12-27
Filing date: 2002-12-27
Publication date: 2010-03-03
Anticipated expiration: 2022-12-27
Also published as: JP2004214397A

Description

【０００１】
【発明の属する技術分野】
本発明は、複合型半導体素子およびその製造方法に関する。
【０００２】
【従来の技術】
半導体素子の一種であるサイリスタは、電源回路等に用いられる。サイリスタには、その特性の向上を図るために、通常のｐｎｐｎ４層構造に、ｐｎ接合ダイオードの構造が複合化されたものがある（例えば、特許文献１参照）。以下では、サイリスタにダイオードが複合化されたものを、複合型半導体素子と呼ぶ。
【０００３】
【特許文献１】
特開平４−３４０２７６
【０００４】
従来のこの種の複合型半導体素子は、一般的には、サイリスタを構成するｐ１領域、ｐ１領域に接続されたｎ１領域、ｎ１領域に接続されたｐ２領域、ｐ２領域に接続されたｎ２領域に加えて、ｎ１領域とｐ２領域とに接続され、ｐ２領域とともにダイオードを構成するｎ型の半導体領域を持っている。サイリスタはさらに、ｐ１領域に接続されたアノード電極と、ｐ２領域、ｎ２領域に接続されたカソード電極とを備えている。
ダイオードはアノード、カソード電極間に所定の値以上の電圧が印加されることにより降伏し、サイリスタはダイオードの降伏により流れる逆方向電流を用いてターンオンする。
【０００５】
【発明が解決しようとする課題】
このような構成では、サイリスタがターンオンする電圧（トリガ電圧）を所望の値に設定するには、ｎ型の半導体領域またはｐ２領域の不純物濃度を変える必要がある。
一般的に、不純物濃度が高いほどトリガ電圧を所望の値に設定しやすい（製造する複合型半導体素子ごとのトリガ電圧の差が許容範囲内に収まりやすい、すなわち個体差が小さい）。また、不純物濃度が低いほどトリガ電圧を所望の値に設定しにくい（複合型半導体素子ごとのトリガ電圧の差が許容範囲を超える、すなわち個体差が大きい）。トリガ電圧の設定が２５０Ｖ未満では、トリガ電圧のばらつきが許容範囲内で収まりやすいが、２５０Ｖ以上になると、トリガ電圧のばらつきが許容範囲を超えやすい。このようなことから、従来の複合型半導体素子では、ばらつきが許容範囲内で収まるようにトリガ電圧を所望の値に設定することが困難な場合があった。
【０００６】
本発明は上記実状に鑑みてなされたもので、ターンオンする電圧を所望の値に容易に設定できる複合型半導体素子を提供することを目的とする。
【０００７】
【課題を解決するための手段】
前記の課題を解決するため、本発明の第１の観点に係る複合型半導体素子は、第１導電型の第１の半導体領域と前記第１の半導体領域に接する第２導電型の第２の半導体領域と前記第２の半導体領域に接する第１導電型の第３の半導体領域と前記第３の半導体領域に接する第２導電型の第４の半導体領域とから構成されるサイリスタと、降伏によりそれぞれに流れる電流の流れる方向が一致するように互いに接続された複数のダイオードからなり、前記第２の半導体領域から前記第３の半導体領域に、または前記第３の半導体領域から前記第２の半導体領域に前記電流が流れるように前記第２の半導体領域と前記第３の半導体領域とに接続されている直列回路と、を備えていることを特徴とする。
このような構成においては、複数のダイオードを直列に接続することによって、ターンオンする電圧を所望の値に容易に設定できる。ひいては、製造する複合型半導体素子ごとの、トリガ電圧のばらつきが許容範囲内に収まりやすい。
【０００８】
前記サイリスタは、前記第１の半導体領域に接続された第１の電極と前記第４の半導体領域に接続された第２の電極とをさらに備え、各前記ダイオードは、ツェナーダイオードであって、前記第１の電極と前記第２の電極との間に電圧が印加されることにより、前記第２の半導体領域と前記第３の半導体領域との接合と各前記ダイオードが持つ接合が逆方向バイアスされ、前記電圧が所定のレベル以上になることにより各前記ダイオードは降伏して電流が流れ、前記サイリスタは各前記ダイオードを降伏により流れる電流をトリガとし、該電流が前記第２の半導体領域または前記第３の半導体領域に流れこむことにより前記第２の半導体領域と前記第３の半導体領域との接合が順バイアスされてターンオンする、ものであってもよい。
【０００９】
各前記ダイオードの降伏電圧は、ほぼ等しい降伏電圧で降伏するようにしてもよい。
【００１０】
前記の課題を解決するため、本発明の第２の観点に係る複合型半導体素子は、上面および下面を有する第１導電型の第１の半導体領域と、前記第１の半導体領域の下面の表面領域に形成された第２導電型の第２の半導体領域と、該第１の半導体領域の上面の表面領域に形成された第２導電型の第３の半導体領域と、前記第３の半導体領域の表面領域に形成された第１導電型の第４の半導体領域とから構成されるサイリスタと、前記第１の半導体領域の上面の表面領域に形成され、前記第３の半導体領域を囲むようにして該第３の半導体領域に電気的に接続された第２導電型の第５の半導体領域と、前記第５の半導体領域の表面領域に形成された第１導電型の第６の半導体領域とから構成される第１のダイオードと、
前記第１の半導体領域の上面の表面領域に、前記第５の半導体領域を囲むように形成された第２導電型の第７の半導体領域と、前記第１の半導体領域の上面の表面領域に、前記第７の半導体領域に接するようにして形成された第１導電型の第８の半導体領域とから構成される第２のダイオードと、前記第１のダイオードと前記第２のダイオードとを互いに直列に接続するように、前記第６の半導体領域と前記第７の半導体領域とに接続された電極と、を備えていることを特徴とする。
このような構成においても、第１および第２のダイオードを直列に接続することによって、ターンオンする電圧を所望の値に容易に設定でき、製造する複合型半導体素子ごとの、トリガ電圧のばらつきが許容範囲内に収まりやすい。
【００１１】
前記サイリスタは、さらに、前記第１の半導体領域に接続されたアノード電極と、前記第４の半導体領域に接続されたカソード電極とをさらに備え、前記第１および第２のダイオードは、ツェナーダイオードであって、前記アノード電極と前記カソード電極との間に電圧が印加されることにより前記第２の半導体領域と前記第３の半導体領域とが形成する接合と前記第１および第２のダイオードのそれぞれが持つ接合が逆方向バイアスされ、前記電圧が所定のレベル以上となることにより前記第１および第２のダイオードは降伏して電流が流れ、前記サイリスタは第１のダイオードと第２のダイオードとを降伏により流れる電流をトリガとし、該電流が前記第２の半導体領域または前記第３の半導体領域に流れこむことにより前記第２の半導体領域と前記第３の半導体領域との接合が順バイアスされてターンオンする、ものであってもよい。
【００１２】
前記複合型半導体素子は、前記第１および第８の半導体領域よりも高い第１導電型の不純物濃度で、該第１の半導体領域の上面の表面領域に該第８の半導体領域に接するように形成された第９の半導体領域をさらに備え、
前記第８の半導体領域は、前記第９の半導体領域を介して前記第１の半導体領域にオーミック接触しているようにしてもよい。
【００１３】
前記第１および第２のダイオードが、ほぼ等しい電圧レベルで降伏するようにしてもよい。
【００１４】
前記の課題を解決するため、本発明の第３の観点に係る複合型半導体素子の製造方法は、上面および下面を有する第１導電型の第１の半導体領域の下面の表面領域に第２導電型の不純物を拡散させることにより第２の半導体領域を形成し、前記第１の半導体領域の上面の表面領域に第２導電型の不純物を拡散させることにより第３の半導体領域を形成し、前記第３の半導体領域の表面領域に第１導電型の不純物を拡散させることにより第４の半導体領域を形成してサイリスタを形成する工程と、前記第１の半導体の上面の表面領域に、前記第３の半導体領域を囲むようにして第２導電型の不純物を拡散することにより該第３の半導体領域に電気的に接続されている第５の半導体領域を形成し、前記第５の半導体領域の表面領域に第１導電型の不純物を拡散することにより第６の半導体領域を形成して第１のダイオードを形成する工程と、前記第１の半導体領域の上面に、前記第５の半導体領域を囲むようにして第２導電型の不純物を拡散することにより第７の半導体領域を形成し、前記第１の半導体領域の上面に第１導電型の不純物を拡散することにより、前記第７の半導体領域に接するように第８の半導体領域を形成して第２のダイオードを形成する工程と、前記第１の半導体基板の上面上に、前記第６の半導体領域と前記第７の半導体領域とに接続されることにより前記第１および第２のダイオードを直列に接続する導体を形成する工程と、を含んでいることを特徴とする。
このような製造工程で複合型半導体素子を製造することにより、ターンオンする電圧を所望の値に容易に設定できる複合型半導体素子を提供できる。
【００１５】
前記第１のダイオードと第２のダイオードとを形成する工程では、前記第５の半導体領域を、前記第７の半導体領域とほぼ等しく、かつ前記第４の半導体領域の不純物濃度よりも低い不純物濃度で形成し、前記第６の半導体領域を、前記第８の半導体領域とほぼ等しく、かつ前記第４の不純物濃度よりも低い不純物濃度で形成するようにしてもよい。
【００１６】
【発明の実施の形態】
以下、本発明の実施の形態に係る複合型半導体素子について、図面を参照して詳細に説明する。
【００１７】
この複合型半導体素子は、逆阻止２端子サイリスタと、互いに直列に接続された複数のツェナーダイオードとが１つの半導体基板に集積されたものである。具体的に説明すると、この複合型半導体素子は、図１に示すように、逆阻止２端子サイリスタと複数のツェナーダイオードとを構成する半導体領域を持つ半導体基板１０と、絶縁膜２０と、カソード電極３０と、アノード電極４０と、電極５０と、金属膜５１とを備えている。
【００１８】
まず、半導体基板１０の構成の詳細について図１および図２を参照して説明する。図２は、半導体基板を上面からみた形状を示している。
半導体基板１０は、図１および図２に示すように、ｎ１領域１１と、ｐ１領域１２と、ｎ２領域１３と、ｐ２領域１４と、第１のｐ型半導体領域１５と、第１のｎ型半導体領域１６と、第２のｐ型半導体領域１７と、第２のｎ型半導体領域１８と、第３のｎ型半導体領域１９とを備えている。ｎ１領域１１、ｐ１領域１２、ｎ２領域１３、ｐ２領域１４は、逆阻止２端子サイリスタを構成する半導体領域である。第１のｐ型半導体領域１５、第１のｎ型半導体領域１６は第１のツェナーダイオードを構成する半導体領域であり、第２のｐ型半導体領域１７、第２のｎ型半導体領域１８は第２のツェナーダイオードを構成する半導体領域である。
【００１９】
なお、図２では、ｎ１領域１１やｐ１領域１２等の構造を理解しやすくするため、絶縁膜２０、カソード電極３０、電極５０、および金属膜５１を省略している。以下では、特に図面番号を指示しないかぎり、図１を参照して説明する。
【００２０】
半導体基板１０は、リン（Ｐ）、ヒ素（Ａｓ）等のｎ型不純物を含んだｎ型の半導体からなる。この半導体基板１０のうち、ｐ１領域１２と、ｎ２領域１３と、ｐ２領域１４と、第１のｐ型半導体領域１５と、第１のｎ型半導体領域１６と、第２のｐ型半導体領域１７と、第２のｎ型半導体領域１８と、第３のｎ型半導体領域１９とを除いた部分が、ｎ１領域１１を構成している。このｎ１領域１１は、例えば１×１０^１４ｃｍ^−３程度の不純物濃度で、また、例えば１９０μｍ程度の厚さで設けられている。
ｎ１領域１１の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。この露出部は、図示するような環状の形状を有する。
【００２１】
ｐ１領域１２は、半導体基板１０の上面の表面領域にボロン（Ｂ）、ガリウム（Ｇａ）等のｐ型不純物を拡散して形成されたｐ型の半導体領域から構成される。具体的には、ｐ１領域１２は、例えば、３×１０^１７ｃｍ^−３程度の不純物濃度で、また、例えば２０μｍ程度の厚さで設けられている。
ｐ１領域１２の一部は、半導体基板１０の上面からみると、図２に示すように、半導体基板１０の上面の表面に露出している。ｐ１領域１２の露出部は、ｎ２領域１３を包囲するような環状の形状を有する。
【００２２】
ｎ２領域１３は、ｐ１領域１２にｎ型不純物を拡散して形成された、ｎ１領域１１よりも不純物濃度の高いｎ型の半導体領域から構成される。具体的に説明すると、ｎ２領域１３は、例えば、８×１０^１９ｃｍ^−３程度の不純物濃度で、また、例えば１０μｍ程度の厚さで設けられている。
ｎ２領域１３の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。ｎ２領域１３の露出部は、図２に示すような島状の形状を有する。
【００２３】
ｐ２領域１４は、半導体基板１０の下面の表面領域にｐ型不純物を拡散して形成された、ｐ１領域１２とほぼ等しい不純物濃度のｐ型の半導体領域から構成される。詳細には、ｐ２領域１４は、例えば、３×１０^１７ｃｍ^−３程度の不純物濃度で、また、例えば２０μｍ程度の厚さで設けられている。ｐ２領域１４は、半導体基板１０の下面の表面に露出している。
【００２４】
第１のｐ型半導体領域１５は、ｎ１領域１１にｐ型不純物を拡散して形成された、ｐ１領域１２よりもｐ型不純物濃度の低いｐ型の半導体領域から構成される。具体的には、第１のｐ型半導体領域１５は、例えば、５×１０^１５ｃｍ^−３程度の不純物濃度で、また、例えば１５μｍ程度の厚さで設けられている。
第１のｐ型半導体領域１５の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。第１のｐ型半導体領域１５の露出部は、図２に示すように、ｐ１領域１２の露出部を包囲するような環状の形状を有する。
【００２５】
第１のｎ型半導体領域１６は、第１のｐ型半導体領域１５にｎ型不純物を拡散して形成された、ｎ２領域１３よりもｎ型不純物濃度の低いｎ型の半導体基板から構成されている。より詳細には、第１のｎ型半導体領域１６は、例えば、２×１０^１６ｃｍ^−３程度の不純物濃度で、また、例えば５μｍ程度の厚さで設けられている。
第１のｎ型半導体領域１６の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。第１のｎ型半導体領域１６の露出部は、図２に示すように、第１のｐ型半導体領域１５の露出部を２分割するような環状の形状を持つ。
【００２６】
第２のｐ型半導体領域１７は、ｎ１領域１１にｐ型不純物を拡散して形成された、第１のｐ型半導体領域１５とほぼ等しいｐ型不純物濃度のｐ型半導体領域から構成されている。具体的には、第２のｐ型半導体領域１７は、例えば、５×１０^１５ｃｍ^−３程度の不純物濃度で、また、例えば１５μｍ程度の厚さで設けられている。
第２のｐ型半導体領域１７の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。第２のｐ型半導体領域１７の露出部は、図２に示すように、ｎ１領域１１の露出部を包囲するような環状の形状を有する。
【００２７】
第２のｎ型半導体領域１８は、第２のｐ型半導体領域１７およびｎ１領域１１に部分的にｎ型不純物を拡散して形成された、第１のｎ型半導体領域１６とほぼ等しいｎ型不純物濃度のｎ型の半導体領域から構成されている。より詳細には、第２のｎ型半導体領域１８は、例えば、２×１０^１６ｃｍ^−３程度の不純物濃度で、また、例えば５μｍ程度の厚さで設けられている。
第２のｎ型半導体領域１８の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。第２のｎ型半導体領域１８の露出部は、図２に示すような環状の形状を有する。
【００２８】
第３のｎ型半導体領域１９は、ｎ１領域１１にｎ型不純物を拡散して形成された、第２のｎ型半導体領域１８よりもｎ型不純物濃度の高いｎ型の半導体領域からなる。より具体的には、第３のｎ型半導体領域１９は、例えば、８×１０^１９ｃｍ^−３程度の不純物濃度で、また、例えば１０μｍ程度の厚さで設けられている。
第３のｎ型半導体領域１９の一部は、図２に示すように、半導体基板１０の上面の表面に露出している。第３のｎ型半導体領域１９の露出部は、図２に示すような環状の形状を有する。
【００２９】
このような構成を有する半導体基板１０において、ｎ１領域１１とｐ２領域１４との界面でｐｎ接合Ｊ１が形成され、ｎ１領域１１とｐ１領域１２との界面でｐｎ接合Ｊ２が形成され、ｐ１領域１２とｎ２領域１３との界面でｐｎ接合Ｊ３が形成される。また、第１のｐ型半導体領域１５と第１のｎ型半導体領域１６との界面でｐｎ接合Ｊ４が形成され、第２のｐ型半導体領域１７と第２のｎ型半導体領域１８との界面でｐｎ接合Ｊ５が形成される。以下では、ｐｎ接合を総称して、接合と呼ぶ。
【００３０】
従って、上述のようにｎ１領域１１とｐ１領域１２とｎ２領域１３とｐ２領域１４とからなる逆阻止２端子サイリスタ（以下サイリスタ）は、３つの接合Ｊ１、Ｊ２、Ｊ３を備えている。
また、第１のｐ型半導体領域１５と第１のｎ型半導体領域１６とからなる第１のツェナーダイオード（以下第１のダイオード）は、接合Ｊ４を備えている。
さらに、第２のｐ型半導体領域１７と第２のｎ型半導体領域１８とからなる第２のツェナーダイオード（以下第２のダイオード）は、接合Ｊ５を備えている。
【００３１】
この複合型半導体素子の基本構造および等価回路をそれぞれ図３（ａ）および図３（ｂ）に示す。
第１のダイオードの、第１のｐ型半導体領域１５は、図１に示すように、サイリスタのｐ１領域１２に接続されている。従って、第１のダイオードは、図３（ａ）、図３（ｂ）に示すように、ｐ１領域１２とｎ２領域１３とを介してカソード電極３０に電気的に接続されている。また、第１のダイオードの、第１のｎ型半導体領域１６は、図１に示すように、電極５０を介して第２のダイオードの第２のｐ型半導体領域１７に接続されている。従って、第１のダイオードと第２のダイオードとは図３（ａ）、図３（ｂ）に示すように、直列に接続されている。
【００３２】
第２のダイオードの第２のｎ型半導体領域１８は、図１に示すように、第３のｎ型半導体領域１９を介してｎ１領域１１にオーミック接触している。従って、第２のダイオードは、図３（ａ）、図３（ｂ）に示すように、サイリスタのｎ１領域１１に電気的に接続されている。第１のダイオードと第２のダイオードとは、サイリスタのｎ１領域１１とｐ１領域１２とに電気的に接続された直列回路をなす。
【００３３】
接合Ｊ４および接合Ｊ５の降伏電圧は、第１および第２のダイオードを構成する半導体領域のうち、第１および第２のｎ型半導体領域１６、１８のｎ型不純物濃度が接合Ｊ２を形成する半導体領域のうち、ｎ１領域１１のｎ型不純物濃度よりも高いので、接合Ｊ２の降伏電圧よりも低い。また、第１のダイオードの降伏電圧は、第１のｐ型半導体領域１５と第２のｐ型半導体領域１７とのｐ型不純物濃度がそれぞれほぼ等しく、かつ第１のｎ型半導体領域１６と第２のｎ型半導体領域１８とのｎ型不純物濃度がそれぞれほぼ等しいので、第２のダイオードの降伏電圧とほぼ等しい。
【００３４】
なお、第２のｎ型半導体領域１８のｎ型不純物濃度がｎ１領域１１のｎ型不純物濃度よりも高いので、第２のｎ型半導体領域１８は第３のｎ型半導体領域１９を介さなくてもｎ１領域１１に実質的にはオーミック接触できる。しかし、第３のｎ型半導体領域を設けることにより、第２のｎ型半導体領域１８とｎ１領域１１との接触抵抗が大きくて電流が流れにくいような場合に、電流が第３のｎ型半導体領域１９を介して第１および第２のダイオードとｎ１領域１１との間を流れることができる。本実施の形態では、電気伝導を確実にするために第３のｎ型半導体領域１９を設けている。サイリスタ、第１および第２のダイオードの動作の詳細については、後述する。
【００３５】
次に、絶縁膜２０、カソード電極３０、アノード電極４０、電極５０、金属膜５１の構成の詳細について図１を参照して説明する。
絶縁膜２０は、酸化シリコン膜等から構成されており、半導体基板１０の上面に形成されている。絶縁膜２０には、ｐ１領域１２およびｎ２領域１３がカソード電極３０に接続できるように、開口２１が設けられている。また、絶縁膜２０には、第１ｎ型半導体領域１６および第２ｐ型半導体領域１７が電極５０に接続できるように開口２２、２３が設けられている。さらに、絶縁膜２０には、第２ｎ型半導体領域１８が金属膜５１に接続されるよう、開口２４が設けられている。
【００３６】
カソード電極３０は、アルミニウム膜等から構成されており、半導体基板１０の上面に、ｐ１領域１２とｎ２領域１３とを被覆するように形成されている。カソード電極３０は、ｐ１領域１２とｎ２領域１３とに接続されている。
【００３７】
アノード電極４０は、アルミニウム膜等から構成されており、半導体基板１０の下面に、ｐ２領域１４を被覆するように形成されている。従って、アノード電極４０は、ｐ２領域１４に接続されている。
【００３８】
電極５０は、アルミニウム膜等から構成されている。電極５０は、絶縁膜２０の開口２２、２３を介して第１のｎ型半導体領域１６、第２のｐ型半導体領域１７に接続されている。従って電極５０は、第１のダイオードと第２のダイオードに接続されている。この電極５０は、カソード電極３０に接していない。
【００３９】
金属膜５１は、アルミニウム膜等から構成されている。金属膜５１は、絶縁膜２０の開口２４を介して第２のｎ型半導体領域１８に接続されている。金属膜５１は、第２のｎ型半導体領域１８の表面電位を安定化する。この金属膜５１は、カソード電極３０および電極５０に接していない。
【００４０】
次に、以上の構成を有するこの複合型半導体素子を製造する手順を、図４（ａ）〜図８（ｏ）を参照して説明する。なお、以下に示す手順は一例であり、同様の構造が得られるのであれば、いかなる手順であっても構わない。
まず、ｎ型半導体基板からなる半導体基板１０を用意する。次に、イオン注入等によって、半導体基板１０の下面にｐ型の不純物を注入し、図４（ａ）に示すように、ｐ型の半導体領域（すなわちｐ２領域１４）を形成する。
【００４１】
次に、図４（ｂ）に示すように、第１のｐ型半導体領域１５形成予定領域上および第２のｐ型半導体領域１７形成予定領域上以外の半導体基板１０の上面上にフォトレジスト６０を形成する。続いて、イオン注入等によって、ｐ型不純物をｎ１領域１１に注入し、不純物濃度がそれぞれ等しいｐ型の半導体領域（第１のｐ型半導体領域１５、第２のｐ型半導体領域１７）を図４（ｃ）に示すように形成する。
【００４２】
次に、フォトレジスト６０を剥離する。フォトレジスト６０の剥離に続いて、図５（ｄ）に示すように、第１のｎ型半導体領域１６形成予定領域上および第２のｎ型半導体領域１８形成予定領域上以外の半導体基板１０の上面上にフォトレジスト６１を形成する。
【００４３】
続いて、イオン注入等によってｎ型不純物を第１のｐ型半導体領域１５に注入し、図５（ｅ）に示すように、ｎ型の半導体領域（第１のｎ型半導体領域１６）を形成する。同様に、イオン注入等によってｎ型の不純物を第２のｐ型半導体領域１７に注入し、第１のｎ型半導体領域１６とｎ型不純物濃度がほぼ等しいｎ型の半導体領域（第２のｎ型半導体領域１８）を図４（ｅ）に示すように形成する。
【００４４】
第１および第２のｎ型半導体領域１６、１８を形成した後、フォトレジスト６１を剥離する。次に、図５（ｆ）に示すように、第３のｎ型半導体領域１９形成予定領域上以外の半導体基板１０の上面上にフォトレジスト６２を形成する。そして、イオン注入等によってｎ型不純物を第２のｎ型半導体領域１８およびｎ１領域１１に注入し、図６（ｇ）に示すように、第３のｎ型半導体領域１９を形成する。
【００４５】
第３のｎ型半導体領域１９を形成した後、フォトレジスト６２を除去する。次に、図６（ｈ）に示すように、ｐ１領域１２形成予定領域上以外の半導体基板１０の上面上にフォトレジスト６３を形成する。フォトレジスト６３をマスクとして用いて、イオン注入等によりｐ型不純物を第１のｐ型半導体領域１５およびｎ１領域１１に注入し、図６（ｉ）に示すように、ｐ型の半導体領域（ｐ１領域１２）を形成する。
【００４６】
フォトレジスト６３を剥離し、次に、図７（ｊ）に示すように、ｎ２領域１３形成予定領域上以外の半導体基板１０の上面にフォトレジスト６４を形成する。次に、イオン注入等によりｎ型不純物をｐ１領域１２に注入し、図７（ｋ）に示すように、ｎ型の半導体領域（ｎ２領域１３）を形成する。ｎ２領域１３を形成後、フォトレジスト６４を剥離し、半導体基板１０にアニールを施し、イオン注入したｐ型、ｎ型の不純物を活性化する。
【００４７】
次に、半導体基板１０の上面上に、ＣＶＤ（Chemical Vapor Deposition）等により、図７（ｌ）に示すようにシリコン酸化膜６５を形成する。このシリコン酸化膜６５に、エッチングを施して図８（ｍ）に示すように開口２１、２２、２３、２４を設け、絶縁膜２０を形成する。
【００４８】
続いて、半導体基板１０の上面上に、ＰＶＤ（Physical Vapor Deposition）等により、アルミニウム膜等を形成する。このアルミニウム膜をパターニングして、図８（ｎ）に示すように、カソード電極３０、電極５０、金属膜５１を形成する。カソード電極３０は、開口２１を介してｐ１領域１２およびｎ２領域１３に電気的に接続される。電極５０は、開口２２を介して第１のｎ型半導体領域１６に接続され、かつ開口２３を介して第２のｐ型半導体領域１７に接続される。また、金属膜５１は、開口２４を介して第２のｎ型半導体領域１８に接続される。
【００４９】
そして、半導体基板１０の他面上にＰＶＤ等によって、図８（ｏ）に示すように、ｐ２領域１４に接続されるアノード電極４０を形成する。
【００５０】
次に、以上説明したこの複合型半導体素子の動作を説明する。
アノード電極４０に正、カソード電極３０に負の電圧（順方向電圧）を印加すると、接合Ｊ１、Ｊ３は順方向バイアス状態となり、接合Ｊ２、Ｊ４、Ｊ５は逆方向バイアス状態となる。
【００５１】
印加する電圧が所定の値以上になると、接合Ｊ２の降伏電圧と比べて降伏電圧が低い接合Ｊ４、Ｊ５とで降伏現象が起こり、カソード電極３０から電子が第１および第２のダイオードに注入される。注入された電子は、第３のｎ型半導体領域１９を介してｎ１領域１１に注入され、さらにｐ２領域１４に注入される。
【００５２】
ｐ２領域１４に電子が注入されることにより、正孔がｐ２領域１４からｎ１領域１１に注入される。注入された正孔は、さらに、第３のｎ型半導体領域１９を介して第２のダイオードと第１のダイオードとに注入される。従って、第１および第２のダイオードに逆方向電流が流れる。この逆方向電流は、ｐ１領域１２に流れ込む。この逆方向電流は、ｐ１領域１２の横方向の抵抗（図１のＸ−Ｘ方向の層抵抗）により電圧降下を生じさせ、これにより接合Ｊ２が順方向にバイアスされ、サイリスタがターンオンする。従って複合型半導体素子がターンオンした状態になる。
【００５３】
このように、本実施の形態の複合型半導体素子は、複数のダイオードを、降伏により流れる逆方向電流の流れる方向が一致するように直列接続し、この複数のダイオードの降伏により流れる逆方向電流をトリガとして用いてサイリスタをオンさせる。
【００５４】
一般的に、ダイオードを構成する半導体領域の不純物濃度が高いほどダイオードの降伏電圧は低くなるが、製造時にダイオードごとの降伏電圧の差が許容範囲内で収まりやすい（ばらつきが小さい）。一方、不純物濃度が低いほどダイオードの降伏電圧は高くなるが、製造時にダイオードごとの降伏電圧の差が許容範囲を超えやすい（ばらつきが大きい）。
この複合型半導体素子は、製造時にばらつきが小さい、降伏電圧が低電圧のダイオードを複数個直列接続して、サイリスタが所望の電圧でオンするようにしている。このダイオードの接続個数を適宜増やすことにより、サイリスタが所望の高い電圧でオンするようにすることができる。各ダイオードに降伏により流れる電流は、各ダイオードの許容限度以下の小電流でよく、各ダイオードが逆方向電流による発熱によって破壊には至りにくい。さらに、複数のダイオードがほぼ等しい降伏電圧で降伏するので、複数のダイオードの制御が容易である。
【００５５】
通常は、サイリスタがオンする電圧（トリガ電圧）の設定が２５０Ｖ以上になると、製造する複合型半導体素子ごとの、トリガ電圧のばらつきが許容範囲を超えやすい。しかし、以上のような構成を採用することにより、この複合型半導体素子はトリガ電圧の設定が２５０Ｖ以上になっても、製造する複合型半導体素子ごとの、トリガ電圧のばらつきが許容範囲内に収まりやすい。
【００５６】
なお、本発明は上記実施の形態に限定されず、種々の応用および変更が可能である。
例えば、逆阻止型のサイリスタの代わりに、双方向性サイリスタを用いてもよい。この場合には、図９（ａ）に示すような構造を採用するとよい。すなわち、図３（ａ）の基本構造に加えて、ｎ１領域１１とｐ２領域１４とに接続された複数のダイオードをさらに設ける。この際、それぞれに降伏により流れる電流の流れる方向が一致するように複数のダイオードを直列に接続する。
【００５７】
また、上記実施の形態では、ｎ２領域１３を、島状に形成する場合を例として説明した。しかし、ｎ２領域１３の形状はこれに限定されず、例えば帯状に形成してもよい。この場合には、ｐ１領域１２等ｎ２領域１３を包囲する他の半導体領域の形状を、ｎ２領域１３の形状に合わせて、適宜変更する。
【００５８】
さらには、上記実施の形態では、第１のｐ型半導体領域は、直接ｐ１領域１２に接することによって、ｐ１領域１２に電気的に接続されていた。しかし、図９（ｂ）に示すように、第１のｐ型半導体領域１５は、カソード電極３０を介してｐ１領域１２に接続されてもよい。この場合には、図示するように、絶縁膜２０に、第１のｐ型半導体領域１５が、カソード電極３０に接するように開口２５を設ける。
【００５９】
あるいは、上記実施の形態では、ダイオードを２つ直列接続する場合を例にして説明したが、トリガ電圧を所望の値に設定するために３つ以上直列接続してもよい。
【００６０】
【発明の効果】
以上説明したように、本発明によれば、ターンオンする電圧を所望の値に容易に設定できる複合型半導体素子を提供することを目的とする。
【図面の簡単な説明】
【図１】図１は本発明の実施の形態にかかる複合型半導体素子の構成を示す断面図である。
【図２】図２は図１の複合型半導体素子の上面の一部を示す平面図である。
【図３】図３（ａ）および図３（ｂ）は、それぞれ、図１の複合型半導体素子の基本構造および等価回路を示す図である。
【図４】図４（ａ）乃至図４（ｃ）は、図１の複合型半導体素子の製造工程を説明するための断面図である。
【図５】図５（ｄ）乃至図５（ｆ）は、図１の複合型半導体素子の製造工程を説明するための断面図である。
【図６】図６（ｇ）乃至図６（ｉ）は、図１の複合型半導体素子の製造工程を説明するための断面図である。
【図７】図７（ｊ）乃至図７（ｌ）は、図１の複合型半導体素子の製造工程を説明するための断面図である。
【図８】図８（ｍ）乃至図８（ｏ）は、図１の複合型半導体素子の製造工程を説明するための断面図である。
【図９】図９（ａ）および図９（ｂ）は本発明の実施の形態に係る複合型半導体素子の変形例を示す断面図である。
【符号の説明】
１０半導体基板
１１ｎ１領域
１２ｐ１領域
１３ｎ２領域
１４ｐ２領域
１５第１のｐ型半導体領域
１６第１のｎ型半導体領域
１７第２のｐ型半導体領域
１８第２のｎ型半導体領域
１９第３のｎ型半導体領域
２０絶縁膜
３０カソード電極
４０アノード電極
５０電極
５１金属膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a composite semiconductor device and a method for manufacturing the same.
[0002]
[Prior art]
A thyristor, which is a kind of semiconductor element, is used in a power supply circuit or the like. Some thyristors have a structure of a pn junction diode combined with a normal pnpn four-layer structure in order to improve the characteristics (see, for example, Patent Document 1). Hereinafter, a combination of a thyristor and a diode is referred to as a composite semiconductor element.
[0003]
[Patent Document 1]
JP-A-4-340276
[0004]
In general, this type of conventional composite semiconductor element generally includes a p1 region constituting a thyristor, an n1 region connected to the p1 region, a p2 region connected to the n1 region, and an n2 region connected to the p2 region. In addition, it has an n-type semiconductor region which is connected to the n1 region and the p2 region and forms a diode together with the p2 region. The thyristor further includes an anode electrode connected to the p1 region and a cathode electrode connected to the p2 region and the n2 region.
The diode breaks down when a voltage of a predetermined value or more is applied between the anode and cathode electrodes, and the thyristor is turned on using a reverse current that flows due to the breakdown of the diode.
[0005]
[Problems to be solved by the invention]
In such a configuration, in order to set a voltage (trigger voltage) at which the thyristor is turned on to a desired value, it is necessary to change the impurity concentration of the n-type semiconductor region or the p2 region.
In general, the higher the impurity concentration, the easier it is to set the trigger voltage to a desired value (the trigger voltage difference for each composite semiconductor element to be manufactured tends to be within an allowable range, that is, the individual difference is small). Also, the lower the impurity concentration, the more difficult it is to set the trigger voltage to a desired value (the trigger voltage difference for each composite semiconductor element exceeds the allowable range, that is, the individual difference is large). If the trigger voltage setting is less than 250V, the trigger voltage variation tends to fall within the allowable range. However, if the trigger voltage setting exceeds 250V, the trigger voltage variation tends to exceed the allowable range. For this reason, in the conventional composite semiconductor device, it may be difficult to set the trigger voltage to a desired value so that the variation is within an allowable range.
[0006]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a composite semiconductor element that can easily set a turn-on voltage to a desired value.
[0007]
[Means for Solving the Problems]
In order to solve the above problem, a composite semiconductor element according to a first aspect of the present invention includes a first semiconductor region of a first conductivity type and a second conductivity type of a second semiconductor layer in contact with the first semiconductor region. A thyristor including a semiconductor region, a third semiconductor region of a first conductivity type in contact with the second semiconductor region, and a fourth semiconductor region of a second conductivity type in contact with the third semiconductor region; It consists of a plurality of diodes connected to each other so that the directions of currents flowing through them match each other, from the second semiconductor region to the third semiconductor region, or from the third semiconductor region to the second semiconductor And a series circuit connected to the second semiconductor region and the third semiconductor region so that the current flows in the region.
In such a configuration, the turn-on voltage can be easily set to a desired value by connecting a plurality of diodes in series. As a result, the trigger voltage variation for each composite semiconductor element to be manufactured tends to fall within an allowable range.
[0008]
The thyristor further includes a first electrode connected to the first semiconductor region and a second electrode connected to the fourth semiconductor region, wherein each of the diodes is a Zener diode, By applying a voltage between the first electrode and the second electrode, the junction between the second semiconductor region and the third semiconductor region and the junction of each diode are reversely biased. When the voltage exceeds a predetermined level, each of the diodes breaks down and a current flows, and the thyristor is triggered by a current flowing through each of the diodes by breakdown, and the current is generated in the second semiconductor region or the second semiconductor region. The junction between the second semiconductor region and the third semiconductor region may be forward biased and turned on by flowing into the third semiconductor region.
[0009]
The breakdown voltage of each of the diodes may be broken with a substantially equal breakdown voltage.
[0010]
In order to solve the above problems, a composite semiconductor device according to a second aspect of the present invention includes a first conductive type first semiconductor region having an upper surface and a lower surface, and a surface of the lower surface of the first semiconductor region. A second conductivity type second semiconductor region formed in the region, a second conductivity type third semiconductor region formed in a surface region of the upper surface of the first semiconductor region, and the third semiconductor region A thyristor formed of a first semiconductor region of the first conductivity type formed in the surface region of the first semiconductor region, and a surface region of the upper surface of the first semiconductor region so as to surround the third semiconductor region. A second conductive type fifth semiconductor region electrically connected to the third semiconductor region, and a first conductive type sixth semiconductor region formed in a surface region of the fifth semiconductor region; A first diode to be
In a surface region on the upper surface of the first semiconductor region, a seventh semiconductor region of a second conductivity type formed so as to surround the fifth semiconductor region, and on a surface region on the upper surface of the first semiconductor region A second diode composed of an eighth semiconductor region of the first conductivity type formed so as to be in contact with the seventh semiconductor region, and the first diode and the second diode are connected to each other. An electrode connected to the sixth semiconductor region and the seventh semiconductor region so as to be connected in series is provided.
Even in such a configuration, by connecting the first and second diodes in series, the turn-on voltage can be easily set to a desired value, and the variation of the trigger voltage for each composite semiconductor element to be manufactured is allowed. Easy to fit within range.
[0011]
The thyristor further includes an anode electrode connected to the first semiconductor region and a cathode electrode connected to the fourth semiconductor region, and the first and second diodes are Zener diodes. A junction formed by the second semiconductor region and the third semiconductor region by applying a voltage between the anode electrode and the cathode electrode, and each of the first and second diodes. When the junction of the first and second diodes is reverse-biased and the voltage exceeds a predetermined level, the first and second diodes break down and current flows, and the thyristor connects the first diode and the second diode. The current flowing due to breakdown is used as a trigger, and when the current flows into the second semiconductor region or the third semiconductor region, the second semiconductor Junction between the region and the third semiconductor region is turned on is forward biased, or may be.
[0012]
The composite semiconductor element has an impurity concentration of the first conductivity type higher than that of the first and eighth semiconductor regions, and is in contact with the eighth semiconductor region on the surface region of the upper surface of the first semiconductor region. A ninth semiconductor region formed;
The eighth semiconductor region may be in ohmic contact with the first semiconductor region via the ninth semiconductor region.
[0013]
The first and second diodes may breakdown at approximately equal voltage levels.
[0014]
In order to solve the above-described problem, a method for manufacturing a composite semiconductor device according to a third aspect of the present invention provides a second conductive material in a lower surface region of a first conductive type first semiconductor region having an upper surface and a lower surface. A second semiconductor region is formed by diffusing a type impurity, and a third semiconductor region is formed by diffusing a second conductivity type impurity in a surface region of the upper surface of the first semiconductor region; Forming a fourth semiconductor region by diffusing a first conductivity type impurity in a surface region of the third semiconductor region to form a thyristor; and forming a thyristor on the surface region of the upper surface of the first semiconductor. A fifth semiconductor region electrically connected to the third semiconductor region is formed by diffusing impurities of the second conductivity type so as to surround the third semiconductor region, and a surface region of the fifth semiconductor region Of the first conductivity type A step of forming a first diode by diffusing pure material to form a first diode; and a second conductivity type on the upper surface of the first semiconductor region so as to surround the fifth semiconductor region. A seventh semiconductor region is formed by diffusing impurities, and an eighth semiconductor is formed in contact with the seventh semiconductor region by diffusing impurities of the first conductivity type on the upper surface of the first semiconductor region. Forming a second diode by forming a region; and connecting the sixth semiconductor region and the seventh semiconductor region on the top surface of the first semiconductor substrate, thereby connecting the first and the seventh semiconductor regions. Forming a conductor connecting the second diodes in series.
By manufacturing the composite semiconductor element in such a manufacturing process, it is possible to provide a composite semiconductor element that can easily set a turn-on voltage to a desired value.
[0015]
In the step of forming the first diode and the second diode, the fifth semiconductor region has an impurity concentration substantially equal to the seventh semiconductor region and lower than the impurity concentration of the fourth semiconductor region. The sixth semiconductor region may be formed with an impurity concentration that is substantially equal to the eighth semiconductor region and lower than the fourth impurity concentration.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a composite semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.
[0017]
This composite semiconductor element is obtained by integrating a reverse blocking two-terminal thyristor and a plurality of Zener diodes connected in series to one semiconductor substrate. More specifically, as shown in FIG. 1, the composite semiconductor element includes a semiconductor substrate 10 having a semiconductor region that constitutes a reverse blocking two-terminal thyristor and a plurality of Zener diodes, an insulating film 20, a cathode electrode. 30, an anode electrode 40, an electrode 50, and a metal film 51.
[0018]
First, details of the configuration of the semiconductor substrate 10 will be described with reference to FIGS. 1 and 2. FIG. 2 shows the shape of the semiconductor substrate as viewed from above.
As shown in FIGS. 1 and 2, the semiconductor substrate 10 includes an n1 region 11, a p1 region 12, an n2 region 13, a p2 region 14, a first p-type semiconductor region 15, and a first n-type semiconductor. A semiconductor region 16, a second p-type semiconductor region 17, a second n-type semiconductor region 18, and a third n-type semiconductor region 19 are provided. The n1 region 11, the p1 region 12, the n2 region 13, and the p2 region 14 are semiconductor regions that constitute a reverse blocking two-terminal thyristor. The first p-type semiconductor region 15 and the first n-type semiconductor region 16 are semiconductor regions constituting the first Zener diode, and the second p-type semiconductor region 17 and the second n-type semiconductor region 18 are the first ones. 2 is a semiconductor region constituting two Zener diodes.
[0019]
In FIG. 2, the insulating film 20, the cathode electrode 30, the electrode 50, and the metal film 51 are omitted for easy understanding of the structure of the n1 region 11 and the p1 region 12. The following description will be made with reference to FIG. 1 unless otherwise specified.
[0020]
The semiconductor substrate 10 is made of an n-type semiconductor containing an n-type impurity such as phosphorus (P) or arsenic (As). Among the semiconductor substrates 10, the p1 region 12, the n2 region 13, the p2 region 14, the first p-type semiconductor region 15, the first n-type semiconductor region 16, and the second p-type semiconductor region 17. The portion excluding the second n-type semiconductor region 18 and the third n-type semiconductor region 19 constitutes the n1 region 11. The n1 region 11 is, for example, 1 × 10 ¹⁴ cm ^-3 It is provided with an impurity concentration of about, and a thickness of about 190 μm, for example.
A part of the n1 region 11 is exposed on the surface of the upper surface of the semiconductor substrate 10 as shown in FIG. This exposed portion has an annular shape as shown.
[0021]
The p1 region 12 includes a p-type semiconductor region formed by diffusing p-type impurities such as boron (B) and gallium (Ga) in the surface region of the upper surface of the semiconductor substrate 10. Specifically, the p1 region 12 is, for example, 3 × 10. ¹⁷ cm ^-3 It is provided with an impurity concentration of about, and a thickness of about 20 μm, for example.
A part of the p1 region 12 is exposed on the upper surface of the semiconductor substrate 10 as seen from the upper surface of the semiconductor substrate 10 as shown in FIG. The exposed portion of the p1 region 12 has an annular shape that surrounds the n2 region 13.
[0022]
The n2 region 13 is composed of an n-type semiconductor region formed by diffusing an n-type impurity in the p1 region 12 and having an impurity concentration higher than that of the n1 region 11. More specifically, the n2 region 13 is, for example, 8 × 10. ¹⁹ cm ^-3 It is provided with an impurity concentration of about, and with a thickness of about 10 μm, for example.
A part of the n2 region 13 is exposed on the surface of the upper surface of the semiconductor substrate 10 as shown in FIG. The exposed portion of the n2 region 13 has an island shape as shown in FIG.
[0023]
The p2 region 14 is composed of a p-type semiconductor region having an impurity concentration substantially equal to that of the p1 region 12 formed by diffusing p-type impurities in the surface region on the lower surface of the semiconductor substrate 10. Specifically, the p2 region 14 is, for example, 3 × 10. ¹⁷ cm ^-3 It is provided with an impurity concentration of about, and a thickness of about 20 μm, for example. The p2 region 14 is exposed on the surface of the lower surface of the semiconductor substrate 10.
[0024]
The first p-type semiconductor region 15 is composed of a p-type semiconductor region formed by diffusing a p-type impurity in the n1 region 11 and having a lower p-type impurity concentration than the p1 region 12. Specifically, the first p-type semiconductor region 15 is, for example, 5 × 10 5. ¹⁵ cm ^-3 It is provided with an impurity concentration of about, and with a thickness of about 15 μm, for example.
A part of the first p-type semiconductor region 15 is exposed on the surface of the upper surface of the semiconductor substrate 10 as shown in FIG. As shown in FIG. 2, the exposed portion of the first p-type semiconductor region 15 has an annular shape that surrounds the exposed portion of the p1 region 12.
[0025]
The first n-type semiconductor region 16 is composed of an n-type semiconductor substrate formed by diffusing an n-type impurity in the first p-type semiconductor region 15 and having a lower n-type impurity concentration than the n2 region 13. Yes. More specifically, the first n-type semiconductor region 16 is, for example, 2 × 10 ¹⁶ cm ^-3 It is provided with an impurity concentration of about, and with a thickness of about 5 μm, for example.
A part of the first n-type semiconductor region 16 is exposed on the surface of the upper surface of the semiconductor substrate 10 as shown in FIG. As shown in FIG. 2, the exposed portion of the first n-type semiconductor region 16 has an annular shape that divides the exposed portion of the first p-type semiconductor region 15 into two.
[0026]
The second p-type semiconductor region 17 is composed of a p-type semiconductor region having a p-type impurity concentration substantially equal to that of the first p-type semiconductor region 15 formed by diffusing a p-type impurity in the n1 region 11. . Specifically, the second p-type semiconductor region 17 is, for example, 5 × 10 5. ¹⁵ cm ^-3 It is provided with an impurity concentration of about, and with a thickness of about 15 μm, for example.
A part of the second p-type semiconductor region 17 is exposed on the upper surface of the semiconductor substrate 10 as shown in FIG. As shown in FIG. 2, the exposed portion of the second p-type semiconductor region 17 has an annular shape that surrounds the exposed portion of the n1 region 11.
[0027]
The second n-type semiconductor region 18 is an n-type substantially equal to the first n-type semiconductor region 16 formed by partially diffusing an n-type impurity in the second p-type semiconductor region 17 and the n1 region 11. It is composed of an n-type semiconductor region having an impurity concentration. More specifically, the second n-type semiconductor region 18 is, for example, 2 × 10 ¹⁶ cm ^-3 It is provided with an impurity concentration of about, and with a thickness of about 5 μm, for example.
A part of the second n-type semiconductor region 18 is exposed on the upper surface of the semiconductor substrate 10 as shown in FIG. The exposed portion of the second n-type semiconductor region 18 has an annular shape as shown in FIG.
[0028]
The third n-type semiconductor region 19 is an n-type semiconductor region formed by diffusing an n-type impurity in the n1 region 11 and having an n-type impurity concentration higher than that of the second n-type semiconductor region 18. More specifically, the third n-type semiconductor region 19 is, for example, 8 × 10 8. ¹⁹ cm ^-3 It is provided with an impurity concentration of about, and with a thickness of about 10 μm, for example.
A part of the third n-type semiconductor region 19 is exposed on the upper surface of the semiconductor substrate 10 as shown in FIG. The exposed portion of the third n-type semiconductor region 19 has an annular shape as shown in FIG.
[0029]
In the semiconductor substrate 10 having such a configuration, a pn junction J1 is formed at the interface between the n1 region 11 and the p2 region 14, a pn junction J2 is formed at the interface between the n1 region 11 and the p1 region 12, and the p1 region 12 And the n2 region 13 form a pn junction J3. In addition, a pn junction J4 is formed at the interface between the first p-type semiconductor region 15 and the first n-type semiconductor region 16, and the interface between the second p-type semiconductor region 17 and the second n-type semiconductor region 18 is formed. Thus, the pn junction J5 is formed. Hereinafter, the pn junction is generically called a junction.
[0030]
Therefore, as described above, the reverse blocking two-terminal thyristor (hereinafter referred to as thyristor) composed of the n1 region 11, the p1 region 12, the n2 region 13, and the p2 region 14 includes three junctions J1, J2, and J3.
The first Zener diode (hereinafter referred to as the first diode) composed of the first p-type semiconductor region 15 and the first n-type semiconductor region 16 includes a junction J4.
Furthermore, a second Zener diode (hereinafter referred to as a second diode) composed of the second p-type semiconductor region 17 and the second n-type semiconductor region 18 includes a junction J5.
[0031]
The basic structure and equivalent circuit of this composite type semiconductor device are shown in FIGS. 3 (a) and 3 (b), respectively.
As shown in FIG. 1, the first p-type semiconductor region 15 of the first diode is connected to the p1 region 12 of the thyristor. Accordingly, the first diode is electrically connected to the cathode electrode 30 via the p1 region 12 and the n2 region 13 as shown in FIGS. 3 (a) and 3 (b). In addition, the first n-type semiconductor region 16 of the first diode is connected to the second p-type semiconductor region 17 of the second diode through the electrode 50 as shown in FIG. Therefore, the first diode and the second diode are connected in series as shown in FIGS. 3 (a) and 3 (b).
[0032]
As shown in FIG. 1, the second n-type semiconductor region 18 of the second diode is in ohmic contact with the n1 region 11 via the third n-type semiconductor region 19. Therefore, the second diode is electrically connected to the n1 region 11 of the thyristor, as shown in FIGS. 3 (a) and 3 (b). The first diode and the second diode form a series circuit electrically connected to the n1 region 11 and the p1 region 12 of the thyristor.
[0033]
The breakdown voltage of the junction J4 and the junction J5 is a semiconductor in which the n-type impurity concentration of the first and second n-type semiconductor regions 16 and 18 among the semiconductor regions constituting the first and second diodes forms the junction J2. Since it is higher than the n-type impurity concentration of the n1 region 11 among the regions, it is lower than the breakdown voltage of the junction J2. The breakdown voltage of the first diode is such that the first p-type semiconductor region 15 and the second p-type semiconductor region 17 have substantially the same p-type impurity concentration, and the first n-type semiconductor region 16 and the first p-type semiconductor region 16 have the same breakdown voltage. Since the n-type impurity concentrations of the second n-type semiconductor region 18 and the second n-type semiconductor region 18 are substantially equal, the breakdown voltage of the second diode is substantially equal.
[0034]
Since the n-type impurity concentration of the second n-type semiconductor region 18 is higher than the n-type impurity concentration of the n1 region 11, the second n-type semiconductor region 18 does not go through the third n-type semiconductor region 19. Can substantially contact the n1 region 11 in ohmic contact. However, when the third n-type semiconductor region is provided and the contact resistance between the second n-type semiconductor region 18 and the n1 region 11 is large and the current does not easily flow, the current flows through the third n-type semiconductor region. It can flow between the first and second diodes and the n1 region 11 through the region 19. In the present embodiment, a third n-type semiconductor region 19 is provided to ensure electrical conduction. Details of the operations of the thyristor and the first and second diodes will be described later.
[0035]
Next, details of the configuration of the insulating film 20, the cathode electrode 30, the anode electrode 40, the electrode 50, and the metal film 51 will be described with reference to FIG.
The insulating film 20 is composed of a silicon oxide film or the like, and is formed on the upper surface of the semiconductor substrate 10. An opening 21 is provided in the insulating film 20 so that the p1 region 12 and the n2 region 13 can be connected to the cathode electrode 30. The insulating film 20 is provided with openings 22 and 23 so that the first n-type semiconductor region 16 and the second p-type semiconductor region 17 can be connected to the electrode 50. Furthermore, an opening 24 is provided in the insulating film 20 so that the second n-type semiconductor region 18 is connected to the metal film 51.
[0036]
The cathode electrode 30 is made of an aluminum film or the like, and is formed on the upper surface of the semiconductor substrate 10 so as to cover the p1 region 12 and the n2 region 13. The cathode electrode 30 is connected to the p1 region 12 and the n2 region 13.
[0037]
The anode electrode 40 is made of an aluminum film or the like, and is formed on the lower surface of the semiconductor substrate 10 so as to cover the p2 region 14. Therefore, the anode electrode 40 is connected to the p2 region 14.
[0038]
The electrode 50 is made of an aluminum film or the like. The electrode 50 is connected to the first n-type semiconductor region 16 and the second p-type semiconductor region 17 through the openings 22 and 23 of the insulating film 20. Accordingly, the electrode 50 is connected to the first diode and the second diode. The electrode 50 is not in contact with the cathode electrode 30.
[0039]
The metal film 51 is made of an aluminum film or the like. The metal film 51 is connected to the second n-type semiconductor region 18 through the opening 24 of the insulating film 20. The metal film 51 stabilizes the surface potential of the second n-type semiconductor region 18. The metal film 51 is not in contact with the cathode electrode 30 and the electrode 50.
[0040]
Next, a procedure for manufacturing the composite semiconductor element having the above configuration will be described with reference to FIGS. 4 (a) to 8 (o). The procedure shown below is an example, and any procedure may be used as long as a similar structure can be obtained.
First, a semiconductor substrate 10 made of an n-type semiconductor substrate is prepared. Next, a p-type impurity is implanted into the lower surface of the semiconductor substrate 10 by ion implantation or the like to form a p-type semiconductor region (that is, the p2 region 14) as shown in FIG.
[0041]
Next, as shown in FIG. 4B, a photoresist 60 is formed on the upper surface of the semiconductor substrate 10 other than on the region where the first p-type semiconductor region 15 is to be formed and on the region where the second p-type semiconductor region 17 is to be formed. Form. Subsequently, p-type impurities are implanted into the n1 region 11 by ion implantation or the like, and p-type semiconductor regions (first p-type semiconductor region 15 and second p-type semiconductor region 17) having the same impurity concentration are shown in FIG. 4 (c).
[0042]
Next, the photoresist 60 is peeled off. Following the removal of the photoresist 60, as shown in FIG. 5D, the semiconductor substrate 10 other than the region on the first n-type semiconductor region 16 formation region and the region on which the second n-type semiconductor region 18 is to be formed is formed. A photoresist 61 is formed on the upper surface.
[0043]
Subsequently, an n-type impurity is implanted into the first p-type semiconductor region 15 by ion implantation or the like to form an n-type semiconductor region (first n-type semiconductor region 16) as shown in FIG. To do. Similarly, an n-type impurity is implanted into the second p-type semiconductor region 17 by ion implantation or the like, and an n-type semiconductor region (second n-type impurity concentration is almost equal to that of the first n-type semiconductor region 16). A type semiconductor region 18) is formed as shown in FIG.
[0044]
After the first and second n-type semiconductor regions 16 and 18 are formed, the photoresist 61 is peeled off. Next, as shown in FIG. 5F, a photoresist 62 is formed on the upper surface of the semiconductor substrate 10 other than the region on which the third n-type semiconductor region 19 is to be formed. Then, n-type impurities are implanted into the second n-type semiconductor region 18 and the n1 region 11 by ion implantation or the like to form a third n-type semiconductor region 19 as shown in FIG.
[0045]
After the third n-type semiconductor region 19 is formed, the photoresist 62 is removed. Next, as shown in FIG. 6H, a photoresist 63 is formed on the upper surface of the semiconductor substrate 10 other than the region where the p1 region 12 is to be formed. Using the photoresist 63 as a mask, p-type impurities are implanted into the first p-type semiconductor region 15 and the n1 region 11 by ion implantation or the like, and as shown in FIG. 6I, the p-type semiconductor region (p1 Region 12) is formed.
[0046]
The photoresist 63 is peeled off, and then a photoresist 64 is formed on the upper surface of the semiconductor substrate 10 other than the region where the n2 region 13 is to be formed, as shown in FIG. Next, an n-type impurity is implanted into the p1 region 12 by ion implantation or the like to form an n-type semiconductor region (n2 region 13) as shown in FIG. After forming the n2 region 13, the photoresist 64 is peeled off, and the semiconductor substrate 10 is annealed to activate the ion-implanted p-type and n-type impurities.
[0047]
Next, a silicon oxide film 65 is formed on the upper surface of the semiconductor substrate 10 by CVD (Chemical Vapor Deposition) or the like as shown in FIG. The silicon oxide film 65 is etched to provide openings 21, 22, 23, and 24 as shown in FIG.
[0048]
Subsequently, an aluminum film or the like is formed on the upper surface of the semiconductor substrate 10 by PVD (Physical Vapor Deposition) or the like. The aluminum film is patterned to form a cathode electrode 30, an electrode 50, and a metal film 51 as shown in FIG. Cathode electrode 30 is electrically connected to p1 region 12 and n2 region 13 through opening 21. The electrode 50 is connected to the first n-type semiconductor region 16 through the opening 22 and is connected to the second p-type semiconductor region 17 through the opening 23. The metal film 51 is connected to the second n-type semiconductor region 18 through the opening 24.
[0049]
Then, the anode electrode 40 connected to the p2 region 14 is formed on the other surface of the semiconductor substrate 10 by PVD or the like, as shown in FIG.
[0050]
Next, the operation of the composite semiconductor element described above will be described.
When a positive voltage is applied to the anode electrode 40 and a negative voltage (forward voltage) is applied to the cathode electrode 30, the junctions J1 and J3 are in a forward bias state, and the junctions J2, J4, and J5 are in a reverse bias state.
[0051]
When the applied voltage exceeds a predetermined value, a breakdown phenomenon occurs in the junctions J4 and J5 whose breakdown voltage is lower than the breakdown voltage of the junction J2, and electrons are injected from the cathode electrode 30 into the first and second diodes. The The injected electrons are injected into the n1 region 11 through the third n-type semiconductor region 19 and further injected into the p2 region 14.
[0052]
By injecting electrons into the p2 region 14, holes are injected from the p2 region 14 into the n1 region 11. The injected holes are further injected into the second diode and the first diode through the third n-type semiconductor region 19. Accordingly, a reverse current flows through the first and second diodes. This reverse current flows into the p1 region 12. This reverse current causes a voltage drop due to the lateral resistance of the p1 region 12 (layer resistance in the XX direction in FIG. 1), thereby biasing the junction J2 forward and turning on the thyristor. Therefore, the composite semiconductor element is turned on.
[0053]
As described above, in the composite semiconductor element of this embodiment, a plurality of diodes are connected in series so that the flow directions of reverse currents flowing due to breakdown coincide with each other, and the reverse current flowing due to breakdown of the plurality of diodes is reduced. Used as a trigger to turn on the thyristor.
[0054]
Generally, the higher the impurity concentration in the semiconductor region constituting the diode, the lower the breakdown voltage of the diode. However, the difference in breakdown voltage for each diode tends to fall within an allowable range during manufacturing (variation is small). On the other hand, the lower the impurity concentration, the higher the breakdown voltage of the diode, but the difference in breakdown voltage for each diode tends to exceed the allowable range during manufacturing (large variation).
In this composite semiconductor element, a plurality of diodes having a small variation in manufacturing and a low breakdown voltage are connected in series so that the thyristor is turned on at a desired voltage. By appropriately increasing the number of connected diodes, the thyristor can be turned on at a desired high voltage. The current that flows in each diode due to breakdown may be a small current that is less than the allowable limit of each diode, and each diode is unlikely to be destroyed by heat generated by a reverse current. Further, since the plurality of diodes break down with substantially the same breakdown voltage, the control of the plurality of diodes is easy.
[0055]
Normally, when the voltage at which the thyristor is turned on (trigger voltage) is set to 250 V or higher, the variation in trigger voltage for each composite semiconductor element to be manufactured tends to exceed the allowable range. However, by adopting the configuration as described above, even if the trigger voltage is set to 250 V or more, this composite semiconductor element has a variation in trigger voltage within an allowable range for each composite semiconductor element to be manufactured. Cheap.
[0056]
In addition, this invention is not limited to the said embodiment, A various application and change are possible.
For example, a bidirectional thyristor may be used instead of the reverse blocking thyristor. In this case, a structure as shown in FIG. That is, in addition to the basic structure of FIG. 3A, a plurality of diodes connected to the n1 region 11 and the p2 region 14 are further provided. At this time, a plurality of diodes are connected in series so that the directions of currents flowing due to breakdown coincide with each other.
[0057]
Moreover, in the said embodiment, the case where the n2 area | region 13 was formed in island shape was demonstrated as an example. However, the shape of the n2 region 13 is not limited to this, and may be formed in a band shape, for example. In this case, the shape of the other semiconductor region surrounding the n2 region 13 such as the p1 region 12 is appropriately changed according to the shape of the n2 region 13.
[0058]
Furthermore, in the above-described embodiment, the first p-type semiconductor region is electrically connected to the p1 region 12 by directly contacting the p1 region 12. However, as shown in FIG. 9B, the first p-type semiconductor region 15 may be connected to the p1 region 12 via the cathode electrode 30. In this case, as shown in the drawing, an opening 25 is provided in the insulating film 20 so that the first p-type semiconductor region 15 is in contact with the cathode electrode 30.
[0059]
Alternatively, in the above embodiment, the case where two diodes are connected in series has been described as an example. However, three or more diodes may be connected in series in order to set the trigger voltage to a desired value.
[0060]
【The invention's effect】
As described above, an object of the present invention is to provide a composite semiconductor device that can easily set a turn-on voltage to a desired value.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a composite semiconductor element according to an embodiment of the present invention.
FIG. 2 is a plan view showing a part of the upper surface of the composite semiconductor element of FIG. 1;
FIGS. 3A and 3B are diagrams showing a basic structure and an equivalent circuit of the composite semiconductor element of FIG. 1, respectively.
4 (a) to 4 (c) are cross-sectional views for explaining a manufacturing process of the composite semiconductor element of FIG.
FIGS. 5D to 5F are cross-sectional views for explaining a manufacturing process of the composite semiconductor element of FIG.
6 (g) to 6 (i) are cross-sectional views for explaining a manufacturing process of the composite semiconductor element of FIG.
7 (j) to 7 (l) are cross-sectional views for explaining a manufacturing process of the composite semiconductor element of FIG.
8 (m) to 8 (o) are cross-sectional views for explaining a manufacturing process of the composite semiconductor element of FIG.
9 (a) and 9 (b) are cross-sectional views showing a modification of the composite semiconductor element according to the embodiment of the present invention.
[Explanation of symbols]
10 Semiconductor substrate
11 n1 region
12 p1 region
13 n2 region
14 p2 region
15 First p-type semiconductor region
16 First n-type semiconductor region
17 Second p-type semiconductor region
18 Second n-type semiconductor region
19 Third n-type semiconductor region
20 Insulating film
30 Cathode electrode
40 Anode electrode
50 electrodes
51 Metal film

Claims

A first conductivity type first semiconductor region; a second conductivity type second semiconductor region in contact with the first semiconductor region; a first conductivity type third semiconductor region in contact with the second semiconductor region; A thyristor including a fourth semiconductor region of a second conductivity type in contact with the third semiconductor region;
It consists of a plurality of diodes connected to each other so that the flow directions of the currents that flow due to breakdown match each other, and from the second semiconductor region to the third semiconductor region or from the third semiconductor region to the second A series circuit connected to the second semiconductor region and the third semiconductor region so that the current flows through the semiconductor region;
A composite semiconductor element comprising:

The thyristor further includes a first electrode connected to the first semiconductor region and a second electrode connected to the fourth semiconductor region,
Each said diode is a Zener diode,
When a voltage is applied between the first electrode and the second electrode, the junction between the second semiconductor region and the third semiconductor region and the junction of each diode are reverse biased. And
When the voltage exceeds a predetermined level, each diode breaks down and a current flows, and the thyristor is triggered by a current flowing through each diode due to breakdown, and the current is generated in the second semiconductor region or the third semiconductor layer. The junction between the second semiconductor region and the third semiconductor region is forward-biased and turned on.
The composite semiconductor device according to claim 1, wherein:

3. The composite semiconductor device according to claim 1, wherein each of the diodes breaks down with a substantially equal breakdown voltage.

A first conductive type first semiconductor region having an upper surface and a lower surface; a second conductive type second semiconductor region formed in a surface region of the lower surface of the first semiconductor region; and the first semiconductor region A thyristor comprising a second conductivity type third semiconductor region formed in the surface region of the upper surface of the first semiconductor region and a first conductivity type fourth semiconductor region formed in the surface region of the third semiconductor region. When,
A fifth semiconductor region of a second conductivity type formed in a surface region on the upper surface of the first semiconductor region and electrically connected to the third semiconductor region so as to surround the third semiconductor region; A first diode composed of a sixth semiconductor region of the first conductivity type formed in a surface region of the fifth semiconductor region;
In a surface region on the upper surface of the first semiconductor region, a seventh semiconductor region of a second conductivity type formed so as to surround the fifth semiconductor region, and on a surface region on the upper surface of the first semiconductor region A second diode composed of an eighth semiconductor region of the first conductivity type formed so as to be in contact with the seventh semiconductor region;
An electrode connected to the sixth semiconductor region and the seventh semiconductor region so as to connect the first diode and the second diode in series with each other;
A composite semiconductor element comprising:

The thyristor further includes an anode electrode connected to the first semiconductor region, and a cathode electrode connected to the fourth semiconductor region,
The first and second diodes are zener diodes,
A junction formed by the second semiconductor region and the third semiconductor region by applying a voltage between the anode electrode and the cathode electrode, and a junction possessed by each of the first and second diodes Is reverse biased,
When the voltage exceeds a predetermined level, the first and second diodes break down and a current flows, and the thyristor is triggered by a current flowing through the first diode and the second diode due to breakdown, When a current flows into the second semiconductor region or the third semiconductor region, the junction between the second semiconductor region and the third semiconductor region is forward biased and turned on.
5. The composite semiconductor element according to claim 4, wherein

A ninth semiconductor formed on the surface region of the upper surface of the first semiconductor region so as to be in contact with the eighth semiconductor region at a higher impurity concentration of the first conductivity type than the first and eighth semiconductor regions; Further comprising an area,
6. The composite semiconductor element according to claim 4, wherein the eighth semiconductor region is in ohmic contact with the first semiconductor region via the ninth semiconductor region.

7. The composite semiconductor device according to claim 4, wherein the first and second diodes break down at substantially the same breakdown voltage. 8.

A second semiconductor region is formed by diffusing a second conductivity type impurity in a surface region of the lower surface of the first conductivity type first semiconductor region having an upper surface and a lower surface, and an upper surface of the first semiconductor region is formed. A third semiconductor region is formed by diffusing a second conductivity type impurity in the surface region, and a fourth semiconductor region is formed by diffusing the first conductivity type impurity in the surface region of the third semiconductor region. Forming a thyristor; and
A fifth semiconductor electrically connected to the third semiconductor region by diffusing a second conductivity type impurity in the surface region of the upper surface of the first semiconductor so as to surround the third semiconductor region. Forming a first semiconductor diode by forming a sixth semiconductor region by forming a region and diffusing impurities of a first conductivity type in a surface region of the fifth semiconductor region;
A seventh semiconductor region is formed on the upper surface of the first semiconductor region by diffusing impurities of the second conductivity type so as to surround the fifth semiconductor region, and the first semiconductor region is formed on the upper surface of the first semiconductor region. Forming a second diode by forming an eighth semiconductor region in contact with the seventh semiconductor region by diffusing conductive impurities;
Forming a conductor for connecting the first and second diodes in series by being connected to the sixth semiconductor region and the seventh semiconductor region on the upper surface of the first semiconductor substrate; ,
A method for manufacturing a composite semiconductor element, comprising:

In the step of forming the first diode and the second diode,
Forming the fifth semiconductor region with an impurity concentration substantially equal to the seventh semiconductor region and lower than the impurity concentration of the fourth semiconductor region;
9. The composite semiconductor device according to claim 8, wherein the sixth semiconductor region is formed with an impurity concentration substantially equal to the eighth semiconductor region and lower than the fourth impurity concentration. Method.