JPH0543530Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Field of Application) The present invention relates to an amplifier circuit that uses field-effect transistors and is suitable for use in monolithic ICs with a wide band and low noise.

(Prior Art) FIG. 5 shows an example of a typical circuit of a negative feedback type broadband amplifier.

In the figure, 1 is a gallium arsenide field effect transistor (GaAs MES FET, hereinafter referred to as FET),
Generally, a pinch-off voltage of about 2.5V from OV is used, and its gate, drain, and source terminals are constituted by terminals 2, 3, and 4, respectively, and 5 is a negative feedback FET, whose gate is connected to terminal 6. Also, the drain and source are connected to terminals 3 and 4,
7 is a load FET whose gate and drain are connected to terminals 8 and 9, respectively, and whose source is connected to terminal 3. 10 is for buffer circuit input
FET, gate and drain are each terminal 3
and 9, and the source is connected to terminal 11, 1
2 is a constant current source FET for the buffer circuit, and its gate and source are connected to terminals 13 and 14, and its drain is connected to terminal 6. 15 and 16 are shot key gate diodes for level shifting, and terminal 11 is connected to its positive terminal. , terminal 6 constitutes its negative terminal, 17 is a matching resistor for setting gate bias and matching input impedance, 18, 19,
20 and 21 are power supply terminals for supplying voltage to the circuit, 22 is grounding, 23 is a high frequency signal source,
24 is an internal resistance of the high frequency signal source 23, 25 is an input coupling capacitor, 26 is an output stage FET whose gate is connected to terminal 6, the drain and source terminals are constituted by terminals 27 and 28, and 29 is an output stage FET. Load resistors 30 and 50 of the FE 26 are power supply terminals for the output stage.

In the conventional negative feedback type wideband amplifier having such a configuration, the input impedance is matched, and
In order to set the potential of the gate of FET 1, a matching resistor 17 is provided to set the gate bias and match the input impedance. This has the drawback of causing noise to be generated, which deteriorates the noise figure of the circuit.

On the other hand, FIGS. 6 and 7 show circuit diagrams of conventional negative feedback type broadband amplifiers. Figure 6 is JP-A-57-
A circuit considered from Publication No. 194613 and FIG. 7 is a circuit considered from Publication of Utility Model Publication No. 47-23944.
In the figure, Q ₁₁ and Q ₄₁ are bipolar transistors, and R ₂ and R ₃ are resistors. 10 is an input FET for the buffer circuit, the gate and drain are connected to terminals 3 and 9, respectively, and the source is connected to terminal 1.
1, 12 is a constant current source FET for the buffer circuit, its gate and source are connected to terminals 13 and 14, and its drain is connected to terminal 6. 15 and 16 are level shift shot key gate diodes connected to terminal 11. constitutes its positive terminal, terminal 6 constitutes its negative terminal, and 18, 20, and 21 are power supply terminals for supplying voltage to the circuit, respectively.

In the circuit shown in FIG. 6, since the bipolar transistor _Q41 is used in the feedback circuit, the entire circuit has large noise. Also, the input transistor
Since a bipolar transistor is used as Q ₁₁ , a base current flows during operation, so if the amount of feedback of transistor Q ₄ or Q ₄₁ is changed, the base potential of input transistor Q ₁₁ will fluctuate (at the gate of the FET). (This kind of fluctuation does not occur because almost no current flows in the circuit), but with a constant power supply voltage, the fundamental drawback is that the circuit characteristics are unstable. In Japanese Utility Model Publication No. 47-23944, in order to control this fluctuation, resistors R ₂ and R ₃ are used to stabilize the base potential as shown in FIG. 7. However, although such a resistor may stabilize the circuit, it significantly increases the noise of the circuit.

(Problems to be solved by the invention) Conventionally, the following problems were achieved: 1. wide band, 2. variable gain, 3. low noise, and 4. circuit operation even if the amount of feedback is changed at a constant power supply voltage. There has never been a negative feedback wideband amplifier that satisfies all the requirements of stability.

(Means for Solving the Problems) The present invention achieves the following by applying negative feedback using a resistor directly connected to the output stage and input stage, and using an FET for the input transistor and an FET for the feedback resistor. 2. Variable gain, 3. Low noise, and 4. Stable circuit operation even if the amount of feedback is changed at a constant power supply voltage. It is characterized by:

(Embodiment) FIG. 1 shows the circuit configuration of an embodiment of the field effect transistor amplifier of the present invention, in which 31 is a load resistor, 32 is a feedback resistor, 33 is a buffer circuit circuit element, and other symbols are used. is the same as that explained in FIG. Here, the circuit element 33 of the buffer circuit is constituted by an FET 34 as shown in FIG. 2a, and its drain terminal 36 is connected to the terminal 6.
Further, the gate terminal 35 and the source terminal 37 are connected to the voltage supply terminal 21.

According to the amplifier of the present invention configured in this way,
The matching resistor 17 and the gate bias voltage supply terminal 19 shown in Fig. 5 for setting the gate bias and matching the input impedance are no longer necessary, and the DC power supply is simple and requires one less than the conventional circuit shown in Fig. 5. The structure is as follows.

Figure 2b shows the element configuration when the feedback resistor 32 is replaced with an FET, where 38 is an FET;
9 is its gate terminal, 40 and 41 are drain and source terminals (or source and drain terminals), respectively, and 42 is a voltage terminal for adjusting the resistance value of the FET 38. This takes advantage of the fact that the resistance between the drain and source of the FET38 (FET resistance) can be changed by the gate bias voltage.If you do this, you can use the FET resistance to control the feedback resistance value with the gate voltage. The input impedance, output impedance,
Gain and bandwidth can also be controlled.

FIG. 3 shows an embodiment of the amplifier of the present invention shown in FIG. 1, with a gate length of 1 μm, a gate width of 150 μm,
Pinch-off voltage 1V, transconductance approx.
This is a characteristic diagram showing the conditions for 50Ω input impedance matching when using a 160mS/mm FET, terminals 18 and 50 are grounded, -4V is applied to terminals 20 and 30, and -6V is applied to terminal 21. can be,
The horizontal axis is the negative feedback resistance value R _f (Ω), and the vertical axis is the load resistance value
In Rl, 43 is a curve under which matching can be achieved.
Also, 44 and 45 are voltage gains under those conditions.
Gain (dB) and cutoff frequency c (GHz) (frequency at which the gain drops by 3 dB) are shown. According to these, the gain can be adjusted by changing the negative feedback resistance value R _f , and the cutoff frequency also changes accordingly, but in either case it is a large value of several GHz.

Figure 4 shows the change in frequency characteristics when only the gate length is changed in one embodiment of the present invention, where the horizontal axis is the frequency (GHz) and the vertical axis is the gain.
Gain (dB), curves 46, 47, 48 and 49 show the frequency characteristics when the gate lengths are 2.0, 1.4, 0.8 and 0.6 μm, respectively. According to this, as the gate length is shortened, the cutoff frequency increases.
It is possible to create an amplifier with a gain of 12dB above 10GHz.

Next, to explain the noise characteristics, in the conventional circuit shown in Fig. 5, the gate bias is set,
Although it was necessary to provide a matching resistor 17 to match the input impedance, the noise generated by this resistor degraded the noise figure of the circuit within a range of 3 to 6 dB. However, according to the present invention shown in Figure 1,
The noise generated by the feedback resistor 32 is reduced by negative feedback, and the effective noise contribution can be reduced, and the gate bias can be set to match the input impedance. Also, generally
The noise current generated by a FET is larger than the noise current generated by a resistor with a value that can be equivalently replaced, so using a resistor as a load can improve the noise figure.

According to the actual measurement results, the gate widths of FETs 1, 10, and 12 in the conventional circuit shown in Figure 5 are
The noise figure is 8.7dB at 1GHz when the gate width of negative feedback FET5 is 20μm, the gate width of load FET7 is 165μm, the gate length of each FET is 1μm, and the pinch-off voltage is 1V. In the circuit of the present invention shown in Figure 1, the gate width of each FET is 150 μm, the gate length is 1 μm, and the pinch-off voltage is
The noise figure was 4.4dB at 1GHz when the voltage was 1V and the feedback and load resistance values were 250Ω.

Although the structure and operation of one embodiment of the present invention have been described above, various modifications may be made in addition to this. That is, an FET can be used as the load instead of a resistor. It is also possible to operate by using the level shift diodes 15 and 16 between the gate and source or between the gate and drain of the FET. Furthermore, the circuit element 33 of the buffer circuit can operate even with a resistor having a larger value than the feedback resistor 32. In addition, voltage supply terminals 20 and 21
are provided individually, but if a diode is inserted between the source terminal 4 of the FET 1 and the voltage supply terminal 20, the voltage drop can be used to make the power supply voltage common.

In any of the above cases, as an FET,
Not only GaAs, but also Si, Inp, GaAs/A1 GaAs and
Two-dimensional electron gas crystals such as InGaAS/InA1As,
InAa etc. can also be used. Further, each element parameter of the FET, the resistance value, the number of level shift diodes, the value of the power supply voltage, etc. can be arbitrarily defined according to the performance and in accordance with the gist of the present invention. Furthermore, although the above description has been made regarding the case of a wideband amplifier, the present invention has the characteristics of a particularly low-noise amplifier circuit, so it can be applied to other analog amplifiers.
The same can be applied to ICs.

(Effects of the Invention) As described above, according to the present invention, when a feedback resistor is used, it is possible to obtain sufficiently wide band characteristics compared to conventional circuits and to realize an amplifier with low noise. In addition, by using a level shift diode, the input and output levels can be made the same, making it possible to connect amplifiers in multiple stages or place this circuit at any position in other circuits without using an extra matching circuit. can be inserted. In addition, by realizing the feedback resistance with a field effect transistor, the feedback resistance value can be changed by the control voltage applied to the gate of the field effect transistor, making it possible to freely change the gain and band with the same circuit. It has the advantage that a low-noise amplifier can be realized and the circuit operation is stable even if the amount of feedback is changed at a constant power supply voltage. Furthermore, by inserting a level shift diode between the first field effect transistor and the second power supply, the second and third power supplies can be shared, which also has the advantage of reducing the number of power supplies by one. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of one embodiment of the field effect transistor amplifier of the present invention, FIG. 2 is a diagram showing an example of the circuit elements and feedback resistor of the buffer circuit used in FIG. 1, and FIG. Figure 4 is a diagram for devising the characteristics of the amplifier of the present invention, Figure 5 is a diagram showing an example of the circuit configuration of a conventional negative feedback wideband amplifier, and Figures 6 and 7 are diagrams showing conventional examples. It is a circuit diagram. 1, 34, 38...FET, 5...For negative feedback
FET, 7... FET for load, 10... FET for input of buffer circuit, 12... FET for constant current source of buffer circuit, 15, 16... Schottky gate diode for level shift, 17... Matching resistor , 18, 19, 20, 21...Power terminal, 2
2...Grounding, 23...High frequency signal source, 24...2
3 internal resistance, 25...input coupling capacitor,
26... Output stage FET, 29... Output stage load resistance, 30, 50... Output stage power supply terminal, 31...
Load resistance, 32...Feedback resistance, 33...Buffer retreat circuit element, 42...Voltage terminal.

Claims (1)

[Claims for Utility Model Registration] (1) The first field effect transistor has an input applied to its gate, a drain connected to a first power supply terminal via a load resistor, and a source connected to a second power supply terminal. connected, the second field effect transistor has a gate connected to the drain of the first field effect transistor, a source connected to one terminal of a diode, a drain connected to the first power supply terminal, and a second field effect transistor connected to the first field effect transistor. A third field effect transistor has a drain connected to the other terminal of the diode, a gate and a source connected to a third power supply terminal, and a fourth field effect transistor has a drain connected to the third power supply terminal. , provided between the gate of the first field effect transistor, one of the source and drain of the fourth field effect transistor is connected to the gate of the first field effect transistor, and the other is connected to the gate of the third field effect transistor. A feedback resistor is connected to each drain of the transistor, a control voltage is applied to the gate, and a bias voltage is applied between the first and second power supply terminals and between the first and third power supply terminals. A field effect transistor amplifier characterized in that the drain terminal of the third field effect transistor is used as an output. (2) The load resistor connected between the drain of the first field effect transistor and the first power supply terminal is constituted by a fifth field effect transistor, and the drain of the fifth field effect transistor 2. The field effect transistor amplifier according to claim 1, wherein the field effect transistor amplifier is connected to the first power supply terminal, and the gate and source are connected to the drain of the first field effect transistor. (3) Claims for registration of a utility model characterized in that, in place of the third field effect transistor, a resistor with a resistance value greater than the resistance value of the feedback resistor is provided between the diode and the third power supply terminal. 2. The field effect transistor amplifier according to claim 1. (4) Registration of a utility model characterized in that a diode is connected between the source of the first field effect transistor and the second power supply terminal, and a common connection is made between the second and third power supply terminals. A field effect transistor amplifier according to claim 1.