JPH0543515Y2 - - Google Patents

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Publication number
JPH0543515Y2
JPH0543515Y2 JP6748889U JP6748889U JPH0543515Y2 JP H0543515 Y2 JPH0543515 Y2 JP H0543515Y2 JP 6748889 U JP6748889 U JP 6748889U JP 6748889 U JP6748889 U JP 6748889U JP H0543515 Y2 JPH0543515 Y2 JP H0543515Y2
Authority
JP
Japan
Prior art keywords
hybrid integrated
integrated circuit
circuit
core
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6748889U
Other languages
Japanese (ja)
Other versions
JPH0254297U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6748889U priority Critical patent/JPH0543515Y2/ja
Publication of JPH0254297U publication Critical patent/JPH0254297U/ja
Application granted granted Critical
Publication of JPH0543515Y2 publication Critical patent/JPH0543515Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【考案の詳細な説明】 (イ) 産業上の利用分野 本考案はスイツチング回路を組込んだ混成集積
回路装置、特にスイツチング回路より発生するノ
イズを抑圧する混成集積回路装置に関する。
[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a hybrid integrated circuit device incorporating a switching circuit, and particularly to a hybrid integrated circuit device that suppresses noise generated by the switching circuit.

(ロ) 従来の技術 スイツチングレギユレータは効率よく、小型軽
量の電源回路を実現できるため、各種の電子機器
に盛んに組込まれている。ところが高電圧・大電
流のスイツチング動作であるために電源回路から
ノイズを発生する問題がある。
(b) Conventional technology Switching regulators are widely incorporated into various electronic devices because they can efficiently realize compact and lightweight power supply circuits. However, since the switching operation uses high voltage and large current, there is a problem in that noise is generated from the power supply circuit.

斯るノイズを低減するために例えば特開昭57−
49369号公報(HO2M 3/28)に示す如く、ス
イツチング周波数成分の電圧がノイズとしてAC
電源に伝導するのを防止している。即ちスイツチ
ングトランジスタの取付金具をスイツチング周波
数でのインピーダンスが低い電線で平滑コンデン
サの一端子に接続している。
For example, in order to reduce such noise,
As shown in Publication No. 49369 (HO2M 3/28), the voltage of the switching frequency component is
Prevents conduction to the power supply. That is, the mounting bracket of the switching transistor is connected to one terminal of the smoothing capacitor with a wire having low impedance at the switching frequency.

しかし斯上の如くデイスクリート素子で電源回
路を構成する場合には、部品がプリント基板上あ
るいは放熱板上に分散されて配置されるので効果
的なノイズ対策は望めない。
However, when a power supply circuit is constructed using discrete elements as described above, effective noise countermeasures cannot be expected because the components are distributed and arranged on a printed circuit board or a heat sink.

(ハ) 考案が解決しようとする課題 本考案は斯点に鑑みてなされ、スイツチング回
路より発生するノイズを抑圧する混成集積回路装
置を実現することにある。
(c) Problems to be Solved by the Invention The present invention has been made in view of this point, and its object is to realize a hybrid integrated circuit device that suppresses the noise generated by the switching circuit.

(ニ) 課題を解決するための手段 本考案に依るスイツチング回路を組込んだ混成
集積回路装置は、表面を絶縁処理した良熱伝導性
金属基板と基板上に形成した所望のスイツチング
回路とスイツチング回路と外部回路との接続をす
る外部リードとを備え、外部リードの少なくとも
スイツチング周波数の印加される外部リードに磁
性体より成るコアを取付けて構成される。
(d) Means for Solving the Problems A hybrid integrated circuit device incorporating a switching circuit according to the present invention consists of a highly thermally conductive metal substrate whose surface is insulated, a desired switching circuit formed on the substrate, and a switching circuit. and an external lead for connection with an external circuit, and a core made of a magnetic material is attached to at least the external lead to which the switching frequency is applied.

(ホ) 実施例 本考案に用いる混成集積回路装置は第1図に示
す如く、アルミニウム等の良熱伝導性金属基板1
上に酸化アルミニウム(Al2O3)薄層2を設け、
この薄膜2上に周知の混成集積回路技術を用いて
所定の導電路3、抵抗体4およびパワートランジ
スタ5等を付着してスイツチングレギユレータの
如きスイツチング回路を形成している。また外部
リード6は金属基板1の一辺に設けられ、外部回
路例えばコンデンサ、入出力端子等との接続を行
う。
(E) Embodiment The hybrid integrated circuit device used in the present invention, as shown in FIG.
a thin layer 2 of aluminum oxide (Al 2 O 3 ) is provided on top;
A predetermined conductive path 3, a resistor 4, a power transistor 5, etc. are attached on this thin film 2 using well-known hybrid integrated circuit technology to form a switching circuit such as a switching regulator. Further, an external lead 6 is provided on one side of the metal substrate 1, and is connected to an external circuit such as a capacitor, an input/output terminal, etc.

本考案の特徴は磁性体より成るコア7にある。
コア7はフエライト粉末を固型化してリング状、
円筒状等に形成し、以下に述べる実施例の如く外
部リード6に取付けられている。
The feature of the present invention lies in the core 7 made of a magnetic material.
The core 7 is made of solidified ferrite powder and has a ring shape.
It is formed into a cylindrical shape or the like and is attached to the external lead 6 as in the embodiment described below.

第3図AおよびBに於いては、円筒状のコア7
を準備し、スイツチング周波数の印加される外部
リード6に選択的に貫通させてノイズの抑圧を行
つている。コア7はモールド樹脂8にその一端を
埋込んで固定されている。
In FIGS. 3A and 3B, the cylindrical core 7
is prepared and selectively penetrated through the external lead 6 to which the switching frequency is applied to suppress noise. The core 7 is fixed with one end embedded in a molded resin 8.

第4図AおよびBに於いては外部リード6の形
状に対応した凹凸状の半割れ合わせ形状のコア
7,7′を準備し、外部リード6を凹部に貫通さ
せて閉磁路を形成している。このコア7,7′で
は全ての外部リード6を囲み、コア7,7′はモ
ールド樹脂8にその一端を埋込んで固定する。
In FIGS. 4A and 4B, cores 7 and 7' having an uneven half-split shape corresponding to the shape of the external lead 6 are prepared, and the external lead 6 is passed through the recess to form a closed magnetic circuit. There is. The cores 7, 7' surround all the external leads 6, and one end of the cores 7, 7' is embedded in a molded resin 8 and fixed.

第5図Aに於いては上記した半割れ合わせ形状
のものを一体に形成したコア7を用いている。
In FIG. 5A, a core 7 which is integrally formed with the above-mentioned half-split shape is used.

第6図AおよびBに於いてはループ状のコア7
を準備し、ループ内に全ての外部リード6を配置
し、コア7はモールド樹脂8にその一端を埋込ん
で固定する。
In FIGS. 6A and B, the loop-shaped core 7
All the external leads 6 are arranged in the loop, and one end of the core 7 is embedded in the molded resin 8 and fixed.

斯上した混成集積回路装置は第2図に示す如
く、シヤーシ等で形成されるアルミシールドボツ
クス9内に絶縁フイルム10を介して取付けられ
るので、金属基板1が静電シールドとして働きノ
イズ抑圧に対して極めて有用な構造となる。更に
外部リード6にはコア7を設けているのでノイズ
発生源に最も近い所でノイズの抑圧をでき、極め
てノイズレベルを小さく押えることができる。
As shown in FIG. 2, the hybrid integrated circuit device described above is installed in an aluminum shield box 9 made of a chassis or the like via an insulating film 10, so that the metal substrate 1 acts as an electrostatic shield and suppresses noise. This makes it an extremely useful structure. Furthermore, since the external lead 6 is provided with the core 7, noise can be suppressed at the location closest to the noise source, making it possible to keep the noise level extremely low.

(ヘ) 考案の効果 本考案に依れば金属基板1およびコア7により
極めて簡単な構造でノイズを有効に抑圧できる有
用なものである。またノイズレベルの抑圧により
スイツチング回路を組込んだ混成集積回路装置を
電子機器に積極的に組込みできる様になり、電子
機器の小型軽量化に寄与できる。
(f) Effects of the invention According to the invention, the metal substrate 1 and the core 7 are used to effectively suppress noise with an extremely simple structure. Furthermore, by suppressing the noise level, it becomes possible to actively incorporate a hybrid integrated circuit device incorporating a switching circuit into electronic equipment, contributing to the reduction in size and weight of electronic equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の混成集積回路装置を説明する
断面図、第2図は本考案の混成集積回路装置の電
子機器への取付け構造を説明する側面図、第3図
A、第3図B、第4図A、第4図B、第5図A、
第6図Aおよび第6図Bは本考案の混成集積回路
装置のコアを説明する側面図および断面図であ
る。 主な図番の説明、1は金属基板、6は外部リー
ド、7はコアである。
Fig. 1 is a cross-sectional view illustrating the hybrid integrated circuit device of the present invention, Fig. 2 is a side view illustrating the mounting structure of the hybrid integrated circuit device of the present invention to electronic equipment, Fig. 3A, Fig. 3B , Figure 4A, Figure 4B, Figure 5A,
FIGS. 6A and 6B are a side view and a cross-sectional view illustrating the core of the hybrid integrated circuit device of the present invention. Explanation of main figure numbers: 1 is a metal substrate, 6 is an external lead, and 7 is a core.

Claims (1)

【実用新案登録請求の範囲】 表面を絶縁処理した良熱伝導性金属基板と 該基板上に形成した所望のスイツチング回路と 該回路と外部回路との接続をする外部リードと モールド樹脂にその一端が埋込んで固定され全
ての前記外部リードを囲む様に配置されたループ
状の磁性体より成るコアを備えた混成集積回路に
おいて、 前記混成集積回路はアルミシールドボツクス内
に配置された絶縁フイルムを介して取付けられて
いることを特徴とするスイツチング回路を組込ん
だ混成集積回路装置。
[Scope of claim for utility model registration] A metal substrate with good thermal conductivity whose surface is insulated, a desired switching circuit formed on the substrate, an external lead for connecting the circuit to an external circuit, and one end of which is attached to a molded resin. In a hybrid integrated circuit including a core made of a loop-shaped magnetic material embedded and fixed and arranged so as to surround all the external leads, the hybrid integrated circuit is connected to the core through an insulating film arranged in an aluminum shield box. 1. A hybrid integrated circuit device incorporating a switching circuit, characterized in that the switching circuit is installed in the device.
JP6748889U 1989-06-09 1989-06-09 Expired - Lifetime JPH0543515Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6748889U JPH0543515Y2 (en) 1989-06-09 1989-06-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6748889U JPH0543515Y2 (en) 1989-06-09 1989-06-09

Publications (2)

Publication Number Publication Date
JPH0254297U JPH0254297U (en) 1990-04-19
JPH0543515Y2 true JPH0543515Y2 (en) 1993-11-02

Family

ID=31292860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6748889U Expired - Lifetime JPH0543515Y2 (en) 1989-06-09 1989-06-09

Country Status (1)

Country Link
JP (1) JPH0543515Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1846931A1 (en) * 2005-01-19 2007-10-24 Panduit Corporation Communication channels with suppression cores

Also Published As

Publication number Publication date
JPH0254297U (en) 1990-04-19

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