JPH0543196B2 - - Google Patents

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Publication number
JPH0543196B2
JPH0543196B2 JP59260157A JP26015784A JPH0543196B2 JP H0543196 B2 JPH0543196 B2 JP H0543196B2 JP 59260157 A JP59260157 A JP 59260157A JP 26015784 A JP26015784 A JP 26015784A JP H0543196 B2 JPH0543196 B2 JP H0543196B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor
amorphous
single crystal
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59260157A
Other languages
Japanese (ja)
Other versions
JPS61137373A (en
Inventor
Yasukazu Seki
Noritada Sato
Masaya Yabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP59260157A priority Critical patent/JPS61137373A/en
Publication of JPS61137373A publication Critical patent/JPS61137373A/en
Publication of JPH0543196B2 publication Critical patent/JPH0543196B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/115Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
    • H01L31/118Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation of the surface barrier or shallow PN junction detector type, e.g. surface barrier alpha-particle detectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Measurement Of Radiation (AREA)
  • Light Receiving Elements (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

本発明は、高純度の単結晶半導体基板とその上
の非晶質半導体層との間に形成されるヘテロ接合
を利用した半導体放射線検出器の製造方法に関す
る。
The present invention relates to a method for manufacturing a semiconductor radiation detector using a heterojunction formed between a high-purity single crystal semiconductor substrate and an amorphous semiconductor layer thereon.

【従来の技術】[Conventional technology]

半導体内の空乏層への放射線の入射により生ず
るキヤリアによつて放射線を検出する検出器の空
乏層形成の手段として、例えば高純度単結晶シリ
コン基板とその上に被着された非晶質シリコン膜
との間に形成されるヘテロ結合を利用した半導体
放射線検出器は、既に特開昭59−22716号および
特開昭60−47471号により開示されている。この
検出器は、第2図の構造に示すように単結晶シリ
コン基板1の一表面および側面に非晶質シリコン
層2が被着されており、両面に設けた金属電極3
および4の間に電圧を印加して半導体単結晶1中
に空乏層5を広げ、この空乏層中へ放射線を入射
させ電子一正孔対を生じさせて信号を検出するも
のであつた。
As a means of forming a depletion layer in a detector that detects radiation by carriers generated by the incidence of radiation into a depletion layer in a semiconductor, for example, a high purity single crystal silicon substrate and an amorphous silicon film deposited thereon are used. Semiconductor radiation detectors that utilize the heterojunction formed between the two have already been disclosed in JP-A-59-22716 and JP-A-60-47471. As shown in the structure of FIG. 2, this detector has an amorphous silicon layer 2 deposited on one surface and side surfaces of a single crystal silicon substrate 1, and metal electrodes 3 provided on both surfaces.
and 4 to spread a depletion layer 5 in the semiconductor single crystal 1, radiation is incident into this depletion layer to generate electron-hole pairs, and a signal is detected.

【発明が解決しようとする課題】[Problem to be solved by the invention]

しかし上記のような検出器においては、特にシ
リコン単結晶1および非晶質シリコン層2が高比
抵抗の場合には、金属電極3,4と単結晶シリコ
ンおよびシリコンとの界面に生ずるシヨツトキー
障壁での電圧降下が大きく生ずるため、本来の非
晶質シリコンと単結晶シリコンのヘテロ接合への
印加電圧が十分に印加されず、その結果十分に結
晶シリコン中に空乏層が広がらないという欠点を
有していた。また、そのシヨツトキー障壁部分
が、半導体放射線検出器として信号を取り出す際
にノイズの発生源となるため好ましいものではな
いという欠点も併有していた。 第3図は第2図に示した半導体放射線検出器に
おけるエネルギ分布を示し、下方に第2図に記入
された符号によつて各部の位置を示す。またEF
はフエルミレベルエネルギ、C、Bは、コンダク
シヨンバンド、V、Bはバレンスバンドをそれぞ
れ示す。第3図において金属電極4と単結晶シリ
コン1との接合部21および非晶質シリコン2と
金属電極3との結合部23にシヨツトキー障壁が
生じており、単結晶シリコン1と非晶質シリコン
2との界面にヘテロ接合22が存在する。シヨツ
トキー障壁は半導体と金属との仕事関数のエネル
ギ差に原因するものでこのエネルギ差を小さくす
ることでシヨツトキー障壁を小さくすることが出
来ることは公知の技術である。またこのシヨツト
キー障壁を小さくするために、すなわちオーミツ
ク・コンタクトを形成するために、p型半導体基
体ではp+層を形成しその上に金属電極を形成す
る方法、またはn型半導体基体ではn+層を形成
してその上に金属電極を形成する方法が現在の半
導体プロセスで広く用いられている技術である。
しかし、現在用いられているp+層、n+層形成技
術はすなわち、オーミツク・コンタクト形成技術
は1000℃以上の熱拡散法や、800℃以上の後処理
を必要とするイオン打込法などである。これ等の
方法はいずれも800℃以上の高温プロセスを含ん
でいることから、従来の低抵抗シリコンではほと
んど問題にならないが、高純度シリコン基体を用
いる半導体放射線検出器では適するプロセスでは
ない。その理由は、高純度シリコン基体を高温に
晒すことにより、シリコン基体自身に熱的欠陥を
与え、その結果ライフタイムが減少し素子の電気
的特性を著しく劣化させてしまう欠点があるから
である。 本発明は、上記の点に鑑みてなされたものであ
つて、高純度半導体単結晶の一表面に非晶質半導
体層を被着し、半導体単結晶および非晶質半導体
層のそれぞれの表面に金属電極を有する既出願の
半導体放射線検出器の電極と半導体との界面にシ
ヨツトキー障壁の生ずるのを防止し、しかも単結
晶半導体基板を高温に晒して熱的欠点を生ずるこ
とのない製造方法を提供することを目的とする。
However, in the above-mentioned detector, especially when the silicon single crystal 1 and the amorphous silicon layer 2 have high specific resistance, the Schottky barrier that occurs at the interface between the metal electrodes 3 and 4 and the single crystal silicon and silicon Since a large voltage drop occurs, the voltage applied to the heterojunction between the original amorphous silicon and single crystal silicon is not sufficiently applied, and as a result, the depletion layer does not spread sufficiently into the crystalline silicon. was. Another drawback is that the shot key barrier portion is not desirable because it becomes a source of noise when a signal is extracted as a semiconductor radiation detector. FIG. 3 shows the energy distribution in the semiconductor radiation detector shown in FIG. 2, and the positions of each part are indicated by the symbols written in FIG. 2 below. Also E F
represents Fermi level energy, C and B represent conduction bands, and V and B represent valence bands, respectively. In FIG. 3, Schottky barriers are generated at the joint 21 between the metal electrode 4 and the single crystal silicon 1 and at the joint 23 between the amorphous silicon 2 and the metal electrode 3, and the single crystal silicon 1 and the amorphous silicon 2 A heterojunction 22 exists at the interface. The Schottky barrier is caused by the energy difference between the work functions of a semiconductor and a metal, and it is a known technique that the Schottky barrier can be reduced by reducing this energy difference. In addition, in order to reduce this Schottky barrier, that is, to form an ohmic contact, there is a method of forming a p + layer on a p-type semiconductor substrate and forming a metal electrode thereon, or a method of forming an n + layer on an n-type semiconductor substrate. The method of forming a metal electrode on the metal electrode is a technique widely used in current semiconductor processes.
However, the currently used p + layer and n + layer formation technology, that is, ohmic contact formation technology, uses thermal diffusion methods at temperatures above 1000°C, and ion implantation methods that require post-processing at temperatures above 800°C. be. All of these methods involve high-temperature processes of 800°C or higher, which poses little problem with conventional low-resistance silicon, but they are not suitable processes for semiconductor radiation detectors that use high-purity silicon substrates. The reason for this is that exposing a high-purity silicon substrate to high temperatures causes thermal defects in the silicon substrate itself, resulting in a shortened lifetime and significant deterioration of the electrical characteristics of the device. The present invention has been made in view of the above points, and consists of depositing an amorphous semiconductor layer on one surface of a high-purity semiconductor single crystal, and depositing an amorphous semiconductor layer on each surface of the semiconductor single crystal and the amorphous semiconductor layer. Provided is a manufacturing method that prevents the formation of a Schottky barrier at the interface between the electrode and semiconductor of a previously applied semiconductor radiation detector having a metal electrode, and that does not cause thermal defects by exposing a single crystal semiconductor substrate to high temperatures. The purpose is to

【課題を解決するための手段】[Means to solve the problem]

上記目的を達成するために、本願の第1発明に
おいては、一導電形(例えばp型)の高純度単結
晶半導体基板の一主面に逆導電形(例えば弱いn
型)で高比抵抗の非晶質半導体層を被着し、前記
の一主面に対向する半導体基板の他の主面に不純
物金属、例えばアルミニウム、の膜を形成し、不
活性ガスプラズマ中で他の主面から半導体基板へ
不純物金属を侵入させて半導体基板と同一導電形
で不純物濃度の高い(p+型の)表面層を形成し、
この表面層上に不純物金属(アルミニウム)から
なる電極を設ける、こととする。 また、本願の第2発明においては、一導電形の
(例えばp型の)高純度単結晶半導体基板の一主
面に逆導電形(例えば弱いn型)で高比抵抗の非
晶質半導体層を被着し、この非晶質半導体層上に
不純物金属、例えばアンチモンを含む金、の膜を
形成し、不活性ガスプラズマ中で非晶質半導体層
の表面からこの非晶質半導体層へ不純物金属を侵
入させて非晶質半導体層と同一導電形で不純物濃
度の高い(n+型の)表面層を形成し、この表面
層上に不純物金属(金−アンチモン)からなる電
極を設ける、こととする。
In order to achieve the above object, in the first invention of the present application, one main surface of a high purity single crystal semiconductor substrate of one conductivity type (for example, p-type) is provided with an opposite conductivity type (for example, weak n-type).
An amorphous semiconductor layer with high specific resistance is deposited using a mold), a film of an impurity metal such as aluminum is formed on the other main surface of the semiconductor substrate opposite to the one main surface, and a film of an impurity metal, such as aluminum, is deposited in an inert gas plasma. impurity metal is infiltrated into the semiconductor substrate from the other main surface to form a surface layer with the same conductivity type as the semiconductor substrate and high impurity concentration (p + type),
An electrode made of impurity metal (aluminum) is provided on this surface layer. Further, in the second invention of the present application, an amorphous semiconductor layer of a high specific resistance of an opposite conductivity type (for example, a weak n-type) is formed on one main surface of a high-purity single crystal semiconductor substrate of one conductivity type (for example, a p-type). A film of an impurity metal, such as gold containing antimony, is formed on this amorphous semiconductor layer, and the impurity is transferred from the surface of the amorphous semiconductor layer to this amorphous semiconductor layer in an inert gas plasma. Infiltrating a metal to form a (n + type) surface layer with the same conductivity type as the amorphous semiconductor layer and high impurity concentration, and providing an electrode made of impurity metal (gold-antimony) on this surface layer. shall be.

【作用】[Effect]

第1発明の上記技術手段により、半導体基板に
熱的欠陥を生ずることなく、半導体基板と金属電
極の界面におけるシヨツトキー障壁が低減し、半
導体基板と金属電極の接触がオーム接触に近づ
く。 また第2発明の上記技術手段により、半導体基
板に熱的欠陥を生ずることなく、非晶質半導体層
と金属電極の界面におけるシヨツトキー障壁が低
減し、非晶質半導体層と金属電極の接触がオーム
接触に近づく。
With the above technical means of the first invention, the Schottky barrier at the interface between the semiconductor substrate and the metal electrode is reduced without causing thermal defects in the semiconductor substrate, and the contact between the semiconductor substrate and the metal electrode approaches ohmic contact. Further, by the above technical means of the second invention, the Schottky barrier at the interface between the amorphous semiconductor layer and the metal electrode is reduced without causing thermal defects in the semiconductor substrate, and the contact between the amorphous semiconductor layer and the metal electrode is made ohmic. approach contact.

【実施例】【Example】

第1図a〜eに本願第1発明の実施例の工程の
大部分を示す。第1図aに示す比抵抗10kΩcm以
上でp型の高純度シリコン単結晶基板1の上表面
に公知のプラズマCVD法によりモノシランガス
から弱いn型を示すアンドープ非晶質シリコン層
2を被着させるb。次に非晶質シリコン層2の表
面に金属電極3としてアルミニウムを蒸着する
c。なお、この金属電極3を設ける工程cを後に
第4図により説明する低温プラズマ処理工程の後
にまわして、工程bから以下に記載の工程dに進
んでもよい。次に基板1を上下反転してd、上表
面に0.01〜0.1μmの厚さのアルミニウム膜6を真
空蒸着法で形成するe。このような工程を経た素
子10を第4図に示す装置の反応槽11の中に入
れ、アルミニウム膜6を上にして下部電極板12
の上に載置する。第4図の装置はそのほかに上部
電極板13、直流電圧電源14、排気系15、排
気量調整用バルブ16、真空計17、下部電極板
加熱用ヒータ18、ヒータ用電源19を備え、さ
らに反応槽11に不活性ガスボンベ31が減圧弁
32、ガス流量調節器33、ガス流量計34を介
して接続されている。第4図の装置を用いて次の
条件でプラズマを発生させ、アルミニウム膜6か
らアルミニウムをシリコン単結晶中に侵入させ
る。 (1) 基板(下部電極板)温度:300℃ (2) 真空度:0.1〜0.5Torr (3) 印加電圧:直流400〜1000V (4) 使用不活性ガス:アルゴン 以下アルミニウムの侵入過程について説明す
る。まず第1図eに示した素子10を載置する下
部電極板12をモータ18を用いて300℃に加熱
しておく。この状態で排気系15を用いて
10-7Torr以下の高真空にした後、排気量調整バ
ルブ16とガス流量調整バルブ33を用いて反応
槽11内のアルゴン圧力を0.1〜0.5Torrに保つ。
ここで電極板12,13間に電源14を用いて
400〜1000Vの直流電圧を印加する。これにより
反応槽内電極間にグロー放電が生じ、この結果下
部電極板上部には極めて電界の強いクルツクス暗
部が形成される。第5図は第4図の素子10付近
の拡大図である。ここで、イオン化したアルゴン
35が陰極電極12に向かつて加速され、アルミ
ニウム6に衝突する作用によりシリコン単結晶1
中へアルミニウムが侵入し、族元素であるアル
ミニウムはアクセプタとして働くため、p+層6
1を形成するものと考えられる。またアルミニウ
ム膜6表面に衝突したアルゴンイオン35は、ア
ルミニウム膜6からアルミニウムを撥ね飛ばすよ
うに作用することも十分に考えられる。 このようにしてp+層61を形成した後、再度
アルミニウムを真空蒸着法により該p+層表面に
被着せしめ電極4とする。このようにして得られ
た半導体放射線検出器は、電極4とシリコン基板
1の界面のシヨツトキー障壁のみが減少しただけ
であるが、それでも印加電圧のほとんどを、単結
晶シリコンと非晶質シリコンのヘテロ接合部分に
印加しうるため、十分に結晶シリコン中に空乏層
を広げることが可能であるばかりでなく、従来シ
ヨツトキー障壁で発生していたノイズも抑制し得
ることにより、直接金属電極を形成した半導体放
射線検出基と比較してγ線およびβ線検出効率は
それぞれ15%、12%の向上が見られた。 次に本願第2発明の実施例として、第3図に符
号23で示したシヨツトキー障壁、すなわち非晶
質シリコンと金属電極の間のシヨツトキー障壁を
減少させたものについて述べる。第6図において
は第1図と同様の工程で被着比工程10kΩcm以上、
p型単結晶基板1の上にアンドープ非晶質シリコ
ン層2を被着させた後a,b、第6図cに示すよ
うに非晶質シリコン層2の表面にアンチモン1〜
10%を含む金の膜7を真空蒸着する。 次いで上述の実施例と同様に第4図に示す装置
を用いてアルゴンプラズマにより非晶質シリコン
層2の中にアンチモンを含んだ金を侵入させる。
この結果非晶質シリコン表面層はアンチモンの添
加によりn+層となり、金属−n+層−弱n型非晶
質シリコンの接合が形成され、シヨツトキー障壁
が低減される。この後さらに金−アンチモン膜7
の上に金蒸着をして電極3を形成する。しかし金
−アンチモン膜を厚くしてそのまま一方の電極と
して用いてもよい。このようにして作製した半導
体放射線検出器は、その電極3と非晶質シリコン
層2の界面のシヨツトキー障壁のみが減少しただ
けであるが、それでも非晶質シリコン層の上に直
接アルミニウム電極を設けた検出器と比較してγ
線およびβ線検出効率はそれぞれ5%、7%の向
上が見られた。 この実施例では非晶質シリコン層2をアンドー
プ非晶質シリコンによつて形成しているが、適応
した不純物をドーピングしてn型を強めた場合、
あるいはn型シリコン単結晶上にp型非晶質シリ
コン層を被着した場合にも、本発明により低温プ
ラズマプロセスによりそれぞれn+層あるいはp+
層を非晶質シリコン表面層に形成することも有効
である。
FIGS. 1a to 1e show most of the steps in the embodiment of the first invention of the present application. An undoped amorphous silicon layer 2 exhibiting weak n-type is deposited from monosilane gas by a known plasma CVD method on the upper surface of a p-type high-purity silicon single crystal substrate 1 with a specific resistance of 10 kΩcm or more as shown in FIG. 1a.b . Next, aluminum is deposited on the surface of the amorphous silicon layer 2 as a metal electrode 3c. Incidentally, the step c of providing the metal electrode 3 may be carried out after the low-temperature plasma treatment step explained later with reference to FIG. 4, and the process can proceed from the step b to the step d described below. Next, the substrate 1 is turned upside down (d), and an aluminum film 6 with a thickness of 0.01 to 0.1 μm is formed on the upper surface by vacuum evaporation (e). The device 10 that has undergone these steps is placed in the reaction tank 11 of the apparatus shown in FIG. 4, and the lower electrode plate 12 is placed with the aluminum film 6 facing upward.
Place it on top. The apparatus shown in FIG. 4 is also equipped with an upper electrode plate 13, a DC voltage power source 14, an exhaust system 15, a displacement adjustment valve 16, a vacuum gauge 17, a heater 18 for heating the lower electrode plate, and a heater power source 19. An inert gas cylinder 31 is connected to the tank 11 via a pressure reducing valve 32, a gas flow rate regulator 33, and a gas flow meter 34. Using the apparatus shown in FIG. 4, plasma is generated under the following conditions to cause aluminum to penetrate from the aluminum film 6 into the silicon single crystal. (1) Substrate (lower electrode plate) temperature: 300℃ (2) Degree of vacuum: 0.1 to 0.5 Torr (3) Applied voltage: DC 400 to 1000V (4) Inert gas used: Argon The process of aluminum penetration is explained below. . First, the lower electrode plate 12 on which the element 10 shown in FIG. 1e is mounted is heated to 300° C. using the motor 18. In this state, using the exhaust system 15,
After creating a high vacuum of 10 -7 Torr or less, the argon pressure in the reaction tank 11 is maintained at 0.1 to 0.5 Torr using the exhaust volume adjustment valve 16 and the gas flow rate adjustment valve 33.
Here, using the power supply 14 between the electrode plates 12 and 13,
Apply a DC voltage of 400 to 1000V. This causes a glow discharge between the electrodes in the reaction tank, and as a result, a Kurkus dark region with an extremely strong electric field is formed above the lower electrode plate. FIG. 5 is an enlarged view of the vicinity of the element 10 in FIG. 4. Here, the ionized argon 35 is accelerated toward the cathode electrode 12 and collides with the aluminum 6, causing the silicon single crystal 1
Aluminum penetrates into the p + layer 6 because aluminum, which is a group element, acts as an acceptor.
It is thought that it forms 1. It is also fully conceivable that the argon ions 35 colliding with the surface of the aluminum film 6 act to repel aluminum from the aluminum film 6. After forming the p + layer 61 in this manner, aluminum is again deposited on the surface of the p + layer by vacuum evaporation to form the electrode 4. In the semiconductor radiation detector obtained in this way, only the Schottky barrier at the interface between the electrode 4 and the silicon substrate 1 has been reduced, but most of the applied voltage is still Since the voltage can be applied to the junction, it is not only possible to sufficiently expand the depletion layer in the crystalline silicon, but also to suppress the noise that was previously generated by the Schottky barrier, making it possible to improve the performance of semiconductors with direct metal electrodes. Compared to the radiation detection group, the gamma-ray and beta-ray detection efficiencies were improved by 15% and 12%, respectively. Next, as an embodiment of the second invention of the present application, a structure in which the Schottky barrier shown at 23 in FIG. 3, that is, the Schottky barrier between the amorphous silicon and the metal electrode is reduced, will be described. In Figure 6, the deposition ratio is 10kΩcm or more in the same process as in Figure 1.
After depositing an undoped amorphous silicon layer 2 on a p-type single crystal substrate 1, antimony 1 to
A film 7 of gold containing 10% is vacuum deposited. Next, gold containing antimony is infiltrated into the amorphous silicon layer 2 by argon plasma using the apparatus shown in FIG. 4 in the same manner as in the above embodiment.
As a result, the amorphous silicon surface layer becomes an n + layer due to the addition of antimony, a metal-n + layer-weak n-type amorphous silicon junction is formed, and the Schottky barrier is reduced. After this, further gold-antimony film 7
Electrode 3 is formed by depositing gold on top of the electrode. However, the gold-antimony film may be made thicker and used as it is as one electrode. In the semiconductor radiation detector thus fabricated, only the Schottky barrier at the interface between the electrode 3 and the amorphous silicon layer 2 was reduced, but the aluminum electrode was still provided directly on the amorphous silicon layer. γ
The detection efficiency of rays and β rays was improved by 5% and 7%, respectively. In this embodiment, the amorphous silicon layer 2 is formed of undoped amorphous silicon, but if the n-type is strengthened by doping with an appropriate impurity,
Alternatively, even when a p-type amorphous silicon layer is deposited on an n-type silicon single crystal, the present invention can form an n + layer or a p+ layer , respectively, using a low-temperature plasma process.
It is also effective to form the layer on an amorphous silicon surface layer.

【発明の効果】【Effect of the invention】

以上説明したように、単結晶半導体と非晶質半
導体とのヘテロ接合に基づく空乏層への放射線の
入射により生ずる電気信号を利用した放射線検出
器の、単結晶および非晶質半導体に設ける電極と
の界面におけるシヨツトキー障壁を低減し、オー
ム接触に近づけるため、単結晶半導体基板あるい
は非晶質半導体層へ低温で生成されるプラズマの
エネルギで金属を侵入させて単結晶半導体基板表
面部あるいは非晶質半導体層の表面部にそれぞれ
高濃度不純物層を形成することにより、高純度の
半導体単結晶に対する高温処理の悪影響を避け、
短い処理時間、簡便な装置により低い費用で半導
体放射線検出器の検出効率を向上できる。
As explained above, the electrodes provided on the single crystal semiconductor and the amorphous semiconductor of the radiation detector that utilize the electric signal generated by the incidence of radiation into the depletion layer based on the heterojunction of the single crystal semiconductor and the amorphous semiconductor. In order to reduce the Schottky barrier at the interface and bring it closer to ohmic contact, metal is infiltrated into the single crystal semiconductor substrate or amorphous semiconductor layer using the energy of plasma generated at low temperature. By forming a highly concentrated impurity layer on the surface of each semiconductor layer, we can avoid the negative effects of high-temperature processing on high-purity semiconductor single crystals.
The detection efficiency of semiconductor radiation detectors can be improved at low cost with short processing time and simple equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本願第1発明の実施例の工程の一部を
示す断面図、第2図は本発明の対象である半導体
放射線検出器の断面図、第3図はそのエネルギ準
位図、第4は本願第1および第2発明の低温プラ
ズマ処理工程に用いられるプラズマ発生装置の一
例の構成説明図、第5図は第4図の装置の一部の
拡大断面図、第6図は本願第2発明の実施例の工
程の一部を順次示す断面図である。 1:p型単結晶シリコン板、2:非晶質シリコ
ン層、3,4:金属電極、6:アルミニウム膜、
61:p+層、7:金−アンチモン膜、10:素
子、11:反応槽、12,13:電極板、15:
排気系、31:不活性ガスボンベ。
FIG. 1 is a sectional view showing a part of the process of an embodiment of the first invention of the present application, FIG. 2 is a sectional view of a semiconductor radiation detector which is the object of the present invention, and FIG. 3 is an energy level diagram thereof. 4 is a configuration explanatory diagram of an example of a plasma generator used in the low-temperature plasma treatment process of the first and second inventions of the present application, FIG. 5 is an enlarged sectional view of a part of the apparatus of FIG. 4, and FIG. FIG. 2 is a cross-sectional view sequentially showing a part of the steps of the second embodiment of the invention. 1: p-type single crystal silicon plate, 2: amorphous silicon layer, 3, 4: metal electrode, 6: aluminum film,
61: p + layer, 7: gold-antimony film, 10: element, 11: reaction tank, 12, 13: electrode plate, 15:
Exhaust system, 31: Inert gas cylinder.

Claims (1)

【特許請求の範囲】 1 一導電形の高純度単結晶半導体基板の一主面
に逆導電形で高比抵抗の非晶質半導体層を被着
し、前記一主面に対向する前記半導体基板の他の
主面に不純物金属の膜を形成し、不活性ガスプラ
ズマ中で前記他の主面から前記半導体基板へ前記
不純物金属を侵入させて前記半導体基板と同一導
電形で不純物濃度の高い表面層を形成し、この表
面層上に前記不純物金属からなる電極を設ける、
ことを特徴とする半導体放射線検出器の製造方
法。 2 高純度単結晶半導体器板がp型シリコン基板
であり、不純物金属がアルミニウムであることを
特徴とする特許請求の範囲第1項に記載の半導体
放射線検出器の製造方法。 3 一導電形の高純度単結晶半導体基板の一主面
に逆導電形で高比抵抗の非晶質半導体層を被着
し、この非晶質半導体層上に不純物金属の膜を形
成し、不活性ガスプラズマ中で前記非晶質半導体
層の表面からこの非晶質半導体層へ前記不純物金
属を侵入させて前記非晶質半導体層と同一導電形
で不純物濃度の高い表面層を形成し、この表面層
上に前記不純物金属からなる電極を設ける、こと
を特徴とする半導体放射線検出器の製造方法。 4 非晶質半導体層が弱いn型の非晶質シリコン
層であり、不純物金属がアンチモンを含んだ金で
あることを特徴とする特許請求の範囲第3項に記
載の半導体放射線検出器の製造方法。
[Claims] 1. An amorphous semiconductor layer of an opposite conductivity type and high specific resistance is deposited on one main surface of a high-purity single crystal semiconductor substrate of one conductivity type, and the semiconductor substrate faces the one main surface. A film of an impurity metal is formed on the other main surface of the semiconductor substrate, and the impurity metal is allowed to enter the semiconductor substrate from the other main surface in an inert gas plasma to form a surface having the same conductivity type as the semiconductor substrate and having a high impurity concentration. forming a layer, and providing an electrode made of the impurity metal on this surface layer;
A method for manufacturing a semiconductor radiation detector, characterized in that: 2. The method for manufacturing a semiconductor radiation detector according to claim 1, wherein the high purity single crystal semiconductor plate is a p-type silicon substrate and the impurity metal is aluminum. 3. Depositing an amorphous semiconductor layer of opposite conductivity type and high specific resistance on one main surface of a high purity single crystal semiconductor substrate of one conductivity type, and forming an impurity metal film on this amorphous semiconductor layer, Intruding the impurity metal from the surface of the amorphous semiconductor layer into the amorphous semiconductor layer in an inert gas plasma to form a surface layer having the same conductivity type as the amorphous semiconductor layer and having a high impurity concentration; A method for manufacturing a semiconductor radiation detector, characterized in that an electrode made of the impurity metal is provided on this surface layer. 4. Manufacturing a semiconductor radiation detector according to claim 3, wherein the amorphous semiconductor layer is a weak n-type amorphous silicon layer, and the impurity metal is gold containing antimony. Method.
JP59260157A 1984-12-10 1984-12-10 Manufacture of semiconductor radiation detector Granted JPS61137373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59260157A JPS61137373A (en) 1984-12-10 1984-12-10 Manufacture of semiconductor radiation detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59260157A JPS61137373A (en) 1984-12-10 1984-12-10 Manufacture of semiconductor radiation detector

Publications (2)

Publication Number Publication Date
JPS61137373A JPS61137373A (en) 1986-06-25
JPH0543196B2 true JPH0543196B2 (en) 1993-06-30

Family

ID=17344105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59260157A Granted JPS61137373A (en) 1984-12-10 1984-12-10 Manufacture of semiconductor radiation detector

Country Status (1)

Country Link
JP (1) JPS61137373A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3678162B2 (en) * 2001-04-12 2005-08-03 株式会社島津製作所 Radiation detector

Also Published As

Publication number Publication date
JPS61137373A (en) 1986-06-25

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